NCD1015-IC 17 February 2011 Data sheet status: Product Data. NCD1015-IC HDX RFID IC. Product data February 2011 Production 1/14

Transcription

1 NCD1015-IC HDX RFID IC Product data February 2011 Production 1/14

2 NCD1015-IC HDX RFID IC 1 GENERAL DESCRIPTION The NCD1015-IC is a read/write IC to be used in HDX contact-less RFID devices for single transponder applications in the area of electronic animal identification operating in the low frequency (134.2 khz) range, supporting ISO 11784/85 standards. The NCD1015-IC contains 4 memory blocks of 33 bits each, based on field programmable, nonvolatile EEPROM. Each block contains 32 data bits (bit 1.. bit 32). Each of the blocks can be write protected through an associated lock bit, which is bit 0 of the corresponding block. Blocks 1 and 2 are referred to as the 64 bit identification data page 1 which is secured by an associated 16 bit CRC. Blocks 0 and 7 contain configuration parameters, as well as the option to irreversibly lock the RFID device. The HDX transponder IC receives Write Block requests from the reader as a pulse interval encoded, 100% amplitude modulated data signal. Return data transmission from the transponder to the reader utilises FSK encoded modulation. This is achieved by a serial data stream controlled Frequency Shift Keying (FSK) of the transponder s resonant circuit oscillation with an additional on-chip modulation capacitor between the two transponder terminals HF and GND. The passive transponder uses the supplied RF signal to obtain the energy needed to send the 64- bit ID code to the reader FEATURES Air Interface: Radio Frequency f C : Reader Tag transmission: Tag Reader transmission: Tag Reader data rate: Contact-less, sequential power & data transmission (HDX) khz typically Pulse interval encoding (PIE) ~ kbit/s FSK modulation, NRZ: 0 ~134.2 khz; 1 ~124.2 khz RF/16 (~ 8 kbit/s) On chip 16 bit CRC generator: Reverse CRC-CCITT as used in ISO/IEC On chip integrated modulation cap. C 1 : Identification data page: ~110 pf; f mod1 ~10kHz with f C = khz 64 bits data + associated 16 bits CRC 2/14

3 2 APPLICATION DIAGRAM NCD1015-IC is designed to be used in a complete RFID HDX. Only 1 inductor to operate as antenna and 2 external capacitors are needed for the RFID front-end to operate. Figure 1 shows the NCD1015-IC and the connections with the external components. ZAP and ZAP_SEL pins are used only for resonance frequency trimming, not for the final application. Typical values are: L = 2.41 mh CR = 470 pf (it is recommended to use a 470 pf ±2 % 50 V external SMD NP0 / C0G capacitor) CL = 220 nf (it is recommended to use a ±5 % 10 V capacitor) VDD ZAP_SEL CL CR L NCD1015 HF GND ZAP Figure 1: Application diagram 3 PIN DESCRIPTION Name VDD GND HF ZAP_SEL ZAP Description Voltage supply Ground Oscillating signal Clock for the trimming Voltage for the trimming Table 1: Pin description 4 FUNCTIONAL OVERVIEW AND DESCRIPTION 4.1 POWER TRANSFER Power transfer to the tag is accomplished by magnetic coupling of the transponder and reader antenna. The reader and the transponder operate in a sequential mode with timely separated power and data transmission cycles. The RF operating field supplies power at the beginning of the request from the reader to the HDX transponder. During the charge (or powering phase) of between 15 and typically 50 ms the reader generates an electromagnetic field using a frequency of khz. The resonant circuit of the transponder is energised 3/14

4 and the induced voltage is rectified by the integrated circuit to charge the capacitor C L. The transponder detects the end of the charge burst (EOB) and transmits its data using Frequency Shift Keying (FSK), utilising the energy stored in the capacitor C L. The charge phase is followed directly by the read phase. Figure 2: Charge and Read Phase - Voltage at the reader s exciter and transponder coil 4.2 COMMUNICATION SIGNAL INTERFACE - TAG TO READER FREQUENCY The tag shall be capable to communicate with the reader via an inductive coupling, whereby the power is switched off and the data are FSK modulated using the frequencies: f 0 = for the data Low Bit encoding f 1 = for the data High Bit encoding (ISO tolerance) (ISO tolerance) f 1 represents the frequency for data bit 1 (T d1 = 16/f 1 ) and f 0 for the data bit 0 (T d0 = 16/f c ). The low and high bits have different duration, because each bit takes 16 RF cycles to transmit. The high bit has a typical duration of ~130 µs, the low bit of ~120 µs. Figure 3 shows the FSK encoding principle used. 4/14

5 Figure 3: FSK transmission used during the read phase TRANSPONDER DATA RATE AND DATA CODING The data coding is based on the NRZ method thus achieving an average data rate of ~ 8 kbit/s based on an equal distribution of 0 and 1 data bits. 4.3 COMMUNICATION SIGNAL INTERFACE - READER TO TAG MODULATION Communication between reader and transponder takes place using ASK modulation of the RF field with a modulation index of ~100%. The carrier frequency of the RF operating field is f C = khz READER DATA RATE AND DATA CODING The reader to transponder communication uses Pulse Interval Coding (PIC). The reader creates pulses by switching the carrier on and off as described above. The modulation index of this amplitude modulation is 90_% to 100_%. The time between the falling edges of the pulses determines either the value of the data bit "0" and "1", a Code violation or a Stop (EOF) condition. T 1 separates the single intervals. Its duration is T 1 <= 40 T C. 5/14

6 T d0 Data "0" TX ON TX OFF T d1 Data "1" TX ON TX OFF T 1 T CV Code violation TX ON TX OFF Figure 4: Reader to Tag - Pulse interval modulation and encoding Symbol Fast data rate min nom max T d0 42 T c 47 T c 52 T c T d1 62 T c 67 T c 72 T c T CVF /T CVS 175 T c 180 T c 185 T c Table 2: Reader - Data Coding Times NOTE: T c =1/f c µs The default PIC threshold is configured for a medium data rate of 2.35 kbit/s, realised for example with a low bit period of T d0 = 350 µs and a high bit period of T d1 = 500 µs. The regenerated clock is available continuously during T Start Of Frame and End Of Frame pattern The reader request starts always with a Start of Frame (SOF) pattern. The SOF pattern as shown in Figure 5 consists the "Code violation" pattern T CVS which defines a clear start of frame. Figure 5: Reader to Tag Encoding of Start of Frame The End of Frame (EOF) condition of any reader request is defined as the rising edge of the RF field followed by a RF field activation time (T eoff ) longer than the maximum T d1 value (72 clock cycles). 6/14

7 Figure 6: Reader to Tag Encoding of End of Frame WRITE PHASE AND THE PROGRAMMING OF DATA A new identification number can be programmed into the OTP transponder in the following manner: After the charge phase, the transponder enters the write mode provided that the reader starts to modulate the field by switching the transmitter on and off. Writing means, the transponder shifts the received bits into an internal shift register. After the write phase the reader's transmitter is switched on for the EEPROM programming time in order to energise the process of programming the shift register s data into the EEPROM. Each 33 data bits of a block including the lock bit - are programmed simultaneously into the EEPROM. Figure 7: Charge, Write and Program - Voltage at the reader and transponder antenna coil As illustrated in Figure 7 the EEPROM programming sequence consists of: Charge phase: Write phase: Programming phase: Read phase: Continuous reader (RF Module) transmitter output signal Pulse interval encoding of the reader s transmitter output signal Continuous RF transmitter output FSK modulation of the transponder s resonant circuit oscillation 7/14

8 5 TRANSMISSION PROTOCOL The transmission protocol defines the mechanism to exchange requests and data between the reader and the transponder. The reader always starts the transmission, and the transponder does not start transmitting its response until the reader s RF field is turned off. The different data exchanges that can happen between reader and transponder are summarized in the lines below: The requests that can be performed by the transponder built using NCD1015-IC are as follows: Charge Only Read The content of page 1 is read without any specific page address by just charging (powering-up) the transponder for up to 50 ms.(iso compatibility mode). Write Block Following the command and the block address, the lock bit(s) and the 32 data bits to be programmed with the associated 16 CRC bits are sent to the transponder. The 32 data bits together with the associated lock bit are written into the specified block simultaneously. Transponder response starts after the RF field is turned off. Note: Each data block can be locked by setting the associated lock bit in order to create a read only access and to disable further re-programming of this block. Note: After writing block1 and block2, it is recommended to send a Charge Only Read command to verify successful writing. 5.1 DATA FORMAT DEFINITIONS READER COMMAND - REQUEST FORMAT A Charge-Read Only request is generated by just charging the transponder: The demodulator must start working once the reader stops generating electromagnetic field. It counts the number of cycles while the electromagnetic field is low, if that number T 1 is larger than 40 T c, the tag will respond to a Charge-Read Only request. If the T 1 duration is not larger than 40 T c, the system has to wait for a Reader Request Frame (RRF). The Reader Request Format as sent by the reader is shown in Figure 8. SOF COM ADR DATA CRC EOF LSB LSB 55 Figure 8: Reader Request Frame format All signals are coded [MSB;LSB]. SOF Start of Frame pattern COM Command [3; 0] ADR Address [3; 0] DATA Data [31; 0] CRC ICRC [15; 0] EOF End of Frame pattern The length of the frame varies with the different commands. 8/14

9 Command Table The NCD1015-IC first evaluates the command byte which consists of an address field in the MSN (Most Significant Nibble) and a 4-bit command code of the incoming RRF according to Table 3. All other bit combinations may be considered as illegal. ADDRESS COMMAND DESCRIPTION MSB LSB Write Write Block 0 Management register Write Block 1 Identification Data/ LSB Write Block 2 Identification Data/ MSB Write Block 7 Configuration Register Write & Lock Write & Lock Block 0 Management register Write & Lock Block 1 Identification Data/ LSB Write & Lock Block 2 Identification Data/ MSB Write & Lock Block 7 Configuration Register Table 3: RRF Commands in normal mode TRANSPONDER RESPONSE DATA FORMAT Tag Response Frame Format Any RFID answer is framed as shown in Figure 9 and it has a fixed length of 112 bits. Depending on the type of answer the STOP and POST bits change. START DATA CRC STOP POST LSB LSB Figure 9: Tag Response Frame format All signals are coded [MSB;LSB]. START Start Byte [7; 0] DATA Data [63; 0] := 7E hex := Data CRC DCRC [15; 0] := Data CRC STOP Stop Byte [7; 0] POST Post Bits [15; 0] STOP Byte content answering a CRO := ADDRESS + STATUS in all other cases page status information := 0000 hex The content of page 1 is sent during the response (ISO compatibility mode). The Stop Byte information will be coded following Table 4. ADDRESS STATUS DESCRIPTION MSB LSB page unlocked block 1 (LSB) locked + block 2 (MSB) unlocked block 1 (LSB) unlocked + block 2 (MSB) locked block 1 (LSB) locked + block 2 (MSB) locked + BIT16 ISO11785 = block 1 (LSB) locked + block 2 (MSB) locked + BIT16 ISO11785 = 1 Table 4: Status Answer following a CRO command 5.2 CRC-CCITT ERROR CHECKING The CRC error checking circuitry generates a 16 bits CRC to ensure the integrity of transmitted and received data packets. The reader and transponder use the CRC-CCITT (Consultative Committee for International Telegraph and Telephone) for error detection. 9/14

10 The 16 bits Write Frame BCC is generated by the transponder on reception of the complete write data stream to validate the correct data transmission. Data in P (X) = X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 LSB MSB Figure 10: Schematic diagram of the 16 bits CRC-CCITT generator The 16 bits cyclic redundancy code is calculated using the following polynomial with an initial value of 0000 HEX : P(X) = x 16 + x 12 + x 5 + x 0 The implemented version of the CRC check has the following characteristics: Reverse CRC-CCITT 16 as described in ISO/IEC and used in ISO/IEC 11784/11785 The CRC 16 bit shift register is initialised to all zeros at the beginning of a request The incoming data bits are XOR-ed with the MSB of the CRC register and is shifted into the register s LSB After all data bits have been processed, the CRC register contains the CRC-16 code. Reversibility - The original data together with associated CRC, when fed back into the same CRC generator will regenerate the initial value (all zero s). 10/14

11 6 MEMORY 6.1 MEMORY BLOCK The memory is structured into 8 Blocks of 32 bits each. In addition a Lock Bit is provided as Bit 0 corresponding to each Block. Two Blocks form one Page, of which 2 exist. Block Address Page Address Description 0 4 Management Register/ MSB 1 Identification Data/ LSB 1 2 Identification Data/ MSB 7 4 Configuration Register/ LSB Table 5: Memory organization Page 1 Identification Data Page 1 is used for the Identification Data as specified in ISO/ IEC This page is locked if the Lock Bits of the corresponding Blocks are set to 1. If the Page is locked, the stored value can not be overwritten Page 4 Configuration Register + Management Register Page 4 consists of Block 0, which is the Management Register, as the Most Significant Bits and the Block 7, which is the Configuration Register as the Least Significant Bits of it.. This Page is locked if the Lock Bits of the corresponding Blocks are set to 1. If the Page is locked, the stored value can not be overwritten. Configuration Register The configuration register (CREG) layout is depicted in Figure 11. If the flag DISCH is 1 and the system is in Normal Mode, the storage capacitance is not going to be discharged. The trimming bits specify the trimming vector for the capacitor in the analog part. LOCK: Lock bit DISCH LOCK Figure 11 Configuration register (CREG) layout DISCH: Discharge ( 0 discharge, 1 no discharge) Management Register The management register (MREG) contains information about the current state of the system. XX MGM KEY LOCK Figure 12 management register (CREG) layout LOCK: Lock bit XX: Undefined MGM KEY: Management key [3:0] The contents of the Management key are explained in Table 6. 11/14

12 Normal mode Key Value Description MSB LSB 0000 Normal Mode by default 0110 All Blocks Locked Table 6 MGM content In Normal mode all the commands explained before are valid. All blocks locked Blocking MREG while the Management key has the 0110 value ( All Blocks Locked ) leads to the All Blocks Locked state. In this state the memory is protected against writing and this is an irreversible state. 12/14

13 7 SPECIFICATIONS 7.1 MECHANICAL DATA Parameter Limits Unit min typ max Wafer thickness 470 m Bump height m Shear strength 3 mg/um 2 Hardness HV 7.2 ELECTRICAL DATA OPERATING CONDITIONS Parameter Limits Unit min max Operating Temperature C Storage Temperature C Parameter Limits Unit Conditions min typ max HF limiter current 4 A VHF = 5 V HF maximum voltage 12 V IHF = 10 ma Quiescent current consumption 5 A VCL = 5.5 V Internal HF capacitor 117 pf All trimming caps connected Modulation capacitor 110 pf Endurance 100 k cycles Data retention 10 years 8 ORDERING INFORMATION MPN Description Order code Package NCD1015- WBUS470XN_ch NCD1015-IC bumped NCD1015- WBUS470XN_ch Bumped chips in 6 wafer, sawn in blue foil, 470 m thickness, 8 metal disco frame, with wafermap (not inked) 13/14

14 Level Data Sheet Status [1] I Objective data Development II Preliminary data Product Status [2][3] Definitions Qualification This data sheet contains data for the objective specification for product development. This data sheet contains data from the preliminary specification. Supplementary data will be updated at a later date III Product data Production This data sheet contains data from the product specification. Disclaimers LIFE SUPPORT- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. IXYS San Sebastian customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify IXYS San Sebastian for any damages resulting from such an application. RIGHT TO MAKE CHANGES- IXYS San Sebastian reserves the right to make changes in the products including circuits, standard cells, and/or software- described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). IXYS San Sebastian assumes no responsibility or liability for the use of any of these products, conveys no license of title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. LIMITATION OF LIABILITY.- Liability of seller to buyer for damages for any cause whatsoever, and regardless of the form of any action, whether in contract or in tort, including, but not limited to negligence shall be limited to the price specified in the sale contract for the specific product or products that caused the damages or that are the subject matter of, or are directly or indirectly related to the cause of action. In no event shall seller be liable to buyer or others for loss of goodwill, loss of profits, loss of use or other special collateral, incidental or consequential damages, regardless of the form of action thereof, whether in contract or in tort, including but not limited to negligence, even if seller has been advised of the possibility of such damages or for any claim against buyer by any third party. Buyer assumes all liability for any and all damages arising from or in connection with, the use or misuse of the products by buyer, its employees, or others. Contact information: For additional information please contact info@ixys.es [1] Please consult the most recently issued data sheet before initiating or completing a design [2] The product status of the device[s] described in this data sheet may have changed since this datasheet was published. The latest information is available by contacting IXYS San Sebastian [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 14/14