ic-lta 6-CH. INCREMENTAL OPTO ENCODER ARRAY

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1 Rev C2, Page 1/15 FEAURES Monolithic photodiode array with excellent signal matching Very compact size for small encoders Moderate track pitch for relaxed assembly tolerances Low noise signal amplifiers with high EMI tolerance Pin-selectable operating modes: analog, comparated (x1), interpolated (x2, x4) Pin-selectable index gating: ungated (1 ), B-gated (0.5 ), AB-gated (0.25 ) Complementary quadrature outputs: A, B, Z and NA, NB, NZ Commutation signal outputs: U, V, W Short-circuit-proof, current-limited, +/- 4 ma push-pull Analog signal output for ease of alignment and resolution enhancement by external interpolation LED power control with 40 ma high-side driver Low power consumption from single 3.5 V to 5.5 V supply Operating temperature range of -40 C to +120 C Space saving optoqfn / optobga packages (RoHS compliant) Custom made code disc and reticle designs on request APPLICAIONS Incremental encoder Brushless DC motor commutation Industrial drives CKAGES 32-pin optoqfn 5 mm x 5 mm x 0.9 mm 15-pin optobga 6.2 mm x 5.2 mm x 1.7 mm BLOCK DIAGRAM V C1 1μF NA NB IP IN SIGNAL COMRAION AND QUADRAURE OUPU LED POWER CONROL LED NA NB D1 R1 47 NZ INDEX OUPU NZ POWER-ON RESE U V - + U V W COMMUAION W Copyright 2010, 2019 ic-haus

2 Rev C2, Page 2/15 DESCRIPION represents an advanced optical encoder IC featuring an array of integrated photosensors evaluated by a fast on-chip interpolation circuit to higher resolution. Its typical application are incremental encoders for motor speed control and commutation. o this end, the device provides differential A/B tracks, a differential index track and three more tracks to generate block commutation signals. he optical radius and the native cycles per revolution (CPR) can be freely determined by the applied code design, i.e. the code wheel and reticle (applied externally, or molded to IC as package option). he adaption to the motor polecount is also carried out by the code disc, for instance with 4 CPR and 90 degree phase shift to operate 4-phase brushless motors. Low-noise transimpedance amplifiers, arranged in a paired layout to ensure excellent channel matching, are used to convert the scanner s signals into voltages of several hundred millivolts 1. Precision comparators with hysteresis generate the digital signals subsequently, either native or interpolated, which are then output by differential ± 4 ma push-pull drivers. he built-in averaging LED power controller with its 40 ma driver permits a direct connection of the encoder LED. he received optical power is kept constant regardless of aging effects or changes in temperature. Various operating modes are selectable at multi-level input 2 : digital output with native (x1) or interpolated resolution (x2 or x4), analog output or mixed analog/digital output; the latter combines an output of sine/cosine signals with comparated UVW commutation signals. During analog operation the amplified signal voltages are available at the outputs for inspection and monitoring of encoder assembly, or to feed external interplation circuits. Index gating is also pin-selectable at input 2, 3 : the options are ungated, respectively -gated if using interpolated output, B-gated and AB-gated. he device runs at single-sided supplies from 3.5 V up to 5.5 V and features a low power consumption. 1 Operating point varies by code design applied. 2 For ease of replacement, the pin functions of chip release W are backwards compatible to chip release X, and compatible to ic-p H-Series devices. 3 Pin is not available on the obga LSH2C package (AB-gated index output is preset).

3 Rev C2, Page 3/15 CKAGING INFORMAION Chip Layout Chip release W1, chip size 2.88 mm x 3.37 mm x x x x0.330 (4x) 1.720x (2x) U V W NB NA NZ DEAIL (2x) SCALE 100 : (*) (*): VS. CENER OF CHIP dra_lta_w_chip_1, 20:1

4 PIN CONFIGURAION obga LSH2C (6.2 mm x 5.2 mm) A B C D <P-CODE> <A-CODE> PIN FUNCIONS No. Name Function A2 A3 LED A4 B1 B2 NA B3 IP B4 U C1 C2 NB C3 IN C4 V D1 D2 NZ D3 D4 W Rev C2, Page 4/ V Supply Voltage LED Controller, High-Side Current Source Output Ground Push-Pull Output A+ (Sin+) Push-Pull Output A- (Sin-) Positive est Current Input Push-Pull Output U Push-Pull Output B+ (Cos+) Push-Pull Output B- (Cos-) Negative est Current Input Push-Pull Output V Push-Pull Output Z+ (Index+) Push-Pull Output Z- (Index-) OOp. Mode Selection Input: 100% = x2 interpolated 75% = ABZ analog, UVW digital 50% = ABZ, UVW analog 25% = x4 interpolated 0% = x1 interpolated Push-Pull Output W Note that this package does not feature pin, and AB-gated index output is preset. For dimensional specifications refer to the relevant package data sheet, available separately.

5 PIN CONFIGURAION oqfn32-5x5 (5 mm x 5 mm) <A-CODE> <P-CODE> PIN FUNCIONS No. Name Function Rev C2, Page 5/ V Supply Voltage 2 LED LED Controller, High-Side Current Source Output 3 Push-Pull Output A+ / Analog Sin+ 1 4 NA Push-Pull Output A- / Analog Sin- 5 Push-Pull Output B+ / Analog Cos+ 6 NB Push-Pull Output B- / Analog Cos- 7 Push-Pull Output Z+ / Analog Z+ 8 NZ Push-Pull Output Z- / Analog Z n.c Op. Mode Selection Input: 100% = x2 interpolated 75% = ABZ analog, UVW digital 50% = ABZ, UVW analog 25% = x4 interpolated 0% = x1 interpolated 18 W Push-Pull Output W / Analog W 19 IN Negative est Current Input 3 20 V Push-Pull Output V / Analog V 21 IP Positive est Current Input 3 22 U Push-Pull Output U / Analog U 23 Index Length Selection Input: lo = 0.5 (B-gated), hi = 1 (ungated/-gated), open = 0.25 (A and B-gated) 24 Ground n.c. BP Backside Paddle 4 IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes); 1 Capacitive pin loads must be avoided when using the analog output signals. 2 Pin numbers marked n.c. are not connected. 3 he test pins IP and IN may remain unconnected. If connecting traces, ensure a proper ground level to avoid unwanted functions. 4 Connecting the backside paddle is recommended by a single link to. A current flow across the paddle is not permissible.

6 Rev C2, Page 6/15 CKAGE DIMENSIONS oqfn32-5x5 RECOMMENDED PCB-FOOPRIN R0.15 OP SIDE 0.90 ± BOOM All dimensions given in mm. olerances of form and position according to JEDEC MO-220. olerance of sensor pattern: ±70μm / ±1 (with respect to center of backside pad). Maximum molding excess +20μm / -75μm versus surface of glass/reticle. dra_oqfn32-5x5-2_lta_w_pack_1, 10:1

7 Rev C2, Page 7/15 ABSOLUE MAXIMUM RAINGS hese ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur. Item Symbol Parameter Conditions Unit No. Min. Max. G001 Voltage at V G002 I() Current in ma G003 V() G004 I() Voltage at Output Pins, NA,, NB,, NZ, U, V, W Current in Output Pins, NA,, NB,, NZ, U, V, W V ma G005 V() Voltage at LED V G006 I() Current in LED ma G007 V() Voltage at IP, IN,, V G008 I() Current in IP, IN,, ma G009 Vd() ESD Susceptibility at all pins HBM, 100 pf discharged through 1.5 kω 2 kv G010 j Junction emperature C HERMAL DAA Operating conditions: = V Item Symbol Parameter Conditions Unit No. Min. yp. Max. 01 a Operating Ambient emperature Range package oqfn32-5x5, obga LSH2C C 02 s Permissible Storage emperature Range package oqfn32-5x5, obga LSH2C C 03 pk Soldering Peak emperature package obga LSH2C; tpk < 20 s, convection reflow 245 C tpk < 20 s, vapor phase soldering 230 C OL (time on label) 8 h; Please refer to customer information file No. 7 for details. 04 pk Soldering Peak emperature package oqfn32-5x5; tpk < 20 s, convection reflow 245 C tpk < 20 s, vapor phase soldering 230 C MSL 5A (max. floor live 24 h at 30 C and 60 % RH); Please refer to customer information file No. 7 for details. All voltages are referenced to ground unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.

8 Rev C2, Page 8/15 ELECRICAL CHARACERISICS Operating conditions: = V, j = C, λ LED = λr = 740 nm, unless otherwise noted Item Symbol Parameter Conditions Unit No. Min. yp. Max. otal Device 001 Permissible Supply Voltage V 002 I() Supply Current in no load, photocurrents within op. range 6 10 ma Photosensors 101 λar Spectral Application Range Se(λar) = 0.25 x S(λ)max nm 102 λpk Peak Sensitivity Wavelength 680 nm 103 Aph() Radiant Sensitive Area,, NA, NB mm 2, NZ 0.26 mm 2 U, V, W mm S(λr) Spectral Sensitivity λ LED = 740 nm 0.5 A/W λ LED = 850 nm, 460 nm 0.3 A/W 106 E()mxpk Permissible Irradiance λ LED = λpk, Vout() < Vout()mx;,, NA, NB 1.0 mw/ cm 2 U, V, W 2.5 mw/ cm 2, NZ 0.4 mw/ cm 2 Photocurrent Amplifiers 201 Iph() Permissible Photocurrent Operating Range 202 η()r Photo Sensitivity (light-to-voltage conversion ratio) for,, NA, NB, U, V, W na for, NZ na for,, NA, NB, U, V, W V/µW for, NZ V/µW 203 Z() Equivalent ransimpedance Gain Z = Vout() / Iph(), j = 27 C; for,, NA, NB, U, V, W MΩ for, NZ MΩ 204 CZ emperature Coefficient Of ransimpedance Gain %/ C 205 Z()pn ransimpedance Gain Matching open, P vs. N path per diff. channel % 206 Vout() Dark Signal Matching of A, B open, output vs. output -8 8 mv 207 Vout() Dark Signal Matching of U, V, W open, output vs. output mv 208 Vout() Dark Signal Matching of A, B, Z, U, V, W open, any output vs. any output mv 209 Vout()pn Dark Signal Matching open, P vs. N path per diff. channel mv 211 fc()hi Cut-off Frequency (-3 db) khz Analog Outputs:, NA,, NB,, NZ, U, V, W 301 Vout()mx Permissible Maximum Output Voltage 302 Iout()mx Permissible Maximum Output Load illumination to E()mxpk 1.8 V sink current (load to IC) 50 µa source current (load to ground) -500 µa 303 Vout()d Dark Signal Level load 100 kω vs. +2 V mv 304 Vout()acmx Maximum Signal Level Vout()acmx = Vout()mx - Vout()d V 307 Ri() Internal Output Resistance f = 1 khz Ω Comparators 401 Vt()hys Comparator Hysteresis Vt()hys = Vt()hi - Vt()lo 24 mv LED Power Control 501 Iop() Permissible LED Output Current ma 502 Vs()hi Saturation Voltage hi Vs()hi = - V(LED), I() = -40 ma V 503 Isc()hi Short-Circuit Current hi V() = 0 V ma Digital Outputs:, NA,, NB,, NZ, U, V, W 601 fout Maximum Output Frequency x1 comparated (native resolution) 400 khz x2 interpolated 800 khz x4 interpolated 1600 khz 602 AArel Relative Angular Accuracy AC signal >200 mvpp, comparated or interpolated, see Figure %

9 Rev C2, Page 9/15 ELECRICAL CHARACERISICS Operating conditions: = V, j = C, λ LED = λr = 740 nm, unless otherwise noted Item Symbol Parameter Conditions Unit No. Min. yp. Max. 603 Vs()lo Saturation Voltage lo = V, I() = 4mA, j = 70 C 0.4 V = V, I() = 4mA, j = 85 C 0.5 V = V, I() = 4mA 0.6 V 604 Isc()lo Short-Circuit Current lo V() = 7 70 ma 605 Vs()hi Saturation Voltage hi Vs()hi = - V(), I() = -4 ma; = V 0.4 V = V 0.6 V 606 Isc()hi Short-Circuit Current hi V() = 0 V ma Operating Mode Selection Input: 701 Vmod() Mode Selection (see Figure 2) x2 interpolated % analog ABZ, digital UVW % all analog % x4 interpolated % x1 comparated (native resolution) 0 5 % 702 Vmod()hys Hysteresis 10 % 703 V0() Pin-Open Voltage % 704 Rpd() Pull-Down Resistor to, V() = 65 kω 705 Rpu() Pull-Up Resistor to, V() = 0 V 65 kω Index Gating Selection Input: 801 Vgate() Gating Selection (see Figure 3) ungated (1 with interpolation) % AB-gated (0.25 ) % B-gated (0.5 ) 0 18 % 802 Vgate()hys Hysteresis 10 % 803 V0() Pin-Open Voltage for index length 0.25 (AB-gated) % 804 Rpu() Pull-Up Resistor to, V() = 0 V 65 kω 805 Rpd() Pull-Down Resistor to, V() = 65 kω Power-On-Reset Circuit 901 on urn-on hreshold (power-on release) 902 off urn-off hreshold (power-down reset) increasing voltage at V decreasing voltage at V 903 hys hreshold Hysteresis hys = on - off mv est Inputs: IP, IN Z01 Ipd() Pull-Down Current test mode not active; V() = 0.4 V µa V() = µa Z02 It()on est Mode Activation hreshold µa Z03 V()test est Pin Operating Voltage test mode active, I() = 200 µa V Z04 I()test Permissible est Current test mode active µa Z05 CR() Current Ratio I()test/Iph() test mode active, I() = 200 µa 1000 ELECRICAL CHARACERISICS: Diagrams 0% 50% 100% ± AArel Figure 1: Definition of relative angular accuracy AArel

10 Rev C2, Page 10/15 Vmod() x2 interpolated undefined ABZ analog UVW digital undefined ABZ, UVW analog undefined x4 interpolated undefined x1 interpolated Vgate() ungated undefined AB-gated undefined B-gated Figure 2: Operating mode selection at pin. Figure 3: Index gating selection at pin.

11 Rev C2, Page 11/15 DIGIAL OUPU SIGNALS U V W AB-gated B-gated ungated /4 /4 /4 /4 ö C C/6 C/6 C/6 C/6 C/6 C/6 s photo-sensor array requires an external reticle (placed either on side of the IC or on side of the LED), and thus allows for a free definition of the optical radius and cycles per revolution for the A and B encoder quadrature signals. he pulse count, period length and phase shift for the U, V, W commutation signals is also determined by the code disc design. Contracted code disc designs and IC packaging with custom reticle can be offered on request; contact ic-haus for details. Figure 4: ypical encoder quadrature and motor commutation signals. ANALOG OUPU SIGNALS R1 U R1 U R2 R2 Figure 5: Example of analog ABZ / analog UVW (pin = 50% ) Figure 6: Example of analog ABZ / digital UVW (pin = 75% ) features 5 principle operation modes which are selectable by the voltage applied to pin. A voltage divider as suggested by able 4 is the easiest way to obtain this. R1 1) R2 1) Operation Mode 100 % 0 Ω open x2 interpolated 75 % 2.7 kω 8.2 kω analog ABZ, dig. UVW 50 % 4.7 kω 4.7 kω all analog (open) (open) 25 % 8.2 kω 2.7 kω x4 interpolated 0 % open 0Ω x1 comparated 1) Exemplary values. able 4: Selection of operation mode by pin. If input is left open, the IC biases its input at 50% and analog output signals are available for test and alignment. Analog output signals may also be used to increase the encoder s resolution by connecting an external interpolation IC. In this case the analog signals are required permanently, so that noise immunity should be improved by wiring pin to an external reference providing /2. Setting 75 % may be considered to obtain analog signals at // and NA/NB/NZ outputs feeding the external interpolation IC, together with digital signals at U/V/W directly connecting a line driver. Special attention to the PCB layout should be paid to avoid cross talk; analog and digital lines should be separated carefully.

12 Rev C2, Page 12/15 INDEX GAING AND INERPOLAION RA RB /4 /4 /4 /4 /4 /4 /4 /4 Figure 7: Ungated index ( = high), x1 comparated ( = low). Figure 12: AB-gated index ( = open or /2), x2 interpolated ( = high). /4 /4 /4 /4 R1 /4 /4 /4 /4 Figure 8: B-gated index ( = low), x1 comparated ( = low). R2 Figure 13: -gated index ( = high), x4 interpolated ( = 25% ). RA RB /4 /4 /4 /4 R1 /4 /4 /4 /4 Figure 9: AB-gated index ( = open or /2), x1 comparated ( = low). /4 /4 /4 /4 Figure 10: -gated index ( = high), x2 interpolated ( = high). R2 Figure 14: B-gated index ( = low) x4 interpolated ( = 25% ). R1 R2 RA RB /4 /4 /4 /4 Figure 15: AB-gated index ( = open or /2) x4 interpolated ( = 25% ). /4 /4 /4 /4 Figure 11: B-gated index ( = low), x2 interpolated ( = high).

13 Rev C2, Page 13/15 ES MODE ungated AB-gated B-gated OFF S1 S2 S3 S4 S5 OFF Figure 16: Output states during test mode ( = low: x1 comparated) State I(IP) I(IN) Function Wiring Instruction OFF I(IP) 10 µa I(IN) 10 µa Normal operation S1 I(IP) 190 µa I(IN) 190 µa est mode activation I(IP) 300 µa I(IN) 300 µa (low-level at, ) Pull-up IN and IN by 10 kω each to 5 V. S2 I(IP) 700 µa I(IN) 300 µa Force high-level at Add pull-up to IP of 4.7 kω to 5 V. S3 I(IP) 700 µa I(IN) 700 µa Force high-level at,, Add pull-up to IN of 4.7 kω to 5 V. S4 I(IP) 300 µa I(IN) 700 µa Keep high-level at (and if B-gated) Disconnect 4k7 pull-up from IP. S5 I(IP) 300 µa I(IN) 300 µa (low-level at all outputs) Disconnect 4k7 pull-up from IN. OFF I(IP) 10 µa I(IN) 10 µa Normal operation All pull-ups removed. able 5: Selection of output states. DESIGN REVIEW: Notes on Chip Functions _X No. Function, Parameter/Code Description and Application Hints Refer to datasheet release B1, 2013 able 6: Chip release _X _W1 No. Function, Parameter/Code Description and Application Hints None at time of printing. able 7: Chip release _W1

14 Rev C2, Page 14/15 APPLICAION CIRCUIS Please refer to ic-pxx series IC s application notes which are available separately. REVISION HISORY Rel. Rel. Date 1 Chapter Modification Page C all New release for s advanced chip releases W, W1. all Rel. Rel. Date 1 Chapter Modification Page C xx ABSOLUE MAXIMUM RAINGS Item G007, G008: pin added; Redundant item G011 (s) deleted DESIGN REVIEW: Notes on Chip Functions Chip release W corrected to W1 13 ORDERING INFORMAION P/O code updated for eval board (L4RS) 15 7 ic-haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the relevant current specifications on our internet website and is automatically generated and shall be sent to registered users by . Copying even as an excerpt is only permitted with ic-haus approval in writing and precise reference to source. he data specified is intended solely for the purpose of product description and shall represent the usual quality of the product. In case the specifications contain obvious mistakes e.g. in writing or calculation, ic-haus reserves the right to correct the specification and no liability arises insofar that the specification was from a third party view obviously not reliable. here shall be no claims based on defects as to quality in cases of insignificant deviations from the specifications or in case of only minor impairment of usability. No representations or warranties, either expressed or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. ic-haus products are not designed for and must not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (Safety-Critical Applications) without ic-haus specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems. ic-haus products are not designed nor intended for use in military or aerospace applications or environments or in automotive applications unless specifically designated for such use by ic-haus. ic-haus conveys no patent, copyright, mask work right or other trade mark right to this product. ic-haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. Software and its documentation is provided by ic-haus GmbH or contributors "AS IS" and is subject to the ZVEI General Conditions for the Supply of Products and Services with ic-haus amendments and the ZVEI Software clause with ic-haus amendments ( 1 Release Date format: YYYY-MM-DD

15 Rev C2, Page 15/15 ORDERING INFORMAION ype Package Options Order Designation 15-pin optobga, 6.2 mm x 5.2 mm, thickness 1.7 mm AB-gated index, glass lid obga LSH2C AB-gated index, on-chip reticle obga LSH2C-xR 32-pin optoqfn, 5 mm x 5 mm, thickness 0.9 mm selectable index gating, glass lid selectable index gating, on-chip reticle oqfn32-5x5 oqfn32-5x5-xr Code Disc glass disc 1.0 mm (for contracted designs only) LAnnS aa-xxxx_u film disc 0.18 mm LAnnFS aa-xxxx_u Evaluation Kit Kit with Scanner Module IC273 (61 mm x 64 mm), LED Module IC274 selectable index gating, glass lid EVAL IC273 Kit with Scanner Module IC273 (61 mm x 64 mm), LED Module IC274 and Code Disc L4S selectable index gating, on-chip reticle EVAL IC273 L4RS Illumination Infrared LED module (28 mm x 29 mm) Blue LED module (28 mm x 29 mm) ic-sd85 EVAL IC274 ic-l46 EVAL IC274 Mother Board Adapter PCB (80 mm x 110 mm) ic277 EVAL IC277 Please send your purchase orders to our order handling team: Fax: +49 (0) dispo@ichaus.com For technical support, information about prices and terms of delivery please contact: ic-haus GmbH el.: +49 (0) Am Kuemmerling 18 Fax: +49 (0) D Bodenheim Web: GERMANY sales@ichaus.com Appointed local distributors: