Low Noise, High Frequency Dual Step-Down Converter. Features. L1 1.5μH. C2 22μF 6.3V. L2 3.3μH LX2. C3 10μF 6.3V PGND2 FB2 AGND2

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1 General Description The is a -channel synchronous step-down converter operating from an input voltage range of.7v to 5.5V, making it the ideal choice for single-cell Lithiumion/polymer battery powered systems or low voltage 3.3V and 5V based consumer equipment. Channel delivers up to 7mA output current while Channel delivers up to 8mA. Both converters incorporate a unique low noise architecture which reduces output ripple and spectral noise. The uses a high switching frequency to minimize external filter sizing. Peak current mode control eliminates external compensation while optimizing transient performance and stability. The requires a minimum of external components to realize a high efficiency dual-output step-down converter while minimizing solution size and footprint. Each of the step-down regulators has an independent input and enable pin. Externally adjustable output voltage is provided. Light load operating mode provides high efficiency over the entire load range. Low quiescent current enables excellent life for battery powered systems. The is available in a 3x4mm Pb-free 6-pin TDFN package and is rated over the - C to 85 C operating temperature range. Features V IN Range:.7V to 5.5V Output Voltage Range:.6V to V IN Low Noise Light Load Mode Low Ripple PWM Mode Output Current: Channel : 7mA Channel : 8mA Highly Efficient Step-Down Converters Low R DS(ON) Integrated Power Switches % Duty Cycle High Switching Frequency Peak Current Mode Control Internal Compensation Excellent Transient Response Internal Soft Start Fast Turn-On Time Over-Temperature Protection Current Limit Protection Low Profile TDFN34-6 Package - C to 85 C Temperature Range Applications Cellular and Smart Phones Digital Cameras Handheld Instruments Mass Storage Systems Microprocessor / DSP Core / IO Power PDAs and Handheld Computers Portable Media Players USB Devices Wireless Data Systems Typical Application V IN :.7V - 5.5V C μf 6.3V TDFN34-6 VP, LX VCC, EN PGND EN FB AGND LX PGND FB AGND L.5μH L 3.3μH C μf 6.3V C3 μf 6.3V V OUT 3.3V, 8mA V OUT.V, 7mA R3 67k R4 59.k R 59.k R 59.k

2 Pin Descriptions Pin # Symbol Function N/C No connect. PGND Power ground pin for Channel step-down converter. Connect return of Channel input and output capacitors close to this pin for best noise performance. 3 LX Channel step-down converter switching pin. Connect output inductor to this pin. Inductor value is determined by output voltage. 4 VP Input supply voltage pin for Channel step-down converter. Connect a μf ceramic input capacitor close to this pin or connect to VP. Operating input voltage range is.7v to 5.5V. 5 VCC Input supply pin for Channel. Must be closely decoupled. 6 EN Enable Channel input pin. Active high. 7,8 VP Input supply voltage pin for Channel step-down converter. Connect a μf ceramic input capacitor close to this pin. Operating input voltage range is.7v to 5.5V. 9 LX Channel step-down converter switching pin. Connect output inductor to this pin. Inductor value is determined by output voltage. PGND Power ground pin for Channel step-down converter. Connect return of Channel input and output capacitors close to this pin for best noise performance. FB Feedback pin for Channel. Connect an external resistor divider to this pin to program the output voltage to the desired value. AGND Signal ground for Channel. 3 VCC Input supply pin for Channel. Must be closely decoupled. 4 EN Enable Channel input pin. Active high. 5 FB Feedback pin for Channel. Connect an external resistor divider to this pin to program the output voltage to the desired value. 6 AGND Signal Ground for Channel. EP EP Exposed paddle. Connect to PGND and PGND as close as possible to the device. Use properly sized vias for thermal coupling to the ground plane. See PCB layout guidelines. Pin Configuration TDFN34-6 (Top View) N/C PGND LX VP VCC EN VP VP AGND FB EN VCC AGND FB PGND LX

3 Absolute Maximum Ratings Symbol Description Value Units V IN VP, VP, VCC, VCC voltages to PGND, AGND 6. V V LX V LX, V LX to PGND, AGND -.3 to V IN +.3 V V FB V FB, V FB to PGND, AGND -.3 to V IN +.3 V V EN V EN, V EN to PGND, AGND -.3 to 6. V T J Operating Junction Temperature Range - to 5 C T LEAD Maximum Soldering Temperature (at leads, sec) 3 C Thermal Information Symbol Description Value Units P D Maximum Power Dissipation. W Θ JA Thermal Resistance 3 5 C/W. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum Rating should be applied at any one time.. Mounted on a FR4 board. 3. Derate mw/ C above 5 C ambient temperature

4 Electrical Characteristics V IN = 3.6V, T A = - C to 85 C, unless noted otherwise. Typical values are at T A = 5 C. Symbol Description Conditions Min Typ Max Units Channel : 7mA Step-Down Converter V P, V CC Input Voltage V V P Rising.4 V V UVLO UVLO Threshold V P Hysteresis 5 mv V P Falling.7 V V OUT Output Voltage Range.6 V P V V OUT(TOL) Output Voltage Tolerance I OUT = A to.7a; V P =.7V to 5.5V % I Q Quiescent Current No load, V EN = V P, V EN = AGND 4 9 μa I SHDN Shutdown Current V EN = GND. μa I LIM Current Limit 8 ma R DSON(H) High Side On-Resistance mω R DSON(L) Low Side On-Resistance 85 mω ΔV LOADREG Load Regulation I OUT = A to.7a.5 % ΔV LINEREG / ΔV P Line Regulation V P =.7V to 5.5V. %/V F OSC Oscillator Frequency...68 MHz T S Start-Up Time From Enable- to Output- Regulation 5 μs Channel : 8mA Step-Down Converter V P, V CC Input Voltage V V P Rising.7 V V UVLO UVLO Threshold V P Hysteresis mv V P Falling.7 V V OUT Output Voltage Range.6 V P V V OUT(TOL) Output Voltage Tolerance I OUT = A to 8mA, V P =.7V to 5.5V % I Q Quiescent Current No load, V EN = V P, V EN = AGND 37 7 μa I SHDN Shutdown Current V EN = GND. μa I LIM Current Limit 9 ma R DSON(H) High Side On-Resistance 33 mω R DSON(L) Low Side On-Resistance 75 mω ΔV LOADREG Load Regulation I OUT = ma to 8mA.5 % ΔV LINEREG / ΔV P Line Regulation V P =.7V to 5.5V. %/V F OSC Oscillator Frequency.9..6 MHz T S Start-Up Time From Enable- to Output- Regulation 5 μs Over-Temperature, EN Logic Over-Temperature Shutdown Threshold C T SD, Over-Temperature Shutdown Hysteresis 5 C V EN,(L) Enable Threshold Low.6 V V EN,(H) Enable Threshold High.4 V I EN(, Input Low Current -.. μa. The is guaranteed to meet performance specifications over the C to +85 C operating temperature range, and is assured by design, characterization and correlation with statistical process controls

5 Typical Characteristics Channel Efficiency vs. Output Current (V OUT = 3.3V) Load Regulation vs. Output Current (V OUT = 3.3V). Efficiency (%) V IN = 3.6V VIN = 4.V VIN = 5V 3. Load Regulation (%) V IN = 3.6V VIN = 4.V VIN = 5V -.. Efficiency vs. Output Current (V OUT =.8V) Load Regulation vs. Output Current (V OUT =.8V). Efficiency (%) V IN =.7V VIN = 3.6V VIN = 4.V 3. Load Regulation (%) V IN =.7V VIN = 3.6V VIN = 4.V -.. Efficiency vs. Output Current (V OUT =.V) Load Regulation vs. Output Current (V OUT =.V) Efficiency (%) V IN =.7V VIN = 3.6V VIN = 4.V 3. Load Regulation (%) V IN =.7V VIN = 3.6V VIN = 4.V

6 Typical Characteristics Channel Quiescent Current vs. Input Voltage (V OUT =.8V; No Load) Output Voltage Error vs. Temperature (V OUT =.8V; I OUT = A) 8.5 Quiescent Current (µa) C 5 5 C 3 - C Output Voltage Error (%) Input Voltage (V) Temperature ( C) Output Voltage vs. Input Voltage (V OUT =.8V; I OUT = A) Switching Frequency vs. Temperature (V OUT =.8V; I OUT = A) Output Voltage (V) C C C Switching Frequency (MHz) Input Voltage (V) Temperature ( C) Load Transient Response (V OUT =.8V) Load Transient Response (V OUT =.8V; C FF = pf) Output Voltage (AC coupled) (top)(mv) Output Current (bottom) (A) Output Voltage (AC coupled) (top)(mv) Output Current (bottom) (A) Time (µs/div) Time (µs/div)

7 Typical Characteristics Channel Line Transient Response (V OUT =.8V; I OUT =.5A; C FF = pf) Line Regulation (V OUT =.8V; I OUT = A) Input Voltage (top) (V) Output Voltage (AC coupled) (bottom) (V) V OUT Error (%) Time (µs/div) Input Voltage (V) Light Load Switching Waveform (V IN = 3.6V; V OUT =.8V; I OUT = ma; C FF = pf) Light Load Switching Waveform (V IN = 3.6V; V OUT =.8V; I OUT = ma; C FF = pf) Output Voltage (AC coupled) (top) (mv) Inductor Ripple Current (bottom) (A) Output Voltage (AC coupled) (top) (mv) Inductor Ripple Current (bottom) (A) Time (5µs/div) Time (µs/div) Light Load Switching Waveform (V IN = 3.6V; V OUT =.8V; I OUT = ma; C FF = pf) Light Load Switching Waveform (V IN = 3.6V; V OUT =.8V; I OUT = ma; C FF = pf) Output Voltage (AC coupled) (top) (mv) Inductor Ripple Current (bottom) (A) Output Voltage (AC coupled) (top) (mv) Inductor Ripple Current (bottom) (A) Time (5µs/div) Time (5µs/div)

8 Typical Characteristics Channel EN (V/div) V OUT (V/div) I IN (5mA/div) Enable Soft Start (V IN = 3.6V; V OUT =.8V; I OUT =.7A) Output Voltage (AC coupled) (top)(mv) - - Heavy Load Switching Waveform (V IN = 3.6V; V OUT =.8V; I OUT =.7A) Inductor Ripple Current (bottom) (A) Time (µs/div) Time (5ns/div)

9 Typical Characteristics Channel Efficiency (%) Efficiency vs. Output Current (V OUT = 3.3V) 5 V IN = 3.6V V IN = 4.V VIN = 5V 3. Output Error (%) Load Regulation (V OUT = 3.3V) V.8 IN = 3.6V VIN = 4.V.6 VIN = 5V Efficiency (%) Efficiency vs. Output Current (V OUT =.5V) 6 V IN = 3V 5 VIN = 3.6V VIN = 4.V VIN = 5V 3. Output Error (%) Load Regulation (V OUT =.5V).8 V IN = 3V VIN = 3.6V.6.4 VIN = 4.V VIN = 5V Efficiency (%) Efficiency vs. Output Current (V OUT =.8V) 5 V IN =.7V VIN = 3.6V VIN = 4.V 3. Output Error (%) Load Regulation (V OUT =.8V) V IN =.7V -.6 VIN = 3.6V -.8 VIN = 4.V

10 Typical Characteristics Channel Accuracy (%) Line Regulation (V OUT =.8V) Input Voltage (V) ma ma 6mA 8mA Switching Frequency (MHz) Switching Frequency vs. Temperature (V OUT =.8V; I OUT = 8mA) Temperature ( C) Frequency Variation vs. Input Voltage Output Voltage Error vs. Temperature (V IN = 3.6V; V O =.8V, I OUT = ma) Frequency Variation (%) V OUT =.8V VOUT = 3V Input Voltage (V) Output Voltage Error (%) Temperature ( C) No Load Quiescent Current vs. Input Voltage P-Channel R DS(ON) vs. Input Voltage Supply Current (µa) C 5C 5 - C Input Voltage (V) R DS(ON) (mω) Input Voltage (V) C C 85 C 5 C

11 Typical Characteristics Channel N-Channel R DS(ON) vs. Input Voltage Load Transient (V IN = 3.6V; V OUT =.8V; C OUT = µf; C FF = pf) R DS(ON) (mω) Input Voltage (V) C C 85 C 5 C Output Voltage (top) (V) mA 3mA ma Time (5µs/div) ma Output and Inductor Current (ma/div) Output Voltage (top) (V) Load Transient (V IN = 3.6V; V OUT =.8V; C OUT = 4.7µF; C FF = pf) ma ma 3mA 3mA Output and Inductor Current (ma/div) Output Voltage (top) (V) Load Transient (V IN = 3.6V; V OUT =.8V; C OUT = µf; C FF = pf) ma ma 3mA 3mA Output and Inductor Current (ma/div) Time (5µs/div) Time (5µs/div) Load Transient (V IN = 3.6V; V OUT =.8V; C OUT = µf; C FF = pf) Line Transient (V OUT =.8V; V IN = 3.6V to 4.V; I OUT = ma; C FF = pf) Output Voltage (top) (V) mA 3mA ma ma Output and Inductor Current (ma/div) Input Voltage (top) (V) Output Voltage (bottom) (V) Time (5µs/div) Time (5µs/div)

12 Typical Characteristics Channel. Output Ripple (V OUT =.8V; V IN = 3.6V; I OUT = ma; C FF = pf) Output Ripple (V OUT =.8V; V IN = 3.6V; I OUT = ma; C FF = pf). Output Voltage (top) (V) Inductor Current (bottom) (A) Output Voltage (top) (V) Inductor Current (bottom) (A) Time (µs/div) Time (ns/div) Soft Start (V IN = 3.6V; V OUT =.8V; I OUT = ma) Enable Voltage (top) (V) Output Voltage (middle) (V) Input Current (bottom) (A) Time (µs/div)

13 Functional Block Diagram VCC, OT OSC VP FB Error Amp Comp. Voltage Ref Logic LX EN Control Logic PGND OT OSC VP FB Error Amp Comp. Voltage Ref Logic LX EN Control Logic PGND AGND, Functional Description The is a -channel synchronous step-down (Buck) converter operating from an input voltage range of.7v to 5.5V; making it the ideal choice for single-cell Lithium-ion/polymer battery powered systems or low voltage 3.3V and 5V based consumer equipment. Channel delivers up to 7mA output current while Channel delivers up to 8mA. Both converters incorporate a unique low noise architecture which reduces output ripple and spectral noise. The device utilizes a high switching frequency to minimize external filter sizing. Peak current mode control eliminates external compensation while optimizing transient performance and stability. The device requires a minimum of external components to realize a high efficiency dual-output step-down converter while minimizing solution size and footprint. Each of the step-down regulators has an independent input and enable pin. Adjustable output voltage is provided. Light load operating mode provides high efficiency over the entire load range. The enable inputs, when pulled low, force the respective converter into a low power non-switching state consuming less than μa of current. Low quiescent current enables excellent life for battery powered systems. Additional features include integrated soft start to limit inrush current. Soft start limits the current surge seen at the input and eliminates output voltage overshoot. For overload conditions, the peak input current is limited. Also, over-temperature protection safeguards the device from damage due to high operating temperature or fault conditions. The junction over-temperature threshold is C with 5 C of hysteresis. Under voltage lockout (UVLO) guarantees sufficient input voltage bias prior to turn-on. The is available in the 3x4mm Pb-free 6-pin TDFN package and is rated over the - C to 85 C operating temperature range

14 Applications Information Inductor Selection Both step-down converters use peak current mode control with slope compensation to maintain stability for duty cycles greater than 5%. When the duty cycle exceeds 5%, the inductor value must be selected to maintain the prescribed down-slope in accordance with the internal slope compensation requirements. Channel The internal slope compensation for the adjustable and low voltage fixed versions of Channel is.75a/μs. This equates to a slope compensation that is 75% of the inductor current down slope for a.8v output and.8μh inductor..75 V m = O.75.8V A = =.75 L.8µH µs.75 V L = O.75.V = =.µh m A.75 µs The inductor should be set equal to the output voltage numeric value in microhenries (μh). This guarantees sufficient internal slope compensation. Manufacturer s specifications list both the inductor DC current rating, which is a thermal limitation, and the peak current rating, which is determined by the saturation characteristics. The inductor should not show any appreciable saturation under normal load conditions. Some inductors may meet the peak and average current ratings yet result in excessive losses due to a high DCR. Always consider the losses associated with the DCR and its effect on the total converter efficiency when selecting an inductor. Channel The slope compensation for Channel output is set at.75a/μs. This equates to a slope compensation that is 75% of the inductor current down slope for a.8v output and.8μh inductor:.75 V m = O.75.8V A = =.75 L.8µH µs.75 V L = O V = = 3.3µH m A.75 µs Input Capacitor Select a μf to μf X7R or X5R ceramic capacitor for the input. To estimate the required input capacitor size, determine the acceptable input ripple level (V PP ) and solve for C IN. The calculated value varies with input voltage and is a maximum when V IN is double the output voltage. V O V IN C IN = V O V IN V PP I O - V O V IN - ESR F S V - O = for V IN = V V O IN 4 C IN(MIN) = V PP I O - ESR 4 F S Always examine the ceramic capacitor DC voltage coefficient characteristics when selecting the proper value. For example, the capacitance of a μf, 6.3V, X5R ceramic capacitor with 5.V DC applied is actually about 6μF. The maximum input capacitor RMS current is: V I RMS = I O O - V IN V O V IN The input capacitor RMS ripple current varies with the input and output voltage and will always be less than or equal to half of the total DC load current. V O V IN For V IN = V O V - O = D ( - D) =.5 = V IN V O - V IN V O I RMS(MAX) The term V IN appears in both the input voltage ripple and input capacitor RMS current equations and is a maximum when V O is twice V IN. This is why the input voltage ripple and the input capacitor RMS current ripple are a maximum at 5% duty cycle. = I O

15 The input capacitor provides a low impedance loop for the edges of pulsed current drawn by the. Low ESR/ESL X7R and X5R ceramic capacitors are ideal for this function. To minimize stray inductance, the capacitor should be placed as closely as possible to the IC. This keeps the high frequency content of the input current localized, minimizing EMI and input voltage ripple. The proper placement of the input capacitor (C) can be seen in the evaluation board layout in the Layout section of this datasheet (see Figures and ). A laboratory test set-up typically consists of two long wires running from the bench power supply to the evaluation board input voltage pins. The inductance of these wires, along with the low-esr ceramic input capacitor, can create a high Q network that may affect converter performance. This problem often becomes apparent in the form of excessive ringing in the output voltage during load transients. Errors in the loop phase and gain measurements can also result. Since the inductance of a short PCB trace feeding the input voltage is significantly lower than the power leads from the bench power supply, most applications do not exhibit this problem. In applications where the input power source lead inductance cannot be reduced to a level that does not affect the converter performance, a high ESR tantalum or aluminum electrolytic should be placed in parallel with the low ESR/ESL bypass ceramic capacitor. This dampens the high Q network and stabilizes the system. Output Capacitor Channel The output capacitor limits the output ripple and provides holdup during large load transitions. A μf to μf X5R or X7R ceramic capacitor typically provides sufficient bulk capacitance to stabilize the output during large load transitions and has the ESR and ESL characteristics necessary for low output ripple. The output voltage droop due to a load transient is dominated by the capacitance of the ceramic output capacitor. During a step increase in load current, the ceramic output capacitor alone supplies the load current until the loop responds. Within two or three switching cycles, the loop responds and the inductor current increases to match the load current demand. The relationship of the output voltage droop during the three switching cycles to the output capacitance can be estimated by: C OUT = 3 ΔI LOAD V DROOP F S Once the average inductor current increases to the DC load level, the output voltage recovers. The above equation establishes a limit on the minimum value for the output capacitor with respect to load transients. The internal voltage loop compensation also limits the minimum output capacitor value to μf. This is due to its effect on the loop crossover frequency (bandwidth), phase margin, and gain margin. Increased output capacitance will reduce the crossover frequency with greater phase margin. The maximum output capacitor RMS ripple current is given by: I RMS(MAX) V = OUT (V IN(MAX) - V OUT ) 3 L F S V IN(MAX) Dissipation due to the RMS current in the ceramic output capacitor ESR is typically minimal, resulting in less than a few degrees rise in hot-spot temperature. Channel The output capacitor limits the output ripple and provides holdup during large load transitions. A 4.7μF to μf X5R or X7R ceramic capacitor typically provides sufficient bulk capacitance to stabilize the output during large load transitions and has the ESR and ESL characteristics necessary for low output ripple. Output Voltage The output voltages are programmed with external resistors R, R (Channel ) and R3, R4 (Channel ). To limit the bias current required for the external feedback resistor string while maintaining good noise immunity, the minimum suggested value for R and R4 are 59kΩ. Although a larger value will further reduce quiescent current, it will also increase the impedance of the feedback node, making it more sensitive to external noise and interference. Table summarizes the resistor values for various output voltages with R and R4 set to either 59kΩ for good noise immunity or kω for reduced no load input current

16 V OUT (V) R, 4 = 59kΩ R, 3 (kω) R, 4 = kω R, 3 (kω) Table : Resistor Values for Various Output Voltages. Thermal Calculations There are three types of losses associated with the step-down converter: switching losses, conduction losses, and quiescent current losses. Conduction losses are associated with the R DS(ON) characteristics of the power output switching devices. Switching losses are dominated by the gate charge of the power output switching devices. At full load, assuming continuous conduction mode (CCM), a simplified form of both stepdown converters is given by: I O (R DSON(HS) V O + R DSON(L) [V IN -V O ]) P TOTAL = + (t sw F S I O + I Q ) V IN V IN I O (R DSON(HS) V O + R DSON(L) [V IN -V O ]) + + (t sw F S I O + I Q ) V IN V IN I Q and I Q are the step-down converter quiescent currents for Channel and Channel respectively. The term t SW is used to estimate the full load step-down converter switching losses. For the condition where the step-down converter is in dropout at % duty cycle, the total device dissipation reduces to: P TOTAL = I O R DS(ON)H + I Q V IN + I O R DS(ON)H + I Q V IN Since R DS(ON), quiescent current, and switching losses all vary with input voltage, the total losses should be investigated over the complete input voltage range. Given the total losses, the maximum junction temperature can be derived from the θ JA for the TDFN34-6 package, which is 5 C/W. PCB Layout T J(MAX) = P TOTAL Θ JA + T AMB The suggested PCB layout for the is shown in Figures and. The following guidelines should be used to help ensure a proper layout.. The input and output capacitors C, C, C3, and C4 should be connected as closely as possible to the input and output pins.. Output capacitors and inductors (C, C3 and L; C4 and L) should connect as closely as possible. The connection of the inductor (L, L) to the LX and LX pins should be as short as possible. 3. The feedback traces or FB pins should be separated from any power traces and connect as closely as possible to the load point. Sensing along a highcurrent load trace will degrade DC load regulation. 4. The resistance of the trace from the load return to PGND should be kept to a minimum. This will help to minimize any error in DC regulation due to differences in the potential of the internal signal ground and the power ground. 5. The lower R (FB) and R4 (FB) resistor's grounds should be connected to the AGND and AGND pins. 6. C5, C6 are optional feed forward capacitors for both channels to stabilize the output voltage during large load transitions. 7. For good thermal coupling, PCB vias are required from the pad for the TDFN paddle to the bottom ground plane

17 Printed Circuit Board Layout Recommendations Figure : Evaluation Board Component Side Layout. Figure : Evaluation Board Solder Side Layout. VIN 7 U NC VP LX FB 9 L.5μH R 59K C5 opt C μf OUT C3 μf 8 VP AGND R 59K C μf 5 6 VCC LX EN FB 3 5 L 3.3μH R3 67K C6 opt OUT 4 VP AGND 6 R4 59K C4 μf 3 VCC PGND 4 EN PGND TDFN34-6 Figure 3: Evaluation Board Schematic. Symbol Part Number Description Qty U AnalogicTech -Output Buck TDFN34-6 C, C, C3, C4 GRM88R6J6ME47D Cap, MLC, uf/6.3v, 63 ( H MAX =.9mm), Murata 4 C5 Generic Cap,nF/6.3V, C6 Generic Cap,pF/6.3V, L LQMHPNR5MG.5uH, I SAT =3A, x.5x.9mm (H MAX =.95mm), shielded chip inductor, Murata L TFC58MBT 3.3uH, I SAT =.5A, x.5xmm (H MAX =.mm), non-shielded chip inductor, TDK R-R4 Generic Carbon Film resistor, Table : Evaluation Board Bill of Materials

18 Design Example Specifications V O (adjustable using.6v version), Pulsed Load ΔI LOAD =.5A V O = 5mA (adjustable using.6v version), Pulsed Load ΔI LOAD =.5A V IN =.7V to 4.V (3.6V nominal) F S =.8MHz, F S = MHz m =.75A/μs T AMB = 85 C in TDFN34-6 Package Channel Inductor.75 V L = O.75.V = =.µh; use.5µh m A.75 µs For TDK inductor LQMPHNR5MG,.5μH, DCR = 7mΩ max. V O V O.V.V ΔI = - = - = 37mA L F S V IN.5µH.8MHz 4.V ΔI I PK = I O + =.5A +.37A =.87A P L = I OUTBUCK DCR =.5A 7mΩ = 58mW Channel Inductor.75 V L = O V = = 3.3µH m A.75 µs For TDK inductor TFC58MBT, 3.3μH, DCR = mω max. V O V O 3.3V 3.3V ΔI = - = - = 7mA L F S V IN 3.3µH.8MHz 4.V ΔI I PK = I O + =.5A +.54A =.55A P L = I OUTBUCK DCR =.55A mω = 3.mW

19 Channel Output Capacitor V DROOP =.V 3 ΔI LOAD 3.5A C OUT3 = = =.8µF; use µf V DROOP F S.V.8MHz I RMS(MAX) V.V (4.V -.V) = OUT (V IN(MAX) - V OUT ) = = 9mA 3 L F S V IN(MAX) 3.5µH.8MHz 4.V P ESR = ESR I RMS = 5mΩ 4mA = 3µW Channel Output Capacitor V DROOP =.V 3 ΔI LOAD 3.5A C OUT3 = = = 7.5µF; use µf V DROOP F S.V MHz I RMS(MAX) V 3.3V (4.V - 3.3V) = OUT (V IN(MAX) - V OUT ) = = 3mA 3 L F S V IN(MAX) 3 3.3µH MHz 4.V P ESR = ESR I RMS = 5mΩ 3mA = 4.5µW Input Capacitor Input Ripple V PP = 5mV, V PP = 5mV C IN = = = 4.9µF V PP 5mV - ESR 4 F I S - 5mΩ 4.8MHz O.5A C IN = = = 3µF V PP 5mV - ESR 4 F I S - 5mΩ 4 MHz O.5A C IN = C IN + C IN = 4.9μF+3μF= 7.9μF; use μf I RMS(MAX) I O + I = O = A P = ESR I RMS = ESR (A) = 5mW

20 Losses Total loss can be estimated by calculating the dropout (V IN = V O ) losses where the power MOSFETs R DS (ON) will be at the maximum value. All values assume an 85 C ambient temperature and a C junction temperature with the TDFN 5 C/W package. P TOTAL = I O R DS(ON)H + I Q V IN + I O R DS(ON)H + I Q V IN P TOTAL =.5A mω + 7µA R DS(ON)H + 7µA 4.V = 7mW T J(MAX) = T AMB + Θ JA P LOSS = 85 C + (5 C/W) 7mW = 99 C

21 Ordering Information Output Voltage Package Channel Channel Marking Part Number (Tape and Reel) TDFN34-6 Adjustable (.6) Adjustable (.6) 3JXYY IRN-AA-T All AnalogicTech products are offered in Pb-free packaging. The term Pb-free means semiconductor products that are in compliance with current RoHS standards, including the requirement that lead not exceed.% by weight in homogeneous materials. For more information, please visit our website at Output Voltage Adjustable (.6) Legend Code A. XYY = assembly and date code.. Sample stock is generally held on part numbers listed in BOLD

22 Package Information TDFN ±.5.6 ±.5 Index Area Detail "A" 4. ±.5.85 MAX 3.3 ±.5.35 ±. Top View Bottom View C.3.3 ±.5 (4x) Pin Indicator (optional).45 ±.5.5 ±.5.9 ±.5 Side View Detail "A" All dimensions in millimeters.. The leadless package family, which includes QFN, TQFN, DFN, TDFN and STDFN, has exposed copper (unplated) at the end of the lead terminals due to the manufacturing process. A solder fillet at the exposed copper edge cannot be guaranteed and is not required to ensure a proper bottom solder connection. Advanced Analogic Technologies, Inc. 33 Scott Boulevard, Santa Clara, CA 9554 Phone (8) Fax (8) Advanced Analogic Technologies, Inc. AnalogicTech cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AnalogicTech product. No circuit patent licenses, copyrights, mask work rights, or other intellectual property rights are implied. AnalogicTech reserves the right to make changes to their products or specifications or to discontinue any product or service without notice. Except as provided in AnalogicTech s terms and conditions of sale, AnalogicTech assumes no liability whatsoever, and AnalogicTech disclaims any express or implied warranty relating to the sale and/or use of AnalogicTech products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Testing and other quality control techniques are utilized to the extent AnalogicTech deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed. AnalogicTech and the AnalogicTech logo are trademarks of Advanced Analogic Technologies Incorporated. All other brand and product names appearing in this document are registered trademarks or trademarks of their respective holders