Performance analysis and low power VLSI implementation of DVB-T receiver

Transcription

1 1 Performance analysis and low power VLSI implementation of DVB-T receiver Imed Ben Dhaou and Laszlo Horvath Electronic System Design Laboratory, Dept. Of Electronics KTH-Electrum, Electrum-229 Royal Institute of Technology S , Kista

2 2 Presentation outline Introduction to WLAN Relation Between WLAN and OSI MAC and Physical Layer:Current status Future Challenges for designing high-data rate WLAN in the ISM band (5GHZ) High Data Rate WLAN in the ISM band: ESDLAB vision Overview of OFDM Efficient signalling techniques over dispersive channels Characteristics of the OFDM for DVB-T ESDLab proposal for WLAN PHY layer. How to achieve longer-battery life for WLAN high data-rate?

3 3 Presentation outline (part 2) DVB-T system description DVB-T transmitter overview DVB-T receiver overview Design Flow Improving the initial design in terms of area and power consumption. Hardware implementations: Demapper Symbol / Bit deinterleaver Depuncturer VLSI implementation and performance analysis

4 4 Introduction to WLAN

5 5 Wirless Local Area Network Client Server Architecture Application Presentation Session TCP AP Application Presentation Session TCP IP IP IP Data-Link Data-Link DS-FH (SS) DS-FH (SS) Physical (Wire) Physical (Wire) Backbone netwrok(wired LAN)

6 6 Relation Between WLAN and OSI (Open System Interconnect) Application Presentation Session TCP IP DS-FH (SS) LLC (802.11) MAC Layer- P CSMA/CA Asynchrounuse Time bounded transfer ISM band FH-DS SS 1-10 Mbps Meter (Tx range)

7 MAC and Physical Layer (Current status) Study expert group was formed under the IEEE project Its mission to recommend an international standard for WLANs The standard supports both ad-hoc and client-server architecture The first ratified standard was proposed in June 1996, Frequency hoppoing and Direct sequence spread spectrum is used at the PHY-level The IEEE standard supports DSSS for use with Differential Binary Phase Shift Keying (DBPSK) with data rate of 1Mbps, or Differential Quadrature Phase Shift Keying (DQPSK) 2 Mbps data rate. FHSS is supported under with GFSK modulation and two hopping patterns with data rates of 1 Mbps and 2 Mbps. The second draft of the standard, July 1998, the digital modulation at the PHY-level is :Direct Sequence/Pulse Position Modulation (DS/PPM) proposed by Lucent TM1 The MAC layer specification for is similar to the Ethernet standard

8 8 Future Challenges for designing high-data rate WLAN in the ISM band (5GHZ)

9 9 High Data Rate WLAN in the ISM band: ESDLAB vision For WLAN with data rate>100 Mbps, OFDM is a very good candidate: 1. High-spectral efficiency, 2. Robust against multi-path fading: Typical problem for WLAN communication channel, 3. In the ISM band, it is possible to design a single WLAN receiver for 80.11: DSSS, FHSS and DS/PPM, 4. OFDM is being proposed as PHY-level by the ETSI/BRAN (the Project for Broadband Radio Access Networks European Telecommunications Standards Institute) 5. The draft of a standard supports OFDM as PHY-layer

10 10 Overview of OFDM (Orthogonal-Frequency Division Multiplexing Modulator (frequency f 0 ) Μ 0 Μ 1 Μ Ν 1 Modulator (frequency f N-1 )

11 11 Digital OFDM (IFFT/IDFT) x 0 x 1 x 2 x N-3 x N-2 x N-1 I F F T X Cyclic extension h Additive noise n Physical channel + y F F T r 0 r 1 r 2 r N-3 r N-2 r N-1 Modulation Demodulation r k = H k x k + n k where r k = received symbol H k = frequency response of the physical channel x k = transmitted symbol n k = additive noise r = FFT(y+n) = FFT(h X+n) = FFT(h IFFT(x)+n) = FFT(h) x+fft(n) = H x+ñ

12 12 What are the problems when using OFDM digital modulation? ICI (Inter-channel Interference): Also called: Cross-talk, meaning: interference between symbol in adjacent frequencies. ISI sometimes called IFI (Inter-frame Interference), caused by the interference of successive OFDM frames. Highly vulnerable to synchronization errors and frequency offsets Highly vulnerable to the non-linearity of the PAs (in the RF analog front end).

13 13 Efficient signalling techniques over dispersive channels Spacing between adjacent sub-carriers is ensured by 1/T. T is the duration of the OFDM frame, Use pulse shaping signals in time domain to preserve orthogonality.

14 14 f*t Fig.1 Spacing between adjacent subcarriers.

15 15 Reducing spectral overlap by designing efficient signalling techniques. Fig2: Sidelobes when using rectangular pulse shaping

16 16 Fig3: Sidelobes when using RC filter with RF 0.5

17 17 How about M-band wavelet? Fig4: MCFB, low-pass filter

18 18 Fig 5: 8-band CMBF (Analysis part)

19 19 Characteristics of the OFDM for DVB-T Fig6: 2K mode, Tg=Tu/4.

20 20 Fig7: 8k mode, Tg=Tu/4. Fig8: Comparison between RC filter and rectangular Pulse shaping, 2K mode.

21 21 Parameters for efficient signalling of the DVB-T. Parameter 2k mode 8k mode Block length N Number of carriers K Symbol duration Ts 109,375 ns 109,375 ns Duration Tu= NTs 224 µs 896 µs Duration of guard interval Tg T u /4 = 56 µs T u /4 = 224 µs Block duration T block = Tu+Tg 280 µs 1,12 ms Carrier spacing 1/Tu 4,464 khz 1,116 khz Bandwidth W = K/Tu 7, MHz 7, MHz

22 22 Proposed OFDM for WLAN (US Patent) Samples 12,288 Samples IFFT (4K) CP RC (β=0.2) 40.96µs µs 1. US. Patent, Jan. 25, # 5,282,222

23 23 ESDLab proposal (not yet finalized!) 1 Mband wavelet with 128 at 5GHZ, data-rate: 150 Mbit/sec, using array processor at the PHY-level. Pico cells of range 50m. Supports both ad-hoc and client-server network. 1. Proposed by: Ben Dhaou Imed, imed@ele.kth.se,

24 24 How to achieve longer-battery life for WLAN high data-rate? Low-power cellular planning (trade-off: Coverage, BER, data-rate): up to 30% power saving Energy efficient protocols:from 10-70% power saving Low-complex, high-performance algorithms: 10-70% power saving, Low-power VLSI/ULSI design: up to 60% of power saving

25 25 Ways and methods for low-power VLSI/ULSI design. System Level (system integration) Partitioning, Power saving, high level of integration, low system clocks Algorithm Complexity, Concurrency, Regularity, minimizing number of operations Architecture Parallelism, Pipelining, Data encoding, Power management, Memory partitioning, Minimizing number of global busses, Minimizing number of instructions, uses of caches. Circuit/Logic Logic optimization, Multi V T logic circuits, Reducing V DD in noncritical path Device level Technology High density of integration, Reducing junction capacitance, Improved device characteristics for low voltage operation.

26 26 DVB-T system description DVB-T: Digital Video Broadcasting Terrestrial Version [EN ] The standard was ratified in March 1997 by ETSI (European Telecommunications Standards Institute) The standard specifies the digitally modulated signal: Modulator side: Detailed description of signal processing. Receiver side: Left open for different implementation solutions. DVB-C [EN ]: Cable system specifications. DVB-S [EN ]: Satellite system specifications. MPEG-2 coder DVB system To transmission channel

27 27 DVB-T / Digital Video Broadcasting for terrestrial television UHF DVB-T transmitter TV signal source MPEG-2 encoder FEC OFDM ( Physical Layer ) to aerial 1 DVB channel ~ 8 MHz 1705 sub carriers (spacing: 4464 HZ) - 2k mode 6817 sub carriers (spacing: 1116 HZ) - 8k mode DVB-T receiver Set top box OFDM FEC MPEG-2 decoder P1394 Firewire D/A TV

28 28 DVB-T system description The system will have to operate within the existing UHF spectrum allocated for analogue transmissions which means that its required to have: Sufficient protection against high levels of Co-channel interference (CCI) Sufficient protection against Adjacent-Channel Interference (ACI): Interference caused when two or more channels are placed in frequency bands that are too close together on the spectrum. Also the system is required to use the UHF-bands with maximum spectral efficiency, this can be achieved by utilizing Single Frequency Network (SFN) operation. (In Single Frequency Networks transmitters may use identical frequencies if they transmit absolutely identical data containers.) To achieve these requirements an OFDM system with concatenated error correcting coding is used for transmission (COFDM).

29 29 DVB-T Transmitter overview Video coder Audio coder Data coder MPEG-2 source coding and multiplexing Programme MUX Transport MUX 1 2 n Splitter MUX adaptation Energy dispersal MUX adaptation Energy dispersal Outer Coder Outer Coder Outer Interleaver Inner Coder Terrestrial channel adaptation Outer Interleaver Inner Coder Puncturing Puncturing To aerial Inner Interleaver Mapper Frame Adaptation IFFT Guard interval insertion D/A Front End Terrestrial channel adaptation Pilots & TPS Signals OFDM

30 30 MPEG-2 MPEG - Moving Picture Experts Group - the name given to the group of experts that developed the standards MPEG-1 and MPEG-2 and MPEG-4, currently working on MPEG-7. Established in 1988, the MPEG working group is part of JTC1, the Joint ISO/IEC Technical Committee on Information Technology. MPEG-2 is an encoding standard that convert analog video and audio input signals into compressed digital form. MPEG-2 also describes a decoding (reconstruction) process where the coded bits are mapped from the compact representation into the original image sequence. Common bit rate: 15 Mbits/s (Main profile, main level) Critical programmes (live broadcasts) require 6 Mbits/s. Non-critical Mbits/s.

31 31 MPEG-2 Elementary and Transport streams Video encoder Audio encoder Private data Video Elementary Stream Audio Elementary Stream Data Stream Multiplex (ES to PES to TP) Transport Demultiplex Video decoder Audio decoder Private data Application Dependent Specified by Standards Audio and video are compressed to form ES (elementary streams). The ES are then used to form PES (packetized elementary streams) which are further packetized to form TS (transport streams).

32 32 1. Randomization for energy dispersal (scrambling) & transport multiplex adaptation SYNC MPEG-2 transport multiplex data 1 byte 187 bytes a) MPEG-2 transport multiplex packet 8 Transport MUX packets PRBS period = 1503 bytes SYNC1 187 bytes randomized data SYNC2 187 bytes randomized data SYNC8 187 bytes randomized data SYNC1 187 bytes randomized data b) Data structure after scrambling and transport multiplex adaptation A pseudo-random bit stream (PRBS) is added modulo-2 to the transport packet stream. (but not to the SYNC bytes) Transport multiplex adaptation: Inverted SYNC byte provides synchronisation.

33 33 Scrambler / descrambler Initialization sequence Enable XOR Clear / randomized data input Randomized / de-randomized data output

34 34 2. Outer coding SYNC1 SYNCn or 204 bytes Randomized MPEG-2 transport packet 187 bytes 16 Parity bytes c) Reed Solomon RS(204, 188, t=8) error protected packets Provides protection against byte errors. Detectable errors: r = N - k = = 16 Correctable errors: t = r/2 = 8

35 35 3. Outer interleaver / deinterleaver x 11 bytes 1 1 byte per position 2 17 bytes 17 x 2 bytes byte per position 3 17 x 3 bytes x 3 bytes x 2 bytes bytes x 11 bytes FIFO shift register Outer interleaver Outer deinterleaver The SYNC or SYNC byte always passes through branch 0 to provide synchronisation. Convolutional, byte-wise interleaving, with depth I=12 is used. Break down any lengthy bursts of errors reaching the outer decoder (RS) in the receiver.

36 36 4. Inner, convolutional coder, rate 1/2 Rate = k n Modulo-2 addition X Output (G 1 = 171 octal ) bin Data Input k = 1 D D D D D D n = bin Constraint length L = 7 Modulo-2 addition Y Output (G 2 = 133 octal ) Convolutional coding with bit-level error correcting capability. Convolutional code, with rate 1:2 and 2 (L-1) k = 64 states. The DVB-T system also allows punctured rates of 2:3, 3:4, 5:6 and 7:8.

37 37 5. Puncturing Unpunctured data from rate 1/2 convolutional encoder Punctured data Code rate 1/2 Code rate 2/3 X 1 Y 1 X 2 X 1 Y 2 Y 1 Y 1 X 1 Y 2 Y 1 X 1 Code rate 3/4 X 3 X 2 X 1 Y 3 Y 2 Y 1 X 3 Y 2 Y 1 X 1 Code rate 5/6 Code rate 7/8 X 6 X 5 X 4 X 2 X 1 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Last X 4 X 3 X 2 X 1 Y 5 Y 4 Y 3 Y 2 Y 1 X 5 X 5 Y 4 X 3 Y 2 Y 1 X 1 X 7 X 3 X 5 Y 4 First X 5 Y 4 Y 3 Y 2 Y 1 X 1

38 38 6. Bit-wise interleaving b 0,0,b 0,1,... Bit deinterleaver I0 a 0,0,a 0,1,... b 1,0,b 1,1,... Bit deinterleaver I1 a 1,0,a 1,1,... From Puncturer...,x 2,x 1,x 0 DEMUX b 2,0,b 2,1,... b 3,0,b 3,1,... Bit deinterleaver I2 Bit deinterleaver I3 a 2,0,a 2,1,... a 3,0,a 3,1,... Symbol interleaver Y 0,Y 1,.. To Mapper b 4,0,b 4,1,... Bit deinterleaver I4 a 4,0,a 4,1,... b 5,0,b 5,1,... Bit deinterleaver I5 a 5,0,a 5,1,... Interleaving block size is 126 bits. Interleaving sequence is different for each interleaver. This block-based, bit-wise interleaving is repeated: 12 times/ofdm symbol (12 * 126 = 1512 bits), 48 times/ofdm symbol (48 * 126 = 6048 bits)

39 39 7. Symbol interleaver / deinterleaver Even OFDM symbols Y =(y 0,y 1,y 2,...,y Nmax-1 ) v - bits from index q to index H(q) Y H(q) = y q Y=(y 0,y 1,y 2,...,y Nmax-1 ) 0 H(q) < N max q = 0,...,N max in 2k N max = 6048 in 8k Odd OFDM symbols Y =(y 0,y 1,y 2,...,y Nmax-1 ) from index H(q) to index q y q = y H(q) Y=(y 0,y 1,y 2,...,y Nmax-1 ) Performs interleaving of data symbols within one OFDM symbol. Frequency interleaving. Repeated 68 times for each OFDM frame.

40 40 Permutation function H(q) 8k mode Control Unit R Toggle wires permutation R MSB 12 skip Address check 13 0 H(q) < 6048

41 41 8. Signal constellations and mapping The system uses Orthogonal Frequency Division Multiplexing (OFDM) transmission. Carrier modulation: All data carriers in one OFDM frame are either: - QPSK - 16-QAM - 64-QAM modulated - non-uniform-16qam - non-uniform-64qam Selecting a certain type of modulation directly affects: available data transmission capacity in a given channel, and the robustness with regard to noise and interference. The choice of code rate of the inner coder can be used to fine-tune the performance of the system.

42 42 OFDM frame structure T S T F OFDM frame Each OFDM-frame has a duration of T F and consist of 68 symbols. Each symbol has duration of T S and is constituted by: a set of 1705 carriers in 2k-mode. a set of 6817 carriers in 8k-mode.

43 43 OFDM symbol structure T U Guard interval cell 0 1 K max 1 OFDM symbol A symbol is composed by two parts: a useful part with duration T u and a guard interval with duration, which consist of a cyclic continuation of the useful part, for protection against multipath and to support SFN:s. /T u can be: 1/4, 1/8, 1/16, 1/32. These are called guard interval ratios. Each symbol can be considered divided into cells, each corresponding to the modulation carried on one carrier during one symbol.

44 44 OFDM frame structure In addition to the transmitted data the OFDM frame contains: Scattered pilot cells Continual pilot carriers TPS carriers (Transmission Parameter Signalling) The pilots are used for: frame synchronization time synchronisation channel estimation transmission mode identification

45 45 DVB-T receiver overview From aerial Time & Frequency Synchronisation Common Phase Error Correction Channel Estimation Reliability Estimation Front End A/D I/Q Conversion FFT Frame Demux Demapper Inner Deinterleaver Depuncturer Hardware implementation exists. Inner Decoder (Viterbi) Outer Deinterleaver Outer Decoder (Reed-Solomon) Common part with satellite baseline receiver (DVB-S) Descrambling & Demux Adaptation Demultiplex MPEG-2 Video Decoder Audio Decoder Data Decoder

46 46 Design Flow Components implemented as Matlab functions Test data from Teracom AB From conv. encoders Puncturer HP Puncturer LP 1 2 Demux Bit interleaver Symbol interleaver Mapper Frame adaptation 3 puncture.m bit_demux.m bit_int.m symbol_int.m generate_constell.m insert_pilots.m From channel correction Demapper Symbol deinterleaver Bit deinterleaver Mux Depuncturer To rate 1/2 Viterbi decoder generate_vbitword.m symbol_deint.m bit_deint.m bit_mux.m depuncture.m Test data DVB-T Standard VHDL Implementation Testbench

47 47 Initial Design y q out = y H(q) in Even RAM in Even RAM out Demapper q Hq q Symbol Deint. q Hq q Bit Deint. Odd RAM in Odd RAM out y H(q) out = y q in Data path Address bus

48 48 Improved design y q out = y H(q) in Even RAM Demapper q Hq Hq q Bit Deint. Odd RAM y H(q) out = y q in Data path Address bus

49 49 Improved design, operation sequence k N clk (k+1) N clk (k+2) N clk (k+3) N clk (k+4) N clk Demapper D odd D even D odd D even Bitd. / Depunct. B even B odd B even B odd N clk = 8448 in 2k mode [231 ms x (256/7) MHz] in 8k mode [924 ms x (256/7) MHz] D : Number of clock cycles required to demap an OFDM symbol. B : Number of clock cycles required to bit deinterleave / depuncture an OFDM symbol. Timing limits, required for correct operation: D odd,d even < N clk B odd,b even < N clk

50 50 MUSCOD Algorithm The imaginary- and real axes are the decision lines for y 0 and y 1. (y 0 = 0 if Re > 0) decision lines for y 2 and y 3 in non-uniform-64-qam, with α=4 Im{z} decision lines Im{z} y 2 = 1 y 2 = y 3 = 0 y 3 = 1 Re{z} decision lines for y 4 and y 5 in non-uniform-64-qam, with α=4 Re{z} Im{z} decision lines Im{z} y 5 = 0 y 5 = 1 y 5 = y 4 = 0 y 4 = 1 y 4 = Re{z} Re{z}

51 51 Demapper mode<1:0> alpha<1:0> v_width<1:0> symbol_sign start_demap setinitbit HqShiftReg address_odd <12:0> RdWrF_odd new_symbol DemapperControl alpha_plus_s<1:0> wordv_s<2:0> skip Hq_address_s<12:0> q_address_s<12:0> RdWrF, CeF, OeF Mem Select symbdeint CeF_odd OeF_odd address_even <12:0> RdWrF_even re_data_in<4:0> sign bit + binary DemapReorIm y 0 y 2 y 4 CeF_even OeF_even vbitword<7:0> im_data_in<4:0> sign bit + binary DemapReorIm y 1 y 3 y 5 Demapper bit 7 -> 0 bit 6 -> 0 bit 5 -> y 0 bit 4 -> y 1 bit 3 -> y 2 bit 2 -> y 3 bit 1 -> y 4 bit 0 -> y 5

52 52 Hq Address Generator set_initbit Shift register (TPSs39) mode(0) Toggle bit 11 in 2k mode bit 13 in 8k mode Wires permutation 16 2 mode HqShiftReg Address check 16 Hq_address skip (TPSs39) mode(0) set_initbit

53 53 data_in(5) [y 0 or a 0,x ] data_in(4) [y 1 or a 1,x ] data_in(3) [y 2 or a 2,x ] data_in(2) [y 3 or a 3,x ] data_in(1) [y 4 or a 4,x ] data_in(0) [y 5 or a 5,x ] Bit deinterleaving BitShifter 0 1 shiftin shiftout shiftin shiftout shiftin shiftout shiftin shiftout shiftin shiftout shiftin shiftout data_from_bitshift(5) [y 0 or b 0,x ] data_from_bitshift(5) [y 1 or b 1,x ] data_from_bitshift(5) [y 2 or b 2,x ] data_from_bitshift(5) [y 3 or b 3,x ] data_from_bitshift(5) [y 4 or b 4,x ] data_from_bitshift(5) [y 5 or b 5,x ] Power management: QPSK: BitShifters 0 and 1 are enabled 16-QAM: BitShifters 0, 1, 2 and 3 are enabled 64-QAM: All BitShifters are enabled

54 54 Bit deinterleaver address_even <12:0> RdWrF_even CeF_even OeF_even data_in_even<7:0> address_odd <12:0> RdWrF_odd CeF_odd OeF_odd data_in_odd<7:0> Mem Select symbdeint RdWrF, CeF, OeF q_address<12:0> reset_memsel symbol_sign_out<1:0> Hq_address<12:0> mode_out<1:0> reset_hqshiftreg step_hq set_initbit start_read mode_out<1:0> symbol_sign_out<1:0> HqShiftReg Read Handler skip_address new_data dep_accept_data new_data_punct Output Control v_width_out<1:0> last_block_ready outctrl_ready Bitdeint Control start_bitdeint mode<1:0> symbol_sign<1:0> vwidth<1:0> bitdeint_ready load<5:0> shift_enable<5:0> data_memsel_to_bitshift<5:0> enable_shift_out<5:0> BitShifter data_out<5:0>

55 55 Puncturing / Depuncturing Depuncture pattern for: 64-QAM (v = 6) hierarchical transmission, low priority stream with code rate 3/4. 16-QAM (v = 4), non-hierarchical transmission with code rate 3/4. a. b. Unpunctured data from conv. encoder Punctured data A 0 A 1 A 2 B 0 B 1 B 2 First Last A 0 B 0 B 1 A 2 c. Delayed data I10 I20 I30 I31 I40 I41 I42 A 0 B 0 B 1 B 1 A 2 A 2 A 2 d. Depuncture pattern MUX 1 : MUX 0 : I10 I20 I31 I42 e. Depunctured data A 0 A 2 B 0 B 1 First Last

56 56 Depuncturer hierarchy priority vwidth<1:0> code_rate<2:0> start_bitdeint bitdeint_ready Depuncturer new_data accept_data Delay 2 new_data_delay_2 Depunct Control Delay 1 puncture_info<1:0> nd2 nd1<37:0> nd0<37:0> hierarchy priority vwidth<1:0> enable_shift<5:0> sel1 MUX1 37 to 1 data_from_bitdeint<5:0> Reorder Delay Generator sel0 depunctured_data<1:0> depunct_value MUX0 37 to 1

57 57 Chip Compiler: place & route Depuncturer Demapper Bit deint. RAM odd Shiftin 0 Shiftout 0 Shiftin 3 Shiftout 3 Shiftin 1 Shiftout 1 Shiftin 4 Shiftout 4 Shiftin 2 Shiftin 5 Shiftout 2 Shiftout 5 RAM even

58 58 Compass Layout2 a. Part of the odd RAM c. Shiftout block 6573 transistors Size: 1,88 mm x 0,95 mm Area: 1,80 mm 2 b. The layout of the chip Size: 7,21mm x 9,45 mm Area: 68,1 mm 2

59 59 IC properties Clock frequency 36,57 MHz (4 x 64/7 MHz) Technology 0.6µm, 3.3V CMOS Max. Power dissipation ~0,41 W Width x Height 7,21 mm x 9,71 mm Area (without pads) 68,2 mm 2 No of transistors (RAMs not included) RAM type Compass, Asynchronous RAM Compiler, 0.6µm, 3.3V CMOS RAM size 8x3x2048 bits = bits = 6 Kbytes

60 60 System performance Table 1: Performance of the implemented subsystems Demapper, max. input bit-rate (8k, 64-QAM, even) Demapper, max. output bit-rate (8k, 64-QAM, even) Bit deint., max input / output bit-rate (several modes) Depuncturer, max. output bit rate (8k, 64-QAM, 7/8, even) 91,4 Mbits/s 54,8 Mbits/s 53,5 Mbits/s 71,8 Mbits/s Table 2: Practical transmission system performance DVB-T (Terrestrial) DVB-C (Cable) DVB-S (Satellite) 4,98-31,97 Mbits/s Up to 38 Mbits/s Mbits/s

61 61 Conclusions and future work DVB-T uses a very effective digital communication method for transmitting MPEG2 video/audio streams. DVB-T got a wide acceptance in Europe, with potential expansion to support future mobile communications and data exchange. DVB-T receiver is cost effective, with low-power implementation possiblities. A high-data rate, low power implementation of the demapper, inner deinterleaver and depuncturer, used in the OFDM chain, was proposed and implemented. Future work will concentrate on finding an ultra-low power implementation for the bit deinterleaver.