Post-PFC DC-DC Converter Design Considerations to Meet Wide Load Current Efficiency Goals

Transcription

1 2011 IBM Power Technology Symposium Post-PFC DC-DC Converter Design Considerations to Meet Wide Load Current Efficiency Goals Rais Miftakhutdinov Texas Instruments, High Performance Isolated Power, South-East Design Center, Cary, North Carolina 1 Outline Energy Saving and Power Supply Efficiency related Standards Benchmark Design Goals: Efficiency, Power Density, Cost Phase-Shifted Full-Bridge Post-PFC Converter Optimal Design Procedure and Power Saving Algorithm Analog and Digital Controllers to meet Power Saving Goals MathCAD and SIMPLIS based Design Tools Prototype Example and Measured Performance Summary 2 1

2 Strive for Efficiency and Power Saving USA Energy Star German Blue Angel Telecommunication industry consumes 1% of electrical energy worldwide that equals to 160 Billions kwh [1] International Telecommunication Union (ITU) estimates that Information and Communication Technology contributes 2.5% into the worldwide greenhouse gas emission: Worldwide movement for energy saving and Green power generation and distribution, have resulted in number of voluntary initiatives and mandatory regulations by international and government organizations for increased efficiency of electronic equipment including data and telecommunication power systems. Examples of such organizations and initiatives are United States ENERGY STAR program, German Blue Angel, Japan Environment Association, European Code of Conduct and others [2]. Japan Environment Association 3 European Code of Conduct China Energy Conservation Project Korea Energy Management Corp CA Energy Commission Energy Star for Server Power Supplies, ver. 1, May 15, 2009 Energy Star minimum efficiency requirements for 12-V output server power supplies at 10%, 20%, 50%, 100% load and 230 V AC line [7]. Power Supply Type Rated Output Power 10% Load 20% Load 50% Load 100% Load Multi-Output (AC- DC & DC-DC) All Output Levels N/A 2% 5% 2% Single-Output (AC- DC & DC-DC) 500 W > W 70% 75% 2% 5% 9% 9% 5% 5% > 1000 W 0% % 92% % 4 2

3 0 PLUS and Climate Savers Computing Climate Savers Computing initiative requires servers to meet Energy Star specification and the power supply to be certified in accordance to 0 PLUS requirements. 20% load 1% 5% % 90% 50% load 5% 9% 92% 94% 100% load 1% 5% % 91% PF 50% load 50% load 50% load 50% load 5 [] [9] Design Goals for Front-End Power Supply Facility 20V AC AC/DC (PFC) DC/DC 12V DC (server) -4V DC (rectifier) Efficiency: 96.5% at half and 95.4% at full load for telecom rectifier 94% at half and 92% at full load for server power supply Power Factor: 0.95 at half-load and full load Power Density: >40 W/cub.inch Cost per Watt: <10 cents/w Design Cycle from Spec to Volume Production: < Months 6 PSMA Power Technology Road Map 2009: 3

4 0+ Platinum Server Power Supply Efficiency Breakdown Platinum 0+ requirements for server power supply are most challenging. Below is efficiency breakdown between PFC and DC/DC parts of Front- End AC/DC server power supply Pout AC-DC DC-DC PFC Power Factor Efficiency and Power Factor goals for Platinum Power Supply 10% 20% 50% 100% Post-PFC DC/DC Converter Topologies Comparison - Phase-Shift Full Bridge Mature ZVS topology Interleaving capability Improved modifications available using the same control + Fixed frequency PWM Can be designed to operate in different power saving modes At wide input voltage range the efficiency degrades because of circulating current during the freewheeling stage Interleaved Assymm. Half- Bridge Mature ZVS topology for one channel Simple control and minimum number of components Easy interleaving of any number of channels Scalable and efficient over wide load current range Duty cycle range is limited Difficult to maintain ZVS at wide input voltage range LLC Converters ZVS and ZCS of major switches Lower rated voltage Sync FETs Highest efficiency at maximum Vin, which is good for post-pfc converter Low EMI Difficult for interleaving and synchronization Frequency control Large ripple current through capacitors Non-trivial for optimal design Short circuit issue 4

5 Phase Shifted Full Bridge Converter 9 Soft switching (ZVS) No snubbers on primary side High frequency Highest efficiency Low EMI while ZVS is maintained Complex control Considerations for Highest Efficiency over Whole Load Range Optimal ratio between conduction and switching losses while FETs selection Primary FETs with low Coss Transformer with optimal turns ratio, Ls and Lµ to achieve ZVS Synchronous rectification on secondary side Adaptive optimal switching timing for all primary and secondary FETs Optimal output inductor to set boundary between CCM and DCM mode Optimal light load management algorithm + Vin 330V to 30V (420V peak) Q1 _ Q11 A Q1, Q2, Q11, Q22: IPB50R250CP, Rdson=0.22Ω typ. Coss Coss Q3, Q4: 3 in parallel each, IRF7749L2TRPbF Rdson =1.1mΩ Rpr=37.mΩ Q3 1T Lμ=736μH 24T 1T Co =,000μF - Vout + 12V Tr Llk=10μH Q4 Coss Coss B Q22 Q2 10 [3] [6] 5

6 Optimal Design Procedure Select ZVS allowing topology and number of channels based on efficiency design goals and output power level Optimize maximum efficiency point location where switching and conduction losses ratio are equal and select power switches and magnetics accordingly Find optimal Ls and Lµ to maintain ZVS over entire load current range Identify optimal DCM, Diode rectification and Burst mode regions, and phase shedding boundaries if multi-channel topology is selected Estimate optimal switching timing for all FETs as function of operating conditions Design cycle might take few iterations, so the use of design support software is very helpful 11 Optimal Pcond/Psw Selection with MathCAD Pcond low, Psw high Pcond & Psw optimal Pcond high, Psw low Optimal light load management in this region 12 Dots show efficiency design goals 6

7 Optimal Light Load Management Moving into DCM mode, sync. FETs in diode emulation mode, D significantly depends on load Diode rectification mode Duty Cycle 0.4 Setting Dmin=15.6% Burst Mode Area Load Current, A Vsmin Vsmax The region below DCM is identified where the diode emulation is maintained Diode rectification region is where synchronous MOSFETs drive losses become burden At very light current it is beneficiary to operate in burst mode to reduce power losses even further. Simplest way to operate in burst mode is by limiting minimum duty cycle Power Saving Control Algorithm vs Load Current Nominal Operation at Io from 20 to 100% Transition Mode at Io from 10 to 20% by gradually reducing synchronous FETs conduction time Diode rectification with DCM at Io <10% Burst Mode at no-load or very light load 14 7

8 Suggested Optimal Power Management Algorithm 15 UCC2950 Phase-Shifted Controller Utilizing Power Saving Algorithm + Vin _ CT Vdd A Vdd B E Vsense QA QC QB QD QE QF VREF UCC VREF GND 24 2 EA+ VDD 23 3 EA- OUTA 22 4 COMP OUTB 21 Enable 5 SS/EN OUTC 20 6 DELAB OUTD 19 7 DELCD OUTE 1 Vdd C Vdd D F Vsense Vdd A B C D E + Vout _ Accurate, adaptive ZVS timing over wide operating range as function of current sensing signal MOSFET Rectifier Outputs synchronized with primary switching as function of current sensing signal VREF DELEF OUTF 17 9 TMIN SYNC RT CS RSUM ADEL DCM ADELEF 13 F SYNC Light Load Power Management Block 16 [12]

9 UCC2950 Block Diagram Employing Green Features 20% Accurate Adaptive ZVS Dead Band Over Wide Operating Range Adaptive Timing MOSFET Rectifier Outputs Programmable SR ON/OFF Control Programmable Burst Mode at Very Light or No Load Programmable Slope Compensation Peak Current or Voltage Mode Control 20-mA, 1.5% Accurate VREF Regulator Closed Loop Soft Start with Enable % Accurate Switching Frequency Setting Bi-directional Synchronization 3% Accurate Cycle-by-Cycle Current Limit V DD Under Voltage Lockout Thermal Shutdown 150 µa Start Up Current Standard TSSOP-24 Package Wide Temperature Range: -40 to 125 C 17 VDD 12 VREF 1 COMP 2 Cycle-by- Cycle Ilim Is EA- 13 EA+ 4 RT 4 RSUM 4 CS 4 7.3V rise 6.7V fall VDD UVLO Comp. Lower + Input is Dominant [12] Oscillator Ramp Summing ON/OFF RAMP CS Thermal Shutdown 5V LDO CLK 2.V 0.V Synchronization Block VDD 4 SYNC PWM COMP 2 V CS 4 GND EN Light Load Efficiency Block DCM VDD Reference Generator Logic Block TMIN CS CS Programmable Delay AB CS Programmable Delay CD Programmable Delay EF Soft Start & Enable with 0.55 V Thershold SS/EN 10 ADEL OUTA 10 DELAB OUTB OUTC 10 DELCD OUTD ADELEF OUTE 10 DELEF OUTF Digital Controller UCD3K PSFB + Sync-Rec Configuration 1 9

10 Digital Controller C2000 PSFB + Sync-Rec Configuration Q14-Q15 Q7 Q13 Q11 Q2 Q1 Q ADC Comp Secondary Side Controller Piccolo-A P W M 19 MathCAD Program to Design Phase-Shifted Converter What it does: Designer enters key spec requirements: Input/Output, Efficiency etc. Program defines optimal ratio between switching and conduction losses Program sets Rdson limits for primary and secondary FETs Defines ZVS boundaries and suggests Ls and Lµ values to achieve ZVS Calculates efficiency and power losses to compare with design goals Provides power losses budget for further optimization if needed Generates basic waveforms for voltages and currents through power stage components 20 10

11 MathCAD Includes non-linear Coss Model to predict ZVS Coss 63pF Voss 100V Coss E( Vds) 2.9 Voss2 ln Vds 5 V V 43 pf Vds analytical equation for Coss energy of IPB50R250CP 7 Analytical plot versus DS 6 5 E( Vds) J Vds Left plot shows that analytical equation based curve used in MathCAD follows the data sheet plot based on experimental data 22 SIMPLIS Model of Phase-Shifted Converter What it does: Allows top level simulations of phase shifted full-bridge Dc-Dc converter Provides behavioral model for most functions and features of UCC2950 controller Simulates transitions between different operating modes: CCM, DCM, Burst Mode Simulation time is relatively short: For example full soft start simulation takes 6 min to 10 min depending on power stage configuration Provides small signal frequency response Bode plots 11

12 SIMPLIS Model for Power Stage R23 R R36 R7 10k Q3 STP20NM60FP R16 R R44 R10 10k Q5 STP20N M60FP 230u R4 VDD U3 FDP047AN0A0 C10 6.n IC =0 30 V4 OUTA 1u IC=0 4.7 R5 C3 TX2 Node A ILS OUTC IQ1 1u IC=0 4.7 R9 C7 TX3 Node B.7u IC=0 Vprimary L1 R6 5m 00u L4 ILu 37.m R15 IQ4 TX4 P1 S1 OUTE RTN Q2 Q1 2m R3 VQ4 R57 1.2k 4.u IC =0 ILo L2 Vout OUTB OUTD IQ2 S2 4.15m IC=0 C1 R1 120 IIN R26 12 R R40 R11 10k Q4 STP20NM60FP R12 12 R2 2.2 R47 R14 10k Q6 STP20NM60FP OUTC 220u R1 IQ3 X1 VD D U4 FDP047AN0A0 C4 6.n IC=0 R 6m 1:50 F1 20m OUTF RTN Q Q7 VQ3 R13 1.2k D1n414 D1 S1 DCM U2 C20 470p IC=0 R R65 10k D1n414 D2 R K R70 R k CS C21 100p IC=0 Vref R3 40k DCM DCM R37 20p IC=0 10k C5 10Meg 1 R31 R33 R34 10k VD D VD DOUTA C6 GNDOUTB Vref VR EF DELAB 300n IC=0 360k SYNOUTC C R27 RTDELCD R24 AD EL OUTD 1k DCM DELEF 50k CS OUTE TMINOUTF R35 R30 RSUM AD ELEF 10Meg SSEN EAP EAN COMP U1 144k 144k R22 R R20 OUTE OUTF RTN VD D U5 OUTA RTN VD D U6 OUTB RTN Vref R61 2k VD D U7 OUTC RTN 11.5 V2 VD D U OUTD VD D 12 V1 1 U13-VIN R29 1u IC=0 C2 C19 10n IC=0 C1 6k 10n IC=0 R60 C17 4.7n IC=0 4.3k R55 C16 7.5k 20m R63 2k 470p IC=0 R54 E2 23 [12] Phase-Shifted Converter Design Example Input voltage: 300V to 400V Output voltage: 12V Output current: 55A Efficiency: up to 95.5% Includes bias supply and fan Size of DC/DC converter portion only: 10 x 2 x 1 Power Density 36W/cub. Inch Overall size: 15 x 2 x [3] 12

13 Phase-Shifted Converter Picture Bias Supply Fan Power Stage Control Card DC/DC Converter Portion Size: 10 x 2 x 1 25 Power Stage Schematic 26 13

14 Control Card Schematic 27 Measured Efficiency of 660W Phase-Shifted Converter Using UCC Efficiency, % Load current, A Vin = 400V with Lres Vin = 350V with Lres Vin = 300V with Lres Small difference between efficiencies at different input voltages indicate minimum switching losses of this design Efficiency curve is flat over wide load current range because of light load power management technique 14

15 Summary Power Saving and Efficiency Design Goals for Post-PFC Converter have been set based on Standards and Regulations PSFB Converter efficiency enhancing technique over entire load current range has been discussed Analog and Digital controllers capable to utilize optimal power saving algorithm have been listed MathCAD and SIMPLIS based design tools have been introduced and test results of prototype have been presented 29 Thanks and Any Questions? 30 15

16 References REFERENCES 1. Fasullo, G.; Kania, M. & Pitts, A. (200). The Green revolution in DC power systems, Proceedings of 30th International Telecommunications Energy Conference, INTELEC 200, pp. 1-7, ISBN: , San Diego, CA, USA, September 200, IEEE 2. Mammano, R. (2006). Improving power supply efficiency - The global perspective, Texas Instruments Power Supply Design Seminar, Topic 1, SEM-1700, Rais Miftakhutdinov, Power Saving Control Strategies and Their Implementation in DC/DC Converter for Data and Telecommunications Power Supply, Proc. of IEEE Applied Power Electronics Conf., 2010, pp Rais Miftakhutdinov, Zhenyu Yu, New Controller Addresses Energy Saving in Server Power System, Power Systems Design North America, January/February Issue, 2010, pp Rais Miftakhutdinov, Power Saving Solutions in DC/DC Converter for Data and Telecommunications Power System, Proc. of PEDS-2009, Taipei, November Rais Miftakhutdinov, Energy Saving Drives New Approaches to Telecommunications Power System, Chapter in the book Telecommunications, Intech, ENERGY STAR program requirements for computer servers, version 1.0: 0 PLUS Power Supplies Requirements: 9. Climate Savers Computing Initiative: Texas Instruments, Datasheet: TMS320F2023 PiccoloTM microcontroller, 11.Texas Instruments, Datasheet: UCD3020 Digital Power Controller, 12.Texas Instruments, Datasheet: Green Phase-Shifted Full-Bridge controller with synchronous rectification, UCC2950,