Disclosure to Promote the Right To Information

Transcription

1 इ टरन ट म नक Disclosure to Promote the Right To Information Whereas the Parliament of India has set out to provide a practical regime of right to information for citizens to secure access to information under the control of public authorities, in order to promote transparency and accountability in the working of every public authority, and whereas the attached publication of the Bureau of Indian Standards is of particular interest to the public, particularly disadvantaged communities and those engaged in the pursuit of education and knowledge, the attached public safety standard is made available to promote the timely dissemination of this information in an accurate manner to the public. ज न1 क अ+धक र, ज 1 क अ+धक र Mazdoor Kisan Shakti Sangathan The Right to Information, The Right to Live प0र 1 क छ ड न' 5 तरफ Jawaharlal Nehru Step Out From the Old to the New IS (1979): Detail specification for digital integrated circuits, Part 1: Nand gate, TTL, Section 1: Single, 8 input, positive [LITD 5: Semiconductor and Other Electronic Components and Devices]! न $ एक न' भ रत क +नमण Satyanarayan Gangaram Pitroda Invent a New India Using Knowledge! न एक ऐस खज न > ज कभ च0र य नहB ज सकत ह ह Bhartṛhari Nītiśatakam Knowledge is such a treasure which cannot be stolen

2

3

4 UDC : m 1 I DETAIL SPECIFICATION Indian Standard IS : 9414 ( Part I/Set 1 ) 1979 FOR DIGITAL INTEGRATED CIRCUITS PART I NAND GATE, TTL Section 1 Single, 8 Input, Positive 1. ScopeCovers two types of NAND gates based on their operating temperature range and other electrical characteristics ( Type l* and Type 2t ). 1.1 Refer to IS: 7441 (Part I j1974 Essential ratings and characteristics of digital integrated circuits: Part I General format. 1.2 The assigned type number shall be prominently displayed on the device. 2. Description Category of device Digital combinatorial Configuration Transistortransistorlogic ( TTL ) Function Positive NAND gate Gates per package One Inputs per gate 8 Inputs Outputs per gate 1 output Technology used Bipolar Constructional detail Monolithic Material Silicon 3. Outlines and Connections 3.1 Outlines and Encapsulation Type of Device Outline Encapsulation Under consideration Ceramic Type 2 IS : 5000 (OD 15) 1973* Ceramic or plastic *Dimensions of semiconductor devices and integrated circuits: Device outline OD Logic Diagram and Connections The logic diagram and pin connections shall be as shown in Fig Functional Specification FIG. 1 PIN CONNECTIONS 4.1 Block Diagram The block diagram of a typical input NAND gate is shown in Fig. 2. * corresponds to commercial type jtype 2 corresponds to commercial type Adopted 13 August 1979 INDIAN STANDARDS INS I I I u I IUN MANAK BHAVAN, 9 BAHADUR SHAH ZAFAR MARG NEW DELHI

5 IS : 9414 ( Part I/Set 1) cc 2 OUTPUT FIG. 2 BLOCK DIAGRAM 4.2 Schematic Diagram ( Each Gate ) The schematic diagram of the gate is shown in Fig. 3. Lkn INPUT OUTPUT =? FIG. 3 SCHEMATIC DIAGRAM Note The components and values are given only as an example The details of the schematic diagram should always be specified or indicated by the manufacturer. 4.3 Funcfion See Table 1. TABLE 1 FUNCTION Input I Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 output 9 ( 1 (2) (5) (4) (5) (6) (7) (3) (9) H H H H H H H H L Note All other combinations of H and L at the input give H output. H Y High state, most positive ( least negative ). l. = Low state, least positive ( most negative ).!j. Ratings (Absolute Maximum ) 5.1 Electrical Ratings Rating Supply voltage Vcc Input voltage VIN Walue ~~~~~_~h ~~_~~ Max Min 17.0 v 0 5 v Remarks v f These voltages are with respect I.5 v t to ground terminal (At high level input I current H of 12 ma 1 Max ) 1 2

6 IS : 9414 ( Part I/Set 1) Conditions for recommended operation a) Supply voltage Type of Device Supply Voltage Vcc Volts r h,~ Min Nom Max Type o 5.25 b) Output loading capability ( fan out ), N = 10 Max DC noise margins M, = V IHA VOHA = Not applicable M2 = VOHB VIHB m 400 mv Ma VILA VOLA = 400 mv M., = VOLB VILE m Not applicable NoteFor explanation of the symbols given above, reference to 10.1 of IS : 7441 ( Part I ) ly74 may be made. 5.2 Temperature Ratings a) b) 4 Operating temperature 55 C to +125Yz Type 2 0% Storage temperature Type C Junction Type 2 temperature 175 C to $7O C to +150 c d) Thermal resistance ( junction to case ) 0*03 C/m W Type 2 0*08X/m W 5.3 Power Dissipation ( Typical) 40 mw/gate at 50 percent duty cycle Type 2 IO mw/gate at 50 percent duty cycle 5.4 Marking Refer to IS : 9596 General requirements and classification of tests for microcircuits. 6. Electrical Characteristics 6.1 Electrical characteristics shall be as specified in Table 2. The values specified apply over the full operating temperature range [see 5.2(a) 1.

7 IS : 9414 ( Part I/&c 1) 1979 TABLE 2 ELECTRICAL CHARACTERlSTlCS ( Clause 6.1 ) Characteristics Symbol Clause No. Condition Limit of IS:9501 h (Part I ) Min 1980* (1) a) Functional Tests i) Verification of type of microcircuit (2) (3) 4 (4) (5) Remarks b) Static Tests i) High level output VOH IO WCC = min 2.4 v See Note 1 /OH = 400 PA VIL = 0.8 V ii) Low level output VOL 9 TVcc = min See Note 2 voltage VIH = 2v for all inputs of gate under test iii) Input clamp voltage VI /ol = 16 ma 1.5 v +Vcc = min iv) High level input voltage v) Low level input voltage vi) High level input current (each input ) vii) High level input current (each input) viii) Low level input current (each input ) ix) Short circuit output current x) High level supply current per gate xi) Low level supply current per gate c) Switching Jests Type I, At 25 C Vcc = nom i) Propagation delay time, hightolow level ii) Propagation delay time, lowtohigh Type f at 55 C and _t125 C and Vcc = nom iii) Propagation delay time, hightolow level iv) Propagation delay time, lowtohigh level Type 2 at 25 C, Vcc = nom v) Propagation delay time, hightolow level vi) Propagation delay time, lowtohigh leve I VIH VIL H H /IL 10s kch /CCL tphl tplh tphl blh tphl ~PLH 8 8 th = 12 ma tvcc = min tvcc = min tvcc VIH tvcc VIH = max = 2 4 V = max =5 5V 2.0 ~VCC = max 0.7 ma VIL = 0.4 v +Vcc = max 20 ma V_ = ov tvcc = max tvcc = max VIH = 5.5 CL RL = 50 pf = 39OQ CL = 50 pf RL = 39on CL = 50 pf RL = 39oB CL = 50 pf RL = CL = 15 pf RL = 39oQ CL 2 15 pf RL 39oB Note 1 ~ All unspecified inputs at Vcc ~ max. Note 2 All unspecified inputs grounded. Note 3 Not more than one output should be shorted at a time ns 3 ns 3 ns 3 ns Max (6) PA ImA (for ) and 100!rA ( for Type 2) 1.6 ma for 1.6 ma for Type 2 55 ma I.65 ma *Methods of measurement of electrical characteristics of microcircuits: Part I Digital microcircuits jfor value of L/cc reference should be made to 5.1(a). 5mA 20 ns 25 ns 24 ns 27 ns 15 ns ns (7) See Note 2 See Note 2 See Notes 2 and 3 See Note 1 )ee Note 2 4

8 7. Environmental Data a) Temperature severity (cold/ dry heat ) b) Damp heat 55 C/125 C Composite temperature/humidity cyclic IS : 9414 ( Part l/set 1) 1979 Type 2 o c/7o c Not Applicable c) Shock d) Acceleration (steady state ) 15 km/s* 200 km/s* 15 km/s* 200 km/s* e) Vibration 20 g, Hz, 6 hours 20 g, Hz, 6 hours 8. Tests 8.1 The provisions for type approved procedure and batch acceptance procedure as given in IS : 9596 shall apply. 8.2 The test schedule and requirements shall be as given in Table 3. SI No. No. of Specimens (1) (2) a) Group 0 i) All ii) All b) Group 1 i) 6 or as applicable ii) iii) 9, c) Group 2 ii) I# iii) d) Group 3 ii) I, iii),i iv) e) Group 4 ii) 8, iii) iv) f) Group 5 g) Group 6 ii) h) Group 7 ii) TABLE 3 TEST SCHEDULE AND REQUIREMENTS Visual Initial Test (3) Examination Measurements: Physical dimensions Marking permanency Solderability Robustness Sealing Final Measurements: of termination Impact ( shock ) Vibration Acceleration steadystate Final measurements: Thermal shock Change of temperature Damp heat ( cyclic ) Final Measurements: Corrosive atmosphere (salt mist ) Life ( high temperature, nonoperating ) Final Measurements: Life ( steady state OPCratiOn ) Final Measurements: ( Clause 8.2 ) Clause of IS : 9597 (Part I)* (4) I Condition of Test and Requirements (5) (6) See Table 2 Lead fatigue Fine leak Gross teak See Table 2 15 km/@ 20 g, Hz, 6 h 200 km/s2 See Table 2 and Type 2 *, and Type 2 11 t, 55 C/125 C 65 C/155 C and Type 2 6 cycles, 16 hours Type 2 See Table 2 and Type 2 and Type 2 See Table 2 9, See Table; *General requirements and environmental and life tests for integrated circuits.. Part I Environmental tests. jthis column specifies the type of device to which the test concerned is applicable. Remarks? and Type 2 j _._ Prmted at New India Prlntlrrg Press, Khurla, India