2.0 Watt Class-D Audio Amplifier with Integrated Boost Regulator and Automatic Gain Control

Transcription

1 FAB32 2. Watt Class-D Audio Amplifier with Integrated Boost Regulator and Automatic Gain Control Features High Output, High-Efficiency, Class-D Mono Speaker Amplifier Low EMI Design Allows Filterless Operation High Noise Rejection Using Differential Audio Inputs High-Efficiency Boost Regulator Provides Higher Output Power Over Battery Voltages Boost Shutdown at Lower Output Power Increases Efficiency and Reduces Quiescent Current Consumption Automatic Gain Control (AGC) Monitors Battery Voltage and Dynamically Adjusts Gain, Extending Battery Runtime Short-Circuit Protection Low-Voltage Shutdown Click and Pop Suppression Available in 2-Bump WLCSP Ordering Information Description September 2 The FAB32 is a mono, Class-D, boosted audio amplifier with differential audio inputs. An integrated boost regulator allows for high output power over a power supply range of 2.5V to 5.2V. At low output power, the boost regulator automatically shuts down for greater efficiency and lower quiescent current consumption. Automatic Gain Control (AGC) reduces gain when the power supply voltage is low to limit maximum current consumption. Figure. Typical Application Circuit Part Number Operating Temperature Range Package Packing Method FAB32UCX -4 C to +85 C 2-Bump,.5mm Pitch, Wafer-Level Chip-Scale Package (WLCSP) 3 Units on Tape & Reel FAB32 Rev. 2..3

2 Pin Configuration Pin Definitions Figure 2. 2-Bbump,.5mm Pitch WLCSP, Top View WLCSP Name Type Description B OUT+ Output Positive audio output C OUT- Output Negative audio output C3 IN+ Analog input Positive audio input D3 IN- Analog input Negative audio input C2 EN CMOS input B2 AGCT Analog input AGC trip point setting B3 VBATT Power Supply voltage Shutdown signal for boost regulator and amplifier: VBATT=enabled, PGND=shutdown (internal 3KΩ pull-down) A2 SW Power Boost regulator switching node A PVDD Power Boost regulator output A3 BGND Ground Boost regulator ground connect to PGND and AGND with a ground plane. D PGND Ground Power ground connect to BGND and AGND with a ground plane. D2 AGND Ground Analog ground connect to BGND and PGND with a ground plane. FAB32 Rev

3 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V BATT Voltage on VBATT Pin V V OUT Voltage on OUT-, OUT+ Pin -.3 V BSTOUT +.3 V V IN Voltage on SW, IN-, IN+, EN, AGCT Pin -.3 V BATT +.3 V P D Power Dissipation Internally Limited Dissipation Ratings Symbol Parameter Min. Typ. Max. Unit T J Junction Temperature 5 C T STG Storage Temperature Range C T L Lead Temperature (Soldering, s) 3 C JA Thermal Resistance, JEDEC Standard, Multilayer Test Boards, Still Air Electrostatic Discharge Protection 77 C/W Symbol Parameter Condition Level Unit ESD Human Body Model (HBM) EIA/JESD22-A4 ±3 KV Charged Device Model (CDM) Recommended Operating Conditions According to "EIA/JESD22-C Level III" Compatible with "IEC Level C4" or "ESD-STM Level C4" ± KV The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit T A Operating Temperature Range C V BATT V BATT Supply Voltage Range V L SW Inductor (at Peak Inductor Current:.5A) () µh C VBATT VBATT Capacitor () 2.. µf C PVDD PVDD Capacitor () µf C AGCT Capacitive Load on AGCT pf R L Load Resistance 3.5 Ω Note:. Minimum passive component values include temperature, tolerance, and aging. FAB32 Rev

4 Electrical Characteristics Unless otherwise noted: AGCT=GND, R L =8Ω + 33µH, f=khz, and audio measurement bandwidth=22hz to 2KHz (AES7). Typical values are at V BATT =3.6V, T A =25 C, with typical external component values. Minimum and maximum values are at V BATT =2.5V to 5.2V, T A =-4 C to 85 C, with minimum external component values. Symbol Parameter Conditions Min. Typ. Max. Unit I DD I SD t WU f SW(AMP) V OS Quiescent Current Shutdown Current Wake-Up Time Class D Switching Frequency Differential Output Offset Voltage Inputs AC Grounded, R L=Open, EN=HIGH With Class-D Edge Rate Control Without Class-D Edge Rate Control EN=PGND, Inputs AC Grounded, V BATT=3.6V, T A=25 C From LOW to HIGH EN Transition to Full Operation ma. 2 µa 5 2 ms 3 KHz Inputs AC Grounded mv A V Gain AGC Inactive V/V R IN R STD V STD THD+N P O I DLMT Input Resistance Single-Ended Input Impedance During Shutdown Maximum Single-Ended Input Voltage Swing During Shutdown THD+N Added to Audio Signal at Inputs During Shutdown Total Harmonic Distortion Plus Noise Output Power Class-D Output Current Limit Gain=V/V (AGC Inactive) EN=PGND, AC-Coupled Inputs, V INx < 2V rms per Input Differential Single-Ended KΩ 8 KΩ EN=PGND, AC-Coupled Inputs 2 V rms EN=PGND, AC-Coupled Inputs, Source Impedance < Ω f=3hz, P OUT=mW.3 f=khz, P OUT=mW.3 f=khz, P OUT=mW.2 f=3hz, P OUT=W.3 f=khz, P OUT=W.3 f=khz, P OUT=W.2 f=3hz to KHz, P OUT=mW to.7w, V BATT=3.6V, T A=25 C THD+N %, f=3hz to KHz, V BATT 3.6V R L=8Ω+33µH, T A=25 C.7 R L=4Ω+33µH, T A=25 C 2. R L=8Ω+33µH, T A=-4 C to 85 C R L=4Ω+33µH, T A=-4 C to 75 C %. % W.4 A Continued on the following page... FAB32 Rev

5 Electrical Characteristics Unless otherwise noted: AGCT=GND, R L =8Ω + 33µH, f=khz, and audio measurement bandwidth=22hz to 2KHz (AES7). Typical values are at V BATT =3.6V, T A =25 C, with typical external component values. Minimum and maximum values are at V BATT =2.5V to 5.2V, T A =-4 C to 85 C, with minimum external component values. Symbol Parameter Conditions Min. Typ. Max. Unit PSRR CMRR Power Supply Rejection Ratio Common Mode Rejection Ratio Inputs Shorted, AC Grounded, Input Referred; V RIPPLE=2mV P-P Square Centered Around V BATT=3.8V, 5% Duty Cycle, µs Rise/Fall Time V RIPPLE=2m V P-P Square, 5% Duty Cycle, µs Rise/Fall Time, Inputs Shorted and AC-Coupled to V RIPPLE f RIPPLE=KHz, Boost Enabled f RIPPLE=27Hz, Boost Enabled f RIPPLE=KHz, Boost Bypassed f RIPPLE=27Hz, Boost Bypassed f RIPPLE=KHz 55 f RIPPLE=27Hz 5 V BIAS IN+, IN- Bias Voltage.2 V SNR e n Efficiency with Class-D Edge Rate Control Efficiency without Class- D Edge Rate Control Signal-To-Noise Ratio Output Noise R L=8Ω+33µH, P OUT=.7W 73 R L=4Ω+33µH, P OUT=2.4W 67 R L=8Ω+33µH, P OUT=.7W 74 R L=4Ω+33µH, P OUT=2.4W 68 P OUT=.7W, R L=8Ω+33µH, A-Weighted 96 P OUT=.7W, R L=8Ω +33µH, Unweighted 94 P OUT=2.W, R L=4Ω +33µH, A-Weighted 94 P OUT=2.W, R L=4Ω +33µH, Unweighted 9 A-Weighted 59 Unweighted 76 T STD Thermal Shutdown Junction Temperature 65 C T HYS V ULVO V HYS f SW(REG) I LIMIT(SU) t INRUSH Thermal Shutdown Hysteresis V BATT Under-Voltage Shutdown V BATT Under-Voltage Hysteresis Boost Converter Switching Frequency Boost Converter Inrush Current Limit Boost Converter Inrush Time db db % db µv rms Junction Temperature 25 C V T A=25 C 2 3 mv P OUT=.7W.2 MHz PV DD Rising from V to V BATT, C PVDD=22µF 6 ma PV DD Rising from V to V BATT, C PVDD=22µF µs Continued on the following page... FAB32 Rev

6 Electrical Characteristics Unless otherwise noted: AGCT=GND, R L =8Ω + 33µH, f=khz, and audio measurement bandwidth=22hz to 2KHz (AES7). Typical values are at V BATT =3.6V, T A =25 C, with typical external component values. Minimum and maximum values are at V BATT =2.5V to 5.2V, T A =-4 C to 85 C, with minimum external component values. Symbol Parameter Conditions Min. Typ. Max. Unit I BST t BSTSRT I BOOST V BSTOUT V BSTSTD t HOLD V AGC Auto Boost Startup Current Limit Auto Boost Startup Time Auto Boost Startup Current Ramp Rate Boost Converter Peak Input Current Limit Boost Converter Output Voltage Auto Boost Shutdown Threshold Voltage Auto Boost Shutdown Hold Time AGC Trip Point Output Power with AGC PV DD Rising from V BATT to 5.6V, C PVDD=22µF 2 ma PV DD Rising from V BATT to 5.6V, C PVDD=22µF, V BATT=3.6V, T A=25 C PV DD Rising from V BATT to 5.6V, C PVDD=22µF, V BATT=3.6V, T A=25 C 2 µs 5 ma/µs Open-Loop Limit, V BATT=3.6V, T A=25 C 6 2 ma V BATT=3.6V, T A=25 C V 2 V pk 25 ms AGCT=Floating AGCT=GND AGCT=VBATT AGCT=GND, V IN=.4V pk, KHz Sine Wave V BATT=3.4V.79 V BATT=3.V.45 t A AGC Attack Time 2 µs/ db t R AGC Release Time 6 ms/db AGC Step Size.5 db V IH V IL AGC Maximum Attenuation EN Logic Input High Voltage EN Logic Input Low Voltage V W db. V.45 V C IN EN Capacitance pf R PD EN Pull-Down Resistance 3 KΩ FAB32 Rev

7 Typical Performance Characteristics Unless otherwise noted: AGCT = GND, R L = 8Ω + 33µH,, audio measurement bandwidth 22Hz to 2KHz (AES7), V BATT = 3.6V, T A = 25 C, typical external component values. Supply Current (ma) THD+N (%) Supply Current (A) Inputs AC grounded Class-D egde rate control disabled Class-D edge rate control enabled Supply Voltage (V) Figure 3. Quiescent Supply Current vs. Supply Voltage VBATT=4.8V VBATT=4.2V VBATT=3.6V VBATT=2.8V... Figure 5. Total Harmonic Distortion + Noise vs. Output Power Class-D edge rate control disabled Boost edge rate control enabled VBATT = 5.2V VBATT = 4.2V VBATT = 3.6V VBATT = 2.8V Amplitude (dbv) THD+N (%) Efficiency (%) Frequency (KHz) Figure Inputs AC grounded Figure 6. A-Weighted Output Noise vs. Frequency Po = mw Po = W Frequency (Hz) Total Harmonic Distortion + Noise vs. Frequency Class-D edge rate control disabled Boost edge rate control enabled VBATT=5.2V VBATT=4.2V VBATT=3.6V VBATT=2.8V.. Figure 7. Supply Current vs. Output Power Figure 8. Efficiency vs. Output Power FAB32 Rev

8 Typical Performance Characteristics Unless otherwise noted: AGCT = GND, R L = 8Ω + 33µH,, audio measurement bandwidth 22Hz to 2KHz (AES7), V BATT = 3.6V, T A = 25 C, typical external component values. Supply Current (A) Supply Current (A) Supply Current (A) Class-D edge rate control disabled Boost edge rate control disabled VBATT = 4.2V VBATT = 3.6V VBATT = 2.8V Figure 9. Supply Current vs. Output Power Class-D edge rate control enabled Boost edge rate control enabled Figure. Supply Current vs. Output Power Class-D edge rate control enabled Boost edge rate control disabled VBATT = 4.2V VBATT = 3.6V VBATT = 2.8V VBATT = 4.2V VBATT = 3.6V VBATT = 2.8V Efficiency (%) Efficiency (%) Efficiency (%) Class-D edge rate control disabled Boost edge rate control disabled.. Figure. Efficiency vs. Output Power Class-D edge rate control enabled Boost edge rate control enabled Figure 2. Efficiency vs. Output Power VBATT=4.2V VBATT=3.6V VBATT=2.8V VBATT=4.2V VBATT=3.6V VBATT=2.8V.. Class-D edge rate control enabled Boost edge rate control disabled VBATT=4.2V VBATT=3.6V VBATT=2.8V.. Figure 3. Supply Current vs. Output Power Figure 4. Efficiency vs. Output Power FAB32 Rev

9 Typical Performance Characteristics Unless otherwise noted: AGCT = GND, R L = 8Ω + 33µH,, audio measurement bandwidth 22Hz to 2KHz (AES7), V BATT = 3.6V, T A = 25 C, typical external component values. Supply Current (A) Supply Current (A) R L = 4Ω + 33µH Class-D edge rate control disabled Boost edge rate control enabled VBATT = 5.2V VBATT = 4.2V VBATT = 3.6V VBATT = 2.8V Figure 5. Supply Current vs. Output Power R L = 4Ω +33µH Class-D edge rate control disabled Boost edge rate control disabled VBATT = 4.2V VBATT = 3.6V VBATT = 2.8V Figure 7. Supply Current vs. Output Power Efficiency (%) Efficiency (%) R L = 4Ω + 33µH Class-D edge rate control disabled Boost edge rate control enabled.. Figure 6. Efficiency vs. Output Power R L = 4Ω + 33µH Class-D edge rate control disabled Boost edge rate control disabled Figure 8. Efficiency vs. Output Power VBATT=5.2V VBATT=4.2V VBATT=3.6V VBATT=2.8V VBATT=4.2V VBATT=3.6V VBATT=2.8V.. FAB32 Rev

10 Detailed Description Signal Path The FAB32 features a fully differential signal path for noise rejection. The low-emi design allows the OUT+ and OUT- pins to be connected directly to a speaker without an output filter. The input section includes an 8KHz low-pass filter for removing out-of-band noise from audio sources, such as sigma delta DACs. Shutdown If EN is grounded, the Class-D amplifier and the boost regulator are turned off. IN+ and IN- are high impedance. Audio signals present at IN+ and IN- with amplitude less than the maximum differential input voltage swing are not distorted by the FAB32 (see electrical characteristics). When EN transitions from LOW to HIGH, during the wake-up time (see Electrical Characteristics) the FAB32 charges the input DC blocking capacitors to the Common Mode voltage before enabling the Class-D amplifier. To minimize click and pop during turn-on, audio signals should not be present during the wake-up period. Other devices that are connected to the same input signal, if not muted, may experience a pop due to this capacitor charging. There is no limitation on the length of shutdown. Remaining charge on the PVDD capacitor at startup (for example, if EN is LOW for only a short period) does not affect startup behavior. The EN pin has an internal 3KΩ pull-down resistor. EN must be LOW when V BATT is lower than the V BATT under-voltage shutdown voltage (see Electrical Characteristics). EN must remain LOW for at least µs after V BATT rises above the V BATT under-voltage shutdown voltage. Class-D Amplifier Over-Current Protection If the output current of the Class-D amplifier exceeds limits (see the Electrical Characteristics), the amplifier is disabled for approximately one second. (Other systems, such as the boost regulator and AGC, remain active.) After one second, the amplifier is re-enabled. If the fault condition still exists, the amplifier is disabled again. This cycle repeats until the fault condition is removed. Low EMI To minimize EMI, edge rate control for the boost regulator and Class-D amplifier can be employed. The boost regulator's rise and fall times are set to 2ns per transition by default. For devices with ns boost edge rates or disabled boost regulator edge-rate control, contact a Fairchild Representative. This is a factory option that cannot be changed in the application. The Class-D amplifier's edge rate control is disabled by default. For devices with 2ns Class-D edge rates, contact a Fairchild Representative. This is a factory option that cannot be changed in the application. Automatic Boost Shutdown Automatic boost shutdown changes the Class-D amplifier supply voltage as a function of audio output level. At audio output levels above 2V pk, the boost converter generates 5.65V from the input battery voltage. If the output level is below 2V pk for more than 25ms, the boost converter is switched off and the Class-D amplifier is supplied directly from the battery. As a result, efficiency is improved at low audio output levels and quiescent current consumption is reduced. FAB32 Rev. 2..3

11 V IN (V) PV DD (V) Battery Current (A) Auto Boost Startup Time Boost Converter Peak Input Current Limit Auto Boost Startup Current Limit Figure 9 shows an example of an auto boost startup event. At first, the boost converter is off and PVDD is the same voltage as VBATT. At 2µs, a large audio signal is presented at the inputs, which causes the boost converter to start up. From 2µs to 2µs, battery current is ramped up from A to the auto boost startup current Limit of.5a for the duration of the auto boost startup time. The auto boost startup current ramp rate is 5mA/µs. These limits are enforced to avoid sudden current draw spikes from the battery. At 2µs, after the auto boost startup time, the ramp is released and battery current falls to a level capable of sustaining the speaker amplifier s outputs. At 6µs, the input signal begins to rise, which increases battery current. At 8µs, the boost converter peak input current limit is enforced and battery current levels off, which causes PV DD to droop. The boost regulator should not be used to drive any loads other than the Class-D amplifier. Time (µs) Figure 9. Auto Boost Startup Automatic Gain Control Due to constant output power, the amount of VBATT current needed to maintain a given output amplitude is inversely proportional to VBATT voltage. This produces very large current requirements at low V BATT. The AGC eases low-vbatt current demands by reducing the gain when VBATT voltage drops below a trip point. One of three different trip points may be selected by shorting AGCT to VBATT, shorting AGCT to PGND, or floating AGCT (see Electrical Characteristics). The trip point is determined upon power-on and when EN transitions from LOW to HIGH. If AGCT is changed during operation, the new value is not read until power or EN is cycled. When V BATT is above the trip point, the AGC has no effect on the signal path. When V BATT is at or below the trip point, target gain is reduced in.5db steps according to the equation: FAB32 Rev. 2..3

12 G S VT V Vout G t arg et I LGI batt () max where: G I = Initial Gain (V/V); S L = 3V/V Slope; V OUTMAX = 5.2V; V T = AGC Trip Point Set by the AGCT Pin; and = Voltage at the VBATT Pin. V BATT Target gain can be reduced by as much as db. Note that the state of auto boost shutdown has no effect on the AGC. Figure 2 shows target gain vs. battery voltage. Target Gain (V/V) Line Color AGCT Configuration AGC Trip Point (V) Red Float 3.25 Green Ground 3.55 Blue V BATT 3.75 Figure 2. Target Gain vs. Battery Voltage Figure 2 is similar to Figure 2 except that the target gain is expressed in db rather than V/V. Target Gain (db) Line Color AGCT Configuration AGC Trip Point (V) Red Float 3.25 Green Ground 3.55 Blue V BATT 3.75 Figure 2. Target Gain vs. Battery Voltage V BATT (V) V BATT (V) Figure 22 shows examples of peak output voltage vs. battery voltage. V OUT (V pk ) Line Color AGCT Configuration AGC Trip Point (V) Input Voltage (V pk ) Red Float Green Ground Blue V BATT Magenta Float Cyan Ground Black V BATT Figure 22. Output Voltage vs. Battery Voltage Figure 23 shows examples of output power vs. battery voltage with a.4v pk sinusoidal input signal. P OUT (W) V IN =.4V pk V IN =.3V pk V BATT (V) R L = 4Ω + 33µH R L = 8Ω + 33µH V BATT (V) Line Color AGCT Configuration AGC Trip Point (V) Input Voltage (V pk ) Red Float Green Ground Blue V BATT Magenta Float Cyan Ground Black V BATT Figure 23. Output Power vs. Battery Voltage Examples (V IN =.4V pk Sine) FAB32 Rev

13 The speed at which gain can change is limited (see Electrical Characteristics); therefore, the actual gain may lag the target gain if V BATT voltage changes quickly. Figure 24 and Figure 25 show examples of AGC changes over time. In these examples, AGCT is grounded, so the AGC trip point is 3.55V.. Initially, V BATT is 3.6V and gain is V/V (2dB). 2. A narrow V BATT drop of less than 2µs is ignored by the AGC. 3. The next V BATT drop lasts longer and the AGC is tripped. The initial.5db gain reduction occurs 3.9µs after V BATT crosses below the 3.55V trip point. Figure 24. AGC Changes vs. Time, Example 4. V BATT is now 3.V, so target gain is V/V 3V/V V/V [(3.55V 3.V) / 5.2V]=7.4V/V=7.4dB. 5. Gain continues to drop by.5db every µs until it is below the target gain, where it settles at 7.dB. 6. When V BATT rises above the trip point, gain increases by.5db. If more than 8ms has passed since the last gain change, gain rises immediately as shown in Figure 24. Otherwise, gain does not rise until after 8ms has passed, as shown in Figure While V BATT remains above the trip point, gain continues to increase by.5db every 8ms until it returns to 2dB. Figure 25. AGC Changes vs. Time, Example 2 FAB32 Rev

14 The intent of the AGC circuitry is to limit current draw from the battery to extend runtime. This is particularly important for handsets that incorporate advanced shutdown algorithms that measure battery voltage. The AGC circuit dynamically adjusts the amplifier gain depending on the trip point used. Even though the amplifier gain is reduced in response to lower battery Applications Information Layout Considerations General layout and supply bypassing play a major role in analog performance and thermal characteristics. Fairchild offers an evaluation board to guide layout and aid device evaluation. Following this layout configuration provides optimum performance for the device. For best results, follow the steps and recommended routing rules listed below. Recommended Routing/Layout Rules Do not run analog and digital signals in parallel. Traces must run on top of the ground plane. Avoid routing at 9 angles. Place bypass capacitors within 2.54mm (. inches) of the device power pin. Minimize all trace lengths to reduce series inductance. Connect BGND, PGND, and AGND together using a single ground plane. voltages, two conditions result in continued higher current draw: ) the handset volume is turned up in an attempt to maintain the same loudness, or 2) the input signal is increased. If one or both of these conditions exist, even though the amplifier gain is reduced in response to lower battery voltage, current draw remains elevated, eventually resulting in handset shutdown. Figure 26. Recommended PCB Layout Table Recommended Passive Components Component Vendor Part Number Value L SW Murata LQM2HPN2R2NJCL 2.2µH C PVDD Murata GRM2AR6J226UE8K 22µF C VBATT Murata GRM88R6J6UE82J µf FAB32 Rev

15 Physical Dimensions 2X.3 C PIN AREA.5 D C B A D TOP VIEW C F E.5 C 2 3 BOTTOM VIEW Product Dimensions A B (X)+/ X.3 C SEATING PLANE F D F.5 C A B 2x Ø.26±.2 F (Y)+/-.8.6 C E SIDE VIEWS (Ø.2) CU PAD RECOMMENDED LAND PATTERN (NSMD).378±.8 Figure Ball WLCSP, 3x4 Array,.5mm Pitch, 25µm Ball.28±.2 (Ø.3) SOLDER MASK OPENING NOTES: A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCE PER ASME Y4.5M, 994. D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS ±39 MICRONS ( MICRONS). F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. G. DRAWING FILNAME: MKT-UC2AErev Product D E X Y FAB32UCX.86mm.44mm.22mm.8mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent version. Package specifications do not expand Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. A Always visit Fairchild Semiconductors online packaging area for the most recent packaging drawings and tape and reel specifications. FAB32 Rev

16 FAB32 Rev