USER S MANUAL. Series IP483 Industrial I/O Pack Counter Timer Module

Transcription

1 Series IP483 Industrial I/O Pack Counter Timer Module USER S MANUAL ACROMAG INCORPORATED Tel: (248) South Wixom Road Fax: (248) P.O. BOX 437 Wixom, MI U.S.A. Copyright 2004, Acromag, Inc., Printed in the USA. Data and specifications are subject to change without notice D11M004

2 2 TABLE OF CONTENTS IP483 Industrial I/O Pack User s Manual Counter Timer Module IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power, wiring, component, sensor, or software failure in the design of any type of control or monitoring system. This is very important where property loss or human life is involved. It is important that you perform satisfactory overall system design and it is agreed between you and Acromag, that this is your responsibility. 1.0 General Information The information of this manual may change without notice. Acromag makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Further, Acromag assumes no responsibility for any errors that may appear in this manual and makes no commitment to update, or keep current, the information contained in this manual. No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag, Inc. KEY IP483 COUNTER/TIMER FEATURES INDUSTRIAL I/O PACK INTERFACE FEATURES... 5 SIGNAL INTERFACE PRODUCTS 5 IP MODULE ActiveX CONTROL SOFTWARE... 6 IP MODULE Win32 CONTROL SOFTWARE... 6 IP MODULE VxWORKS SOFTWARE PREPARATION FOR USE UNPACKING AND INSPECTION CARD CAGE CONSIDERATIONS BOARD CONFIGURATION CONNECTORS IP Field I/O Connector (P2) IP Logic Interface Connector (P1) I/O Noise and Grounding Considerations PROGRAMMING INFORMATION IP IDENTIFICATION SPACE MEMORY MAP Board Control Register Interrupt Status/Clear Register Counter Trigger Register Counter Stop Register Counter Read Back Register Counter Constant A Register Counter Constant B Register Digital Input Register. 17 Digital Output Register.. 17 Interrupt Vector Register.. 17 COUNTER CONTROL REGISTER Quadrature Position Measurement Pulse Width Modulation Watchdog Timer Operation Event Counting Operation Frequency Measurement Operation Input Pulse Width Measurement. 30 Input Period Measurement One-Shot Pulse Mode

3 IP483 Industrial I/O Pack User s Manual Counter Timer Module PROGRAMMING EXAMPLES 36 Quadrature Position Measurement Example.. 36 Pulse Width Modulation Example Watchdog Timer Operation Example Event Counting Operation Example Frequency Measurement Operation Example. 41 Input Pulse Width Measurement Example Input Period Measurement Example One-Shot Pulse Mode Example TABLE OF CONTENTS 3 1. THEORY OF OPERATION LOGIC/POWER INTERFACE FIELD INPUT/OUTPUT SIGNALS Counter/Timers Digital I/O SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE WHERE TO GET HELP SPECIFICATIONS PHYSICAL ENVIRONMENTAL COUNTER/TIMERS DIGITAL I/O 52 INDUSTRIAL I/O PACK COMPLIANCE APPENDIX CABLE: MODEL TERMINATION PANEL: MODEL TERMINATION PANEL: MODEL TRANS-GP DRAWINGS IP483 BLOCK DIAGRAM IP MECHANICAL ASSEMBLY RS485 I/O CONNECTIONS CABLE (NON-SHIELDED) CABLE (SHIELDED) TERMINATION PANEL TRANSITION MODULE TRANS-GP Trademarks are the property of their respective owners.

4 4 1.0 GENERAL INFORMATION IP483 Industrial I/O Pack User s Manual Counter Timer Module The Industrial I/O Pack (IP) Series IP483 module provides support for seven independent 16-bit multifunction counter/timers. Each counter/timer can be configured for quadrature position measurement, pulse width modulated output, watchdog timer, event counter, frequency measurement, pulse width measurement, period measurement, or one shot pulse output. Table 1.1: The IP482/3/4 module is available in standard and extended temperature ranges MODEL Counters I/O Type IP bit TTL 0 C to +70 C IP bit 2 16-bit TTL RS485/RS422 OPERATING TEMPERATURE RANGE 0 C to +70 C IP bit RS485/RS422 0 C to +70 C IP482E bit TTL -40 C to +85 C IP483E 5 16-bit 2 16-bit TTL RS485/RS C to +85 C IP484E 5 16-bit RS485/RS C to +85 C KEY IP483 COUNTER/TIMER FEATURES 0TTL/Differential I/O Mixed TTL and RS485/RS422 I/O are available on the IP483. IP482 Counter/Timer I/O is available as TTL only. Only RS485/RS422 I/O is available on the IP484 model. 1. Quadrature Position Measurement Three input signals can be used to determine bi-directional motion. The sequence of logic high pulses for two input signals, A and B, indicate direction and a third signal (index) is used to initialize the counter. X1, X2, and X4 decoding is also implemented. X1 decoding executes one count per duty cycle of the A and B signals, while X2, and X4 execute two and four counts per duty cycle, respectively. 2. Pulse Width Modulation Each counter can be programmed for pulse width modulation. The duration of the logic high and low levels of the output signal can be independently controlled. An external gate signal can also be used to start/stop generation of the output signal. 3. Watchdog Timer Each counter can be configured as a countdown timer for implementation as a watchdog timer. A gate-off signal is available for use to stop the count down operation. Interrupt generation upon a countdown to zero condition is available. 4. Event Counter Each counter can be configured to count input pulses or events. A gate-off signal is provided to control count-up or count down with each event. Interrupt generation upon programmed count condition is available. 1Frequency Measurement Each counter can be configured to count how many active edges are received during a period defined by an external count enable signal. An interrupt can be generated upon measurement complete.

5 IP483 Industrial I/O Pack User s Manual Counter Timer Module 2Pulse-Width or Period Measurement Each counter can be configured KEY IP483 to measure pulse-width or waveform period. In addition, an interrupt can be COUNTER/TIMER generated upon measurement complete. FEATURES 3One-Shot and Repetitive One-Shot A one-shot pulse waveform may also be generated by each counter. The duration of the pulse and the delay until the pulse goes active is user programmable. A repetitive one-shot can be initiated with repetitive trigger pulses. 4Programmable Interface Polarity The polarities of the counter s external trigger, input, and output pins are programmable for active high or low operation. 5Internal or External Triggering A software or hardware trigger is selectable to initiate quadrature position measurement, pulse width modulation, watchdog countdown, event counting, frequency measurement, pulse-width measurement, period measurement, or one shot. 6Digital I/O The IP483 has 3 TTL outputs, 1 TTL input, 2 RS485/RS422 outputs, and 2 RS485/RS422 inputs available for use. 5 7High density - Single-size, industry-standard, IP module footprint. Up to four units may be mounted on a 6U VMEbus carrier board or five units may be mounted on a PCI carrier board. 8Local ID - Each IP module has its own 8-bit ID information which is accessed via data transfers in the "ID Read" space. INDUSTRIAL I/O PACK INTERFACE FEATURES 916-bit & 8-bit I/O - Channel register Read/Write is performed through D16 or D08 (EO) data transfer cycles in the IP module I/O space. 10High Speed - Access times for all data transfer cycles are described in terms of "wait" states. For the supplied IP module example, wait states are utilized for all read and write operations (see specifications for detailed information). 118 and 32 MHz Clock Support Module supports IP operating clocks of 8 and 32 MHz. This IP module will mate directly to any industry standard IP carrier board (including Acromag s AVME9630/60/70/75 VMEbus, APC8620/21 PCI bus, and ACPC8625/30/35 Compact PCI bus non-intelligent carrier boards). A wide range of other Acromag IP modules are also available to serve your signal conditioning and interface needs. SIGNAL INTERFACE PRODUCTS The cables and termination panels, described in the following paragraphs, represent some of the accessories available from Acromag. Each Acromag carrier has its own unique accessories. They are not all listed in this document. Consult your carrier board documentation for the correct interface product part numbers to ensure compatibility with your carrier board.

6 6 IP483 Industrial I/O Pack User s Manual Counter Timer Module SIGNAL INTERFACE PRODUCTS Cables: Model X (Shielded Cable), or Model X (Non- Shielded Cable): A Flat 50-pin cable with female connectors at both ends for connecting AVME9630/9660, or other compatible carrier boards, to Model termination panels. The unshielded cable is recommended for digital I/O, while the shielded cable is recommended for optimum performance with precision analog I/O applications. See the Appendix for further information on these products. Termination Panel: Model : A DIN-rail mountable panel that provides 50 screw terminals for universal field I/O termination. Connects to all Acromag carriers (or other compatible carrier boards) via flat 50-pin ribbon cable (Model X or X). Transition Module: Model TRANS-GP: This module repeats field I/O connections of IP modules A through D for rear exit from a VMEbus card cage. It is available for use in card cages which provide rear exit for I/O connections via transition modules (transition modules can only be used in card cages specifically designed for them). It is a double-height (6U), single-slot module with front panel hardware adhering to the VMEbus mechanical dimensions, except for shorter printed circuit board depth. It connects to Acromag Termination Panel from the rear of the card cage, and to AVME9630/9660 boards within the card cage, via flat 50-pin ribbon cable (Model X or X). IP MODULE ActiveX CONTROL SOFTWARE IP MODULE Win32 DRIVER SOFTWARE Acromag provides a software product (sold separately) consisting of IP module ActiveX (OLE) controls for Windows 98, ME, 2000, and XP compatible application programs (Model IPSW-ATX-PCI). This software provides individual controls that allow Acromag IP modules to be easily integrated into Windows application programs, such as Visual C++, Visual Basic, and others. The ActiveX controls provide a high-level interface to IP modules, eliminating the need to perform low-level reads/writes of registers, and the writing of interrupt handlers all the complicated details of programming are handled by the ActiveX controls. These functions are intended for use in conjunction with an Acromag personal computer carrier and consist of an ActiveX Carrier Control, and an ActiveX control for each Acromag IP module, as well as, a generic control for non-acromag IP modules. Acromag provides a software product (sold separately) to facilitate the development of Windows (98/Me/2000/XP ) applications accessing Industry Pack modules installed on Acromag PCI Carrier Cards and CompactPCI Carrier Cards. This software (Model IPSW-API-WIN) consists of low-level drivers and Windows 32 Dynamic Link Libraries (DLLS) that are compatible with a number of programming environments including Visual C++, Visual Basic, Borland C++ Builder and others. The DLL functions provide a high-level interface to the carriers and IP modules eliminating the need to perform low-level reads/writes of registers, and the writing of interrupt handlers.

7 IP483 Industrial I/O Pack User s Manual Counter Timer Module Acromag provides a software product (sold separately) consisting of IP module VxWorks libraries. This software (Model IPSW-API-VXW) is composed of VxWorks (real time operating system) libraries for all Acromag IP modules and carriers including the AVME9670, AVME9660/9630, APC8620/21, ACPC8630/35, and ACPC8625. The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag IP modules and carriers. 7 IP MODULE VxWORKS SOFTWARE 2.0 PREPARATION FOR USE Upon receipt of this product, inspect the shipping carton for evidence of mishandling during transit. If the shipping carton is badly damaged or water stained, request that the carrier's agent be present when the carton is opened. If the carrier's agent is absent when the carton is opened and the contents of the carton are damaged, keep the carton and packing material for the agent's inspection. UNPACKING AND INSPECTION For repairs to a product damaged in shipment, refer to the Acromag Service Policy to obtain return instructions. It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped. This board is physically protected with packing material and electrically protected with an anti-static bag during shipment. However, it is recommended that the board be visually inspected for evidence of mishandling prior to applying power. Refer to the specifications for loading and power requirements. Be sure that the system power supplies are able to accommodate the power requirements of the carrier/cpu board, plus the installed IP modules, within the voltage tolerances specified. The dense packing of the IP module to the carrier/cpu board restricts air flow within the card cage and is cause for concern. Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics. If the installation is in an industrial environment and the board is exposed to environmental air, careful consideration should be given to air-filtering. WARNING: This board utilizes static sensitive components and should only be handled at a staticsafe workstation. CARD CAGE CONSIDERATIONS IMPORTANT: Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature. Power should be removed from the board when installing IP modules, cables, termination panels, and field wiring. Refer to Mechanical Assembly Drawing and the following discussion for configuration and assembly instructions. Model IP483 Counter/Timer Boards have no jumpers or switches to configure all configuration is through software commands. BOARD CONFIGURATION

8 8 CONNECTORS IP483 Industrial I/O Pack User s Manual Counter Timer Module IP Field I/O Connector (P2) P2 provides the field I/O interface connector for mating IP modules to the carrier board. P2 is a 50-pin female receptacle header (AMP or equivalent) which mates to the male connector of the carrier board (AMP or equivalent). This provides excellent connection integrity and utilizes gold-plating in the mating area. Threaded metric M2 screws and spacers are supplied with the module to provide additional stability for harsh environments (see Mechanical Assembly Drawing ). The field and logic side connectors are keyed to avoid incorrect assembly. P2 pin assignments are unique to each IP model (see Table 2.1) and normally correspond to the pin numbers of the field-i/o interface connector on the carrier board (you should verify this for your carrier board). Table 2.1: IP483 Field I/O Pin Connections The IP483 has 5 TTL and 2 RS485/RS bit counters available. Additionally, it has 1 TTL and 2 RS485 Digital Inputs and 3 TTL and 2 RS485 Digital Outputs. The Digital I/O s are emphasized in bold italics. 1. Do Not Connect: Pin has direct connection to FPGA. Reserved for programming purposes. (TDI#) Pin has active pull-up. Pin Description TTL Pin Number Pin Pin Description Number RS485/RS422 In1_A 1 In6_A+ 25 In2_A 2 In6_A- 26 In3_A 3 In7_A+ 27 In4_A 4 In7_A- 28 In5_A 5 In6_B+ 29 In1_B 6 In6_B- 30 In2_B 7 In7_B+ 31 In3_B 8 In7_B- 32 In4_B 9 In6_C+ 33 In5_B 10 In6_C- 34 In1_C 11 In7_C+ 35 In2_C 12 In7_C- 36 In3_C 13 Out6+ 37 In4_C 14 Out6-38 In5_C 15 Out7+ 39 DIn1 16 Out7-40 Out1 17 DOut4+ 41 Out2 18 DOut4-42 Out3 19 DOut5+ 43 Out4 20 DOut5-44 Out5 21 DIn2+ 45 DOut1 22 DIn2-46 DOut2 23 DIn3+ 47 DOut3 24 DIn3-48 D.N.C GND 50

9 IP483 Industrial I/O Pack User s Manual Counter Timer Module P1 of the IP module provides the logic interface to the mating connector on the carrier board. This connector is a 50-pin female receptacle header (AMP or equivalent) which mates to the male connector of the carrier board (AMP or equivalent). This provides excellent connection integrity and utilizes gold-plating in the mating area. Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environments (see Drawing for assembly details). Field and logic side connectors are keyed to avoid incorrect assembly. The pin assignments of P1 are standard for all IP modules according to the Industrial I/O Pack Specification (see Table 2.2). CONNECTORS 9 IP Logic Interface Connector (P1) Pin Pin Pin Pin Description Number Description Number GND 1 GND 26 CLK 2 +5V 27 Reset# 3 R/W# 28 D00 4 IDSEL# 29 D01 5 DMAReq0# 30 D02 6 MEMSEL# 31 D03 7 DMAReq1# 32 D04 8 IntSel# 33 D05 9 DMAck0# 34 D06 10 IOSEL# 35 D07 11 RESERVED 3 36 D08 12 A1 37 D09 13 DMAEnd# 38 D10 14 A2 39 D11 15 ERROR 3 40 D12 16 A3 41 D13 17 INTReq0# 42 D14 18 A4 43 D15 19 INTReq1# 44 BS0# 20 A5 45 BS1# 21 STROBE# 46-12V 2 22 A V 2 23 ACK# 48 +5V 24 RESERVED 3 49 GND 25 GND 50 Table 2.2: Standard Logic Interface Connections (P1) 1. # is used to indicate an Active-low signal. 2. Logic Lines are NOT USED by this IP Model. 3. Logic Lines are reserved for programming purposes. (TMS#, TDO#, and TCLK) Each has an active pull-up.

10 10 CONNECTORS IP483 Industrial I/O Pack User s Manual Counter Timer Module I/O Noise and Grounding Considerations The IP483 is non-isolated between the logic and field I/O grounds since output common is electrically connected to the IP module ground. Consequently, the field I/O connections are not isolated from the carrier board and backplane. Two ounce copper ground plane foil has been employed in the design of this model to help minimize the effects of ground bounce, impedance drops, and switching transients. However, care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections. To minimize high levels of EMI the signal ground connection at the field I/O port (pin 50) should be used to provide a path for induced commonmode noise and currents. The ground path provides a low-impedance path to reduce emissions. EIA RS485/RS422 communication distances are generally limited to less than 4000 feet. To minimize transmission-line problems, all nodes connected to the cable must use minimum stub length connections. The optimal configuration for the RS485/RS422 bus is a daisy-chain connection from node 1 to node 2 to node 3 to node n. The bus must form a single continuous path, and the nodes in the middle of the bus must not be at the ends of long branches, spokes, or stubs. See Drawing for example connection and termination practices. Transmission line signal reflections can be minimized with proper termination. The EIA RS485/RS422 standard allows up to 32 driver/receivers to be connected to a single bus. Termination resistors should only be used at the two extreme ends of the bus and not at each of the nodes of the bus. Termination resistors are not provided on the IP483. They can be added to the field wiring as near to the IP module as possible.

11 IP483 Industrial I/O Pack User s Manual Counter Timer Module This Section provides the specific information necessary to program and operate the IP483 module PROGRAMMING INFORMATION Each IP module contains identification (ID) information that resides in the ID space per the IP module specification. This area of memory contains 32 bytes of information at most. Both fixed and variable information may be present within the ID space. Fixed information includes the "IPAH" identifier, model number, and manufacturer's identification codes. Variable information includes unique information required for the module. The IP483 ID space does not contain any variable (e.g. unique calibration) information. ID space bytes are addressed using only the odd addresses in a 64 byte block (on the Big Endian VMEbus). Even addresses are used on the Little Endian PC ISA or PCI buses. IP Identification Space (Read Only) The IP483 ID Space is shown in Table 3.1. Note that the base-address for the IP module ID space (see your carrier board instructions) must be added to the addresses shown to properly access the ID information. Execution of an ID Space Read operation requires 0 wait states. Hex Offset From ID Base Address ASCII Character Equivalent Numeric Value (Hex) 01 I P A H 48 Field Description All 32MHz IP's have 'IPAH' 09 A3 Acromag ID Code 0B 46 IP Model Code 1 0D 00 Not Used (Revision) 0F 00 Reserved Not Used (Driver ID Low Byte) Not Used (Driver ID High Byte) 15 0C Total Number of ID PROM Bytes CRC 19 to 3F yy Not Used Table 3.1: IP483 ID Space Identification (ID) 1. The IP model number is represented by a two-digit code within the ID space. The IP483 is represented by 46 Hex.

12 12 MEMORY MAP IP483 Industrial I/O Pack User s Manual Counter Timer Module This board is addressable in the Industrial Pack I/O space to monitor and control the status and configuration of up to seven 16-bit counter/timers. Counters one through five have TTL I/O, while Counters six and seven have Differential RS485/RS422 I/O. Additionally there are Digital I/O available for use. The IP483 has one TTL and three RS485/RS422 digital inputs, and three TTL and two RS485/RS422 digital outputs. All the Digital I/O s are controlled by the Digital Registers. The I/O space may be as large as 64, 16-bit words (128 bytes) using address lines A1..A6, but the IP483 uses only a portion of this space. The memory space address map for the IP483 is shown in Table 3.2. Note that the base address for the IP483 in memory space must be added to the addresses shown to properly access the IP483 registers. Accesses are generally performed on a 16-bit basis (D0..D15), but 8-bit (D0..D8) (EO) accesses are possible in most cases. Table 3.2: IP483 Memory Map EVEN Base Addr.+ EVEN Byte D15 D08 ODD Byte D07 D00 ODD Base Addr.+ Counters 1-5 have TTL I/O. Counters 6-7 have Differential (RS485/RS422) I/O. 00 Board Control Register Counters Interrupt Status/Clear Register 04 Counter Trigger Register Counter Stop Register Counter 1 Control Register 09 0A Counter 2 Control Register 0B 0C Counter 3 Control Register 0D 0E Counter 4 Control Register 0F 10 Counter 5 Control Register The IP483 will return 0 for all addresses that are "Not Used". 12 Counter 6 Control Register A Counter 7 Control Register Not Used 1 1B 1C Counter 1 Read Back Register 1D 1E Counter 2 Read Back Register 1F 20 Counter 3 Read Back Register Counter 4 Read Back Register Counter 5 Read Back Register Counter 6 Read Back Register 27

13 IP483 Industrial I/O Pack User s Manual Counter Timer Module 28 Counter 7 Read Back Register 29 2A 2E Not Used 1 2B 2F 30 Counter 1 Constant A Register Counter 2 Constant A Register Counter 3 Constant A Register Counter 4 Constant A Register Counter 5 Constant A Register 39 3A Counter 6 Constant A Register 3B 3C Counter 7 Constant A Register 3D 3E 42 Not Used 1 3F Counter 1 Constant B Register Counter 2 Constant B Register Counter 3 Constant B Register 49 4A Counter 4 Constant B Register 4B 4C Counter 5 Constant B Register 4D 4E Counter 6 Constant B Register 4F 50 Counter 7 Constant B Register Not Used Digital Input 58 Not Used Register 1 Digital Output 5A Not Used Register 1 Interrupt Vector 5C Not Used Register 5E Not Used 1 7E 59 5B 5D 5F 7F MEMORY MAP The IP483 will return 0 for all addresses that are "Not Used".

14 14 MEMORY MAP IP483 Industrial I/O Pack User s Manual Counter Timer Module The memory map for this module is given assuming byte accesses using the Big Endian byte ordering format. Big Endian is the convention used in the Motorola and PowerPC microprocessor family and is the VMEbus convention. In Big Endian, the lower-order byte is stored at odd-byte addresses. The Intel x86 family of microprocessors uses the opposite convention, or Little Endian byte ordering. Little Endian uses even-byte addresses to store the low-order byte. As such, use of the memory map for this module on a PC carrier board will require the use of the even address locations to access the lower 8-bit data. On a VMEbus carrier use of odd address locations are required to access the lower 8-bit data. CONTROL REGISTERS CAUTION: Bit 0 of the Board Control Register must be set correctly for proper module operation. Table 3.3: Board Control Register 1. All bits labeled Not Used and the Software Reset bit will return logic 0 when read. Board Control Register (Read/Write)- (Base + 00H) This read/write register is used to identify the IP48x model, set the carrier operational frequency, and for software reset. The function of each of the board control register bits is described in Table 3.3. This register can be read or written with either 8-bit or 16-bit data transfers. A power-up or system reset sets board control register bit 0 to logic 0. BIT FUNCTION 0 IP Carrier Clock Speed (Read/Write Bit) 0 = 8MHz Carrier 1 = 32MHz Carrier This bit must be set correctly for proper operation. 1 to 7 Not Used 1 Identify IP48x model. (Read Only Bits) 111 = IP482 10, 9, = IP = IP to 14 Not Used 1 15 Software Reset: Write logic 1 to this bit to reset the IP Interrupt Status/Clear Register (Read/Write) (Base +02H) This read/write register is used to determine the pending status of the Counter/Timer interrupts, and release pending interrupts The Counter/Timer interrupt status/clear bits 0 to 9 reflect the status of each of the Counter/Timers. A 1 bit indicates that an interrupt is pending for the corresponding counter/timer. The Counter/Timer and its corresponding interrupt Pending/Clear bits are as shown in Table 3.4. Read of this bit reflects the interrupt pending status of the counter timer logic. 0 = Interrupt Not Pending 1 = Interrupt Pending Write a logic 1 to this bit to release a counter timer pending interrupt. A counter timer pending interrupt can also be released by disabling interrupts via bit-15 of the Counter Control registers.

15 IP483 Industrial I/O Pack User s Manual Counter Timer Module 15 CONTROL REGISTERS BIT FUNCTION 0 Counter/Timer 1 Interrupt Pending/Clear 1 Counter/Timer 2 Interrupt Pending/Clear 2 Counter/Timer 3 Interrupt Pending/Clear 3 Counter/Timer 4 Interrupt Pending/Clear 4 Counter/Timer 5 Interrupt Pending/Clear 5 Counter/Timer 6 Interrupt Pending/Clear 6 Counter/Timer 7 Interrupt Pending/Clear 7-15 Not Used 1 A Counter/Timer that is not interrupt enabled will never set its interrupt status flag. A Counter/Timer interrupt can be cleared by writing a 1 to its bit position in the Interrupt Status/Clear Register (writing a 1 acts as a reset signal to clear the set state). The interrupt will be generated again, if the condition which caused the interrupt to occur remains. Writing 0 to a bit location has no effect. That is, a pending interrupt will remain pending. Table 3.4: IP483 Counter/Timer Interrupt Status/Clear 1. All bits labeled Not Used will return logic 0 when read. Writing to this register is possible via 16-bit or 8-bit data transfers. A power-up or system reset clears all interrupts, setting all bits in the Interrupt Status/Clear Register to logic 0. Counter Trigger Register (Write) - (Base + 04H) This register is used to implement software triggering for all counter/timers. Writing a 1 to the counter s corresponding trigger bit of this register will cause the counter function to be triggered. Table 3.5 identifies the trigger bit location corresponding to each of the counters. The contents of this register are not stored and merely act to trigger the corresponding counters. BIT FUNCTION 0 Counter 1 Trigger 1 1 Counter 2 Trigger 1 2 Counter 3 Trigger 1 3 Counter 4 Trigger 1 4 Counter 5 Trigger 1 5 Counter 6 Trigger 1 6 Counter 7 Trigger Not Used 1 Table 3.5: IP483 Counter Trigger Register 1. All bits will return logic 0 when read. Triggering may be used to initiate quadrature position measurement, pulse width modulation, watchdog timer (initiates countdown), event counting, frequency measurement, pulse-width measurement, period measurement, or one-shot. Writing to this register is possible via 16-bit or 8-bit data transfers.

16 16 IP483 Industrial I/O Pack User s Manual Counter Timer Module CONTROL REGISTERS Counter Stop Register (Write) - (Base + 06H) Table 3.6: IP483 Counter Stop Register 1. All bits will return logic 0 when read. This register is used to stop the counters of one or a group of Counter/Timers. Writing a 1 to the counter s corresponding stop bit of this register will cause the counter to be disabled. That is, bits 2, 1, and 0 of the counter control register are cleared to 000 thus disabling the counter. Table 3.6 identifies the stop bit location corresponding to each of the counters. The bits of this register are not stored and merely act to stop the corresponding counter when set logic high. BIT FUNCTION 0 Counter 1 Stop 1 1 Counter 2 Stop 1 2 Counter 3 Stop 1 3 Counter 4 Stop 1 4 Counter 5 Stop 1 5 Counter 6 Stop 1 6 Counter 7 Stop Not Used 1 Writing to this register is possible via 16-bit or 8-bit data transfers. Counter Read Back Register (Read Only) This read-only register is a dynamic function register that returns the current value held in the counter. It is updated with the value stored in the internal counter each time it is read. The internal counter is generally initialized with the value in the Counter Constant Register, and its value is incremented or decremented according to the application. The addresses corresponding to the Counter Read Back registers are given in Table 3.2. This register must be read using 16-bit accesses. Counter Constant A Register (Read/Write) Note that the Counter Constant Registers are cleared (set to 0) following a system or software reset. This read/write register is used to store the counter/timer constant A value (initial value) for the various counting modes. It is necessary to load the constant value into the counter in one clock cycle. Thus, access to this register is allowed on a 16-bit basis, only. The addresses corresponding to the Counter Constant A registers are given in Table 3.2. Counter Constant B Register (Read/Write) This read/write register is used to store the counter/timer constant B value. It is necessary to load the constant value into the counter in one clock cycle. Thus, a 16-bit write access is required. The addresses corresponding to the Counter Constant B registers are given in Table 3.2.

17 IP483 Industrial I/O Pack User s Manual Counter Timer Module Digital Input Register (Read) (Base + 58H) This 8-bit read only register contains the value of the digital TTL and RS485/RS422 inputs. A read value of one symbolizes a logic high while a value of zero represents a logic low. Table 3.7 identifies the position of the available input bits. 17 CONTROL REGISTERS BIT FUNCTION 0 DIn1 (TTL) 1 1 DIn2 (RS485/RS422) 1 2 DIn3 (RS485/RS422) Not Used 2 Reading this register is possible via 16-bit or 8-bit data transfers. Table 3.7: IP483 Digital Input Register 1. Digital Input bits will read logic 1 if left unconnected. 2. All bits labeled Not Used will return logic 0 when read. Digital Output Register (Read/Write) (Base + 5AH) This 8-bit read/write register contains the value of the digital TTL and RS485/RS422 outputs. To set a digital output high write a one to the proper bit position. To set the value logic low write a zero to the proper bit. On power-up output bits are initialized to logic "1. Table 3.8 identifies the position of the available output bits. BIT FUNCTION 0 DOut1 1 (TTL) 1 DOut2 1 (TTL) 2 DOut3 1 (TTL) 3 DOut4 1 (RS485/RS422) 4 DOut5 1 (RS485/RS422) 5-7 Not Used 2 Table 3.8: IP483 Digital Input Register 1. Bit is initialized to logic All bits labeled Not Used will return logic 0 when read. Writing to this register is possible via 16-bit or 8-bit data transfers. A software or hardware reset will set bits 0 to 4 to logic 1. Interrupt Vector Register (Read/Write) - (Base + 5CH) The Interrupt Vector Register maintains an 8-bit interrupt pointer for all channels configured as input channels. The Vector Register can be written with an 8-bit interrupt vector as seen in Table 3.9. This vector is provided to the carrier and system bus upon an active INTSEL cycle. Reading or writing to this register is possible via 16-bit or 8-bit data transfers. Interrupt Vector Register MSB LSB Table 3.9: IP483 Interrupt Vector Register Interrupts are released on access to the Interrupt Status register. Issue of a software or hardware reset will clear the contents of this register to 0.

18 18 COUNTER CONTROL REGISTER IP483 Industrial I/O Pack User s Manual Counter Timer Module Counter Control Register (Read/Write) This register is used to configure counter/timer functionality. It defines the counter mode, output polarity, input polarity, clock source, debounce enable, and interrupt enable. The IP483 has seven 16-bit Counter/Timers. Counter/Timers one through five have TTL I/O, while six and seven have Differential (RS485/RS422) I/O. The memory map addresses corresponding to the control registers are given in Table 3.2. The Counter Control Register is cleared (set to 0) following a reset, thus disabling the counter/timer. Reading or writing to this register is possible via 16-bit or 8-bit data transfers. Eight modes of operation are provided: quadrature position measurement, pulse width modulation, watchdog timer, event counting, frequency measurement, pulse width measurement, period measurement, and one-shot pulse mode. The following sections describe the features of each method of operation and how to best use them.

19 IP483 Industrial I/O Pack User s Manual Counter Timer Module Quadrature Position Measurement The counter/timers may be used to perform position measurements from quadrature motion encoders. Bits 2 to 0 of the Counter Control Register set to logic 001 configure the counter for quadrature measurement. A quadrature encoder can have up to three channels: A, B, and Index. When channel A leads channel B by 90 in a quadrature cycle, the counter increments. When channel B leads channel A by 90 in a quadrature cycle, the counter decrements. The number of increments or decrements per cycle depends on the type of encoding: X1, X2, or X4. 19 COUNTER CONTROL REGISTER Figure 3.1: Shows a quadrature cycle and the resulting increments and decrements for X1, X2, and X4 encoding. 4 An X1 encoding Increment occurs on the rising edge of channel A when channel A leads channel B. An X1 encoding decrement occurs on the falling edge of channel A when channel B leads channel A. For X2 encoding, two increments or decrements (on each edge of channel A) result from each cycle. The counter increments when A leads B and decrements when B leads A. For X4 encoding, four increments or decrements (on each edge of channel A and B) result from each cycle. The counter increments when A leads B and decrements when B leads A. Quadrature measurement must be triggered internally via the Counter Trigger Register at the base address + offset 04H. An initial software trigger starts quadrature position measurement operation. InA and InB input signals are used to input the channel A and channel B input signals, respectively. The counter will increment when channel A leads channel B and will decrement when channel B leads channel A. Three rates of increments and decrements are available X1, X2, and X4 which are programmed via counter timer control register bits 5 and 4. Channel B is enabled for input by setting bit-6 to a logic 1. InC can be used for the Index signal. Encoders that have an index channel can cause the counter to reload with the Counter Constant B value in a specified phase of the quadrature cycle. Reload can be programmed to occur in any one of the four phases in a quadrature cycle. You must ensure that the Index channel is high during at least a portion of the phase you specify for reload. The phase can be selected via the counter timer control register bits 9, 8, and 7 as seen in Table 3.10.

20 20 IP483 Industrial I/O Pack User s Manual Counter Timer Module COUNTER CONTROL REGISTER QUADRATURE POSITION MEASUREMENT The quadrature measurement value can be read from the Counter Read Back Register. An interrupt can be generated upon index reload, or when the counter value equals the constant value stored in the Counter Constant A Register. Interrupts must be enabled via the interrupt enable bit-15 of the Counter Control Register. The interrupt type must also be selected via bits 10 and 11 of the Counter Control Register. The interrupt will remain pending until released by setting the required bit of the Counter/Timer Interrupt Status/Clear register or setting bit-15 of the Counter Control register to 0. Note that interrupts in Quadrature Position Measurement are generated whenever the interrupt conditions exists. If a pending interrupt is cleared, but the interrupt conditions still exists, another interrupt will be generated. Table 3.10: Counter Control Register (Quadrature Position Measurement) 1. The default state of the output pin is high (output has pullup resistor installed). Bit 3 specifies the active output polarity when the output is driven. Bit(s) FUNCTION 2,1,0 Specifies the Counter Mode: 001 Quadrature Position Measurement 3 Output Polarity (Output Pin ACTIVE Level): 0 Active LOW (Default) 1 1 Active HIGH 5, 4 InA / Channel A 00 Disabled (Default) 01 X1 Encoding 10 X2 Encoding 11 X4 Encoding 6 InB / Channel B 0 Disabled (Default) 1 Enabled 9,8,7 InC / Index: Channel Interrupt/Reload occurs when Index signal=1 and the A & B input signals are as selected below. See Control bits 11 & 10 for additional interrupt/load control. 000 Disabled (Default) 101, 110, and 111 also Disable 001 A = 0, B = A = 1, B = A = 1, B = A = 0, B = 0 11,10 Interrupt Condition Select 00 No Interrupt Selected 01 Interrupt on counter equal Constant A Register. 10 Interrupt on Index and reload on Index 11 Interrupt on Index but do not reload counter on Index. 12 Not Used (bit reads back as 0) 13 Input Debounce Enable 0 Disabled (Default) No Debounce Applied to any Input. 1 Enabled Reject A, B, or Index Pulses less than or equal to 2.5 s. 14 Not Used (bit reads back as 0) 15 Interrupt Enable 0 Disable Interrupt Service (Default) 1 Enable Interrupt Service

21 IP483 Industrial I/O Pack User s Manual Counter Timer Module The Counter Control register bits 11 and 10 are used to control the operation of the counter output signal. With bits 11 and 10 set to 01, the output signal will be driven active while the counter equals the counter Constant A value. With bit 11 set to logic 1 the output signal will be driven active while the index condition remains true. Encoder output signals can be noisy. It is recommended that the InA, InB, and InC input signals be debounced by setting bit-13 of the Counter Control register to logic 1. Noise transitions less than 2.5 s will be removed with debounce enabled. 21 COUNTER CONTROL REGISTER QUADRATURE POSITION MEASUREMENT

22 22 IP483 Industrial I/O Pack User s Manual Counter Timer Module COUNTER CONTROL REGISTER Pulse Width Modulation Pulse width modulated waveforms may be generated at the counter timer output. The pulse width modulated waveform is generated continuously. Pulse Width Modulation generation is selected by setting Counter Control Register bits 2 to 0 to logic 010. Counter Constant A value controls the time until the pulse goes active. The duration of the pulse is set via the Counter Constant B register. Note that a high pulse will be generated if active high output is selected while a low pulse will be generated if active low output is selected. The counter goes through a countdown sequence for each Counter Constant value. When the 0 count is detected, the output toggles to the opposite state. Then the second Counter Constant value is loaded into the counter, and countdown resumes, decrementing by one for each rising edge of the clock selected via Control Register bits 12, 11, and 10. For example, a counter constant value of 3 will provide a pulse duration of 3 clock cycles of the selected clock. Note, when the maximum internal clock frequency is selected (8MHz or 32MHz), a delay of one extra clock cycle will be added to the counter constant value. InA can be used as a Gate-Off signal to stop and start the counter and thus the pulse-width modulated output. When InA is enabled via bits 5 and 4 of the control register for active low Gate-Off input, a logic low input will enable pulse-width modulation counting while a logic high will stop PWM counting. When InA is enabled for active high Gate-Off operation, a logic high will enable PWM counting while a logic low will stop PWM counting. InB can be used to input an external clock for use in PWM. Bits 7 and 6 must be set to either logic 01 or 10. Additionally, the clock source bits 12, 11, and 10 must be set to logic 101 to enable external clock input. PWM can alternatively be internally clocked using control register bits 12, 11, and 10. Available frequencies vary depending on the carrier operational frequency. InC can be used to externally trigger Pulse Width Modulation generation. Additionally PWM can be triggered internally via the Counter Trigger Register at the base address + offset 04H. An initial trigger, software or external, causes the pulse width modulated signal to be generated. After an initial trigger do not issue additional triggers. Triggers issued while running will cause the Constant A and B values to load at the wrong time. In addition, changing the Control register setting while running can also cause the Constant A and B values to load at the wrong time. If the Interrupt Enable bit of the Counter Control Register is set (bit 15), an interrupt is generated when the output pulse transitions from low to high and also for transitions from high to low. Thus, an interrupt is generated at each pulse transition.

23 IP483 Industrial I/O Pack User s Manual Counter Timer Module Bit(s) FUNCTION 2,1,0 Specifies the Counter Mode: 010 Pulse Width Modulation 3 Output Polarity (Output Pin ACTIVE Level): 0 Active LOW (Default) 1 1 Active HIGH 5, 4 InA Polarity / Gate-Off Polarity 00 Disabled (Default) Active LOW 01 In A=0 Counter is Enabled In A=1 Counter is Disabled Active HIGH 10 In A=0 Counter is Disabled In A=1 Counter is Enabled 11 Disabled 7, 6 InB Polarity / External Clock Input 00 Disabled (Default) 01 External Clock Enabled 10 External Clock Enabled 11 Disabled 9,8 InC Polarity / External Trigger 00 Disabled (Default) 01 Active LOW External Trigger 10 Active HIGH External Trigger 11 Disabled 12,11,10 Clock Source 2 Carrier Operational Freq. 8MHz 32MHz 000 (Default) 0.5MHz 2MHz 001 1MHz 4MHz 010 2MHz 8MHz 011 4MHz 16MHz 100 8MHz 32MHz 101 External Clock Up to 2MHz Up to 8MHz 13 Input Debounce Enable 0 Disabled (Default) No Debounce Applied to any 1 Input. Enabled Reject Gate-Off or Trigger Pulses (noise) less than or equal to 2.5 s. 14 Not Used (bit reads back as 0) 15 Interrupt Enable 0 Disable Interrupt Service (Default) 1 Enable Interrupt Service 23 COUNTER CONTROL REGISTER PULSE WIDTH MODULATION Table 3.11: Counter Control Register (Pulse Width Modulation) 1. The default state of the output pin is high (output has pullup installed). Bit 3 specifies the active output polarity when the output is driven. 2. The available clock sources are determined by the operational frequency of the carrier board. For an 8MHz carrier, bit 0 of the Board Control Register located at the base address plus an offset of 0H must be set low. For a 32MHz carrier, the bit must be set high.

24 24 IP483 Industrial I/O Pack User s Manual Counter Timer Module COUNTER CONTROL REGISTER Watchdog Timer Operation The watchdog operation counts down from a programmed (Counter Constant A) value until it reaches 0. While counting, the counter output will be in its active state (the output polarity is programmable). Upon time-out, the counter output will return to its inactive state, and an optional interrupt may be generated. Watchdog operation is selected by setting Counter Control Register bits 2 to 0 to logic 011. A timed-out watchdog timer will not re-cycle until it is reloaded and then followed with a new trigger. Failure to cause a reload would generate an automatic time-out upon re-triggering, since the counter register will contain the 0 it previously counted down to. InA input can be used to reload the counter with the Constant A register value. InA reload input is enabled via Control register bits 5 and 4. The counter can also be reloaded via a software write to the Counter Constant A register. Writing to the Counter Constant A register will load the value directly into the counter even if watchdog counting is actively counting down. InB can be used to input an external clock for watchdog timing. Bits 7 and 6 must be set to either logic 01 or 10. Additionally, the clock source bits 12, 11, and 10 must be set to logic 101 to enable external clock input. The timer can alternatively be internally clocked using control register bits 12, 11, and 10. Available frequencies vary depending on carrier opertional frequency. InC can be used to either continue/stop watchdog counting or as an external trigger input. When control register bits 9 and 8 are set to logic 11, InC functions as a Continue/Stop signal. When the Continue/Stop signal is high the counter continues counting (when low the counter stops counting). Alternately, when control register bits 9 and 8 are set to logic 01 or 10, the InC input functions as an external trigger input. The watchdog timer may also be internally triggered (via the Trigger Control Register at the base address + offset 04H). When triggered, the counter/timer contents are decremented by one for each clock cycle, until it reaches 0, upon which a watchdog timer time-out occurs. For example, a counter constant value of 30 will provide a time-out delay of 30 clock cycles of the selected clock. However, due to the asynchronous relationship between the trigger and the selected clock, one clock cycle of error can be expected. The counter can be read from the Counter Read Back register at any time during watchdog operation. Upon time-out, the counter output pin returns to its inactive state. The IP483 will also issue an interrupt upon detection of a count value equal to 0, if enabled via bit-15 of the Counter Control Register. This could be useful for alerting the host that a watchdog timer time-out has occurred and may need to be reinitialized. The interrupt will remain pending until the watchdog timer is reinitialized and the interrupt is released by setting the required bit of the Counter/Timer Interrupt Status/Clear register.

25 IP483 Industrial I/O Pack User s Manual Counter Timer Module COUNTER CONTROL REGISTER Bit(s) FUNCTION 2,1,0 Specifies the Counter Mode: 011 Watchdog Function 3 Output Polarity (Output Pin ACTIVE Level): 0 Active LOW (Default) 1 1 Active HIGH 5, 4 InA Polarity / Counter Reload 00 Disabled (Default) Active LOW 01 In A=0 Counter Reinitialized In A=1 Inactive State Active HIGH 10 In A=0 Inactive State In A=1 Counter Reinitialized 11 Disabled 7, 6 InB Polarity / External Clock Input 00 Disabled (Default) 01 External Clock Enabled 10 External Clock Enabled 11 Disabled 9,8 InC Polarity / External Trigger 00 Disabled (Default) 01 Active LOW Trigger 10 Active HIGH Trigger 11 Gate-Off (Continue when high/stop when low) 12,11,10 Clock Source 2 Carrier Operational Freq. 8MHz 32MHz 000 (Default) 0.5MHz 2MHz 001 1MHz 4MHz 010 2MHz 8MHz 011 4MHz 16MHz 100 8MHz 32MHz 101 External Clock Up to 2MHz Up to 8MHz 13 Input Debounce Enable 0 Disabled (Default) No Debounce Applied to any 1 Input. Enabled Reject Reinitialize or Trigger Pulses (noise) less than or equal to 2.5 s. 14 Not Used (bit reads back as 0) 15 Interrupt Enable 0 Disable Interrupt Service (Default) 1 Enable Interrupt Service WATCHDOG TIMER OPERATION 25 Table 3.12: Counter Control Register (Watchdog Timer) 1. The default state of the output pin is high (output has pullup installed). Bit 3 specifies the active output polarity when the output is driven. 2. The available clock sources are determined by the operational frequency of the carrier board. For an 8MHz carrier, bit 0 of the Board Control Register located at the base address plus an offset of 0H must be set low. For a 32MHz carrier, the bit must be set high.

26 26 COUNTER CONTROL REGISTER IP483 Industrial I/O Pack User s Manual Counter Timer Module Event Counting Operation Positive or negative polarity events can be counted. Event Counting is selected by setting Counter Control Register bits 2 to 0 to logic 100 and setting bits 12 to 10 to logic 000. Input pulses or events occurring at the input InB of the counter will increment the counter until it reaches the Counter Constant A value. Upon reaching the count limit, an output pulse of 1.75 s will be generated at the counter output pin, and an optional interrupt may be generated. Additionally, the internal event counter is cleared. The counter will continue counting, again from 0, until it reaches the Counter Constant A value. Once triggered, event counting will continue until disabled via Control register bits 2 to 0. InA can be used as a Gate-Off signal to stop and start event counting. When InA is enabled via bits 5 and 4 of the control register for active low Gate-Off input, a logic low input will enable event counting while a logic high will stop event counting. When InA is enabled for active high Gate-Off operation, a logic high will enable event counting while a logic low will stop event counting. InB is used as the event input signal. Active high or low input events can be selected via Control register bits 7 and 6. A minimum event pulse width (InB) of 125ns is required for correct pulse detection with input debounce disabled. Programmable clock selection is not available in event counter mode. InC can be used to either control up/down counting or as an external trigger input. When control register bits 9 and 8 are set to logic 11, InC functions as an Up/Down signal. When the Up/Down signal is high the counter is in the count down mode (when low the counter counts up). The counter will not count down below a count of zero. Alternately, when control register bits 9 and 8 are set to logic 01 or 10, the InC input functions as an external trigger input. Event counting may also be internally triggered (via the Trigger Control Register at the base address + offset 04H). The Counter Constant A Register holds the count-to value (constant). Reading the Counter Read Back Register will return the current count (variable). The Counter Constant A value must not be left as 0. The counter upon trigger starts counting from 0 and since the counter would match the count-to value the counter resets and starts counting from zero again. If the Interrupt Enable bit of the Counter Control Register is set (bit 15), an interrupt is generated when the number of input pulse events is equal to the Counter Constant A register value. The internal counter is then cleared and will continue counting events until the counter constant A value is again reached and a new interrupt generated. An interrupt will remain pending until released by setting the required bit of the Counters Interrupt Status/Clear register at the base address + offset 02H. A pending interrupt can also be cleared, by setting Control register bit-15 to logic low.