L6472. dspin fully integrated microstepping motor driver with motion engine and SPI. Features. Applications. Description

Transcription

1 dspin fully integrated microstepping motor driver with motion engine and SPI Features Operating voltage: 8-45 V 7.0 A output peak current (3.0 A r.m.s.) Low R DSon power MOSFETs Programmable speed profile Programmable Power MOSFET slew rate Up to 1/16 microstepping Predictive current control with adaptive decay Non-dissipative current sensing SPI interface Low quiescent and standby currents Programmable non-dissipative overcurrent protection on all Power MOSFETs Two levels of overtemperature protection Applications Bipolar stepper motor Description The L6472, realized in analog mixed signal technology, is an advanced fully integrated solution suitable for driving two-phase bipolar stepper motors with microstepping. It integrates a dual low R DS(on) DMOS full bridge with all of the power switches equipped with an accurate onchip current sensing circuitry suitable for nondissipative current control and overcurrent protection. Thanks to a new current control, a 1/16 microstepping is achieved through an adaptive decay mode which outperforms traditional implementations. The digital control core can generate user defined motion profiles with acceleration, deceleration, speed or target position, easily programmed through a dedicated register set. All application commands and data registers, including those used to set analog values (i.e. current control value, current protection trip point, dead time, etc.) are sent through a standard 5- Mbit/s SPI. A very rich set of protections (thermal, low bus voltage, overcurrent) makes the L6472 bullet proof, as required by the most demanding motor control applications. Table 1. POWERSO36 Device summary HTSSOP28 Order codes Package Packing L6472H HTSSOP28 Tube L6472HTR HTSSOP28 Tape and reel L6472PD POWERSO36 Tube L6472PDTR POWERSO36 Tape and reel January 2012 Doc ID Rev 1 1/

2 Contents L6472 Contents 1 Block diagram Electrical data Absolute maximum ratings Recommended operating conditions Thermal data Electrical characteristics Pin connection Pin list Typical applications Functional description Device power-up Logic I/O Charge pump Microstepping Automatic full-step mode Absolute position counter Programmable speed profiles Infinite acceleration/deceleration mode Motor control commands Constant speed commands Positioning commands Motion commands Stop commands Step-clock mode GoUntil and ReleaseSW commands Internal oscillator and oscillator driver Internal oscillator External clock source /69 Doc ID Rev 1

3 Contents 6.9 Overcurrent detection Undervoltage lockout (UVLO) Thermal warning and thermal shutdown Reset and standby External switch (SW pin) Programmable DMOS slew rate, dead time and blanking time Integrated analog-to-digital converter Internal voltage regulator BUSY\SYNC pin BUSY operation mode SYNC operation mode FLAG pin Phase current control Predictive current control Auto-adjusted decay mode Auto-adjusted fast decay during the falling steps Torque regulation (output current amplitude regulation) Serial interface Programming manual Register and flag description ABS_POS EL_POS MARK SPEED ACC DEC MAX_SPEED MIN_SPEED FS_SPD TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC T_FAST TON_MIN TOFF_MIN Doc ID Rev 1 3/69

4 Contents L ADC_OUT OCD_TH STEP_MODE ALARM_EN CONFIG STATUS Application commands Command management Nop SetParam (PARAM, VALUE) GetParam (PARAM) Run (DIR, SPD) StepClock (DIR) Move (DIR, N_STEP) GoTo (ABS_POS) GoTo_DIR (DIR, ABS_POS) GoUntil (ACT, DIR, SPD) ReleaseSW (ACT, DIR) GoHome GoMark ResetPos ResetDevice SoftStop HardStop SoftHiZ HardHiZ GetStatus Package mechanical data Revision history /69 Doc ID Rev 1

5 List of tables List of tables Table 1. Device summary Table 2. Absolute maximum ratings Table 3. Recommended operating conditions Table 4. Thermal data Table 5. Electrical characteristics Table 6. Pin description Table 7. Typical application values Table 8. CL values according to external oscillator frequency Table 9. Register map Table 10. EL_POS register Table 11. MIN_SPEED register Table 12. Torque regulation by TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN registers. 43 Table 13. Maximum fast decay times Table 14. Minimum ON time Table 15. Minimum OFF time Table 16. ADC_OUT value and torque regulation feature Table 17. Overcurrent detection threshold Table 18. STEP_MODE register Table 19. Step mode selection Table 20. SYNC output frequency Table 21. SYNC signal source Table 22. ALARM_EN register Table 23. CONFIG register Table 24. Oscillator management Table 25. External switch hard stop interrupt mode Table 26. Overcurrent event Table 27. Programmable power bridge output slew rate values Table 28. External torque regulation enable Table 29. Switching period Table 30. STATUS register Table 31. STATUS register DIR bit Table 32. STATUS register MOT_STATE bits Table 33. Application commands Table 34. NOP command structure Table 35. SetParam command structure Table 36. GetParam command structure Table 37. Run command structure Table 38. StepClock command structure Table 39. Move command structure Table 40. GoTo command structure Table 41. GoTo_DIR command structure Table 42. GoUntil command structure Table 43. ReleaseSW command structure Table 44. GoHome command structure Table 45. ResetPos command structure Table 46. ResetDevice command structure Table 47. SoftStop command structure Table 48. HardStop command structure Doc ID Rev 1 5/69

6 List of tables L6472 Table 49. SoftHiZ command structure Table 50. HardHiZ command structure Table 51. GetStatus command structure Table 52. HTSSOP28 mechanical data Table 53. POWERSO36 mechanical data Table 54. Document revision history /69 Doc ID Rev 1

7 List of figures List of figures Figure 1. Block diagram Figure 2. HTSSOP28 pin connection (top view) Figure 3. POWERSO36 pin connection (top view) Figure 4. Bipolar stepper motor control application using the L Figure 5. Charge pump circuitry Figure 6. Normal mode and microstepping (16 microsteps) Figure 7. Automatic full-step switching Figure 8. Speed profile in infinite acceleration/deceleration mode Figure 9. Constant speed commands examples Figure 10. Positioning command examples Figure 11. Motion command examples Figure 12. OSCIN and OSCOUT pin configurations Figure 13. External switch connection Figure 14. Internal 3 V linear regulator Figure 15. Predictive current control Figure 16. Non-predictive current control Figure 17. Adaptive decay - fast decay tuning Figure 18. Adaptive decay - switch from normal to slow+fast decay mode and vice versa Figure 19. Fast decay tuning during the falling steps Figure 20. SPI timings diagram Figure 21. Daisy chain configuration Figure 22. Command with 3-byte argument Figure 23. Command with 3-byte response Figure 24. Command response aborted Figure 25. HTSSOP28 mechanical data Figure 26. POWERSO36 drawings Doc ID Rev 1 7/69

8 Block diagram L Block diagram Figure 1. Block diagram 8/69 Doc ID Rev 1

9 Electrical data 2 Electrical data 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Test condition Value Unit V DD Logic interface supply voltage 5.5 V V S Motor supply voltage V SA = V SB = V S 48 V V GND, diff Differential voltage between AGND, PGND and DGND ±0.3 V V boot Bootstrap peak voltage 55 V V REG V ADCIN V OSC V out_diff Internal voltage regulator output pin and logic supply voltage Integrated ADC input voltage range (ADCIN pin) OSCIN and OSCOUT pin voltage range Differential voltage between V SA, OUT1 A, OUT2 A, PGND and V SB, OUT1 B, OUT2 B, PGND pins 3.6 V -0.3 to +3.6 V -0.3 to +3.6 V V SA = V SB = V S 48 V V LOGIC Logic inputs voltage range -0.3 to +5.5 V I out (1) R.m.s. output current 3 A I out_peak (1) Pulsed output current T PULSE < 1 ms 7 A T OP Operating junction temperature 150 C T s Storage temperature range -55 to 150 C P tot Total power dissipation (T A = 25 C) (2) 5 W 1. Maximum output current limit is related to metal connection and bonding characteristics. Actual limit must satisfy maximum thermal dissipation constraints. 2. HTSSOP28 mounted on EVAL6472H Rev 1.0. Doc ID Rev 1 9/69

10 Electrical data L Recommended operating conditions Table 3. Recommended operating conditions Symbol Parameter Test condition Value Unit V DD Logic interface supply voltage 3.3 V logic outputs 3.3 V 5 V logic outputs 5 V S Motor supply voltage V SA = V SB = V S 8 45 V V out_diff Differential voltage between V SA, OUT1 A, OUT2 A, PGND and V SB, OUT1 B, OUT2 B, PGND pins V REG,in Logic supply voltage V SA = V SB = V S 45 V V REG voltage imposed by external source V V ADC Integrated ADC input voltage (ADCIN pin) 0 V REG V T j Operating junction temperature C 2.3 Thermal data Table 4. Thermal data Symbol Parameter Package Typ Unit R thja Thermal resistance junction-ambient HTSSOP28 (1) POWERSO36 (2) 1. HTSSOP28 mounted on EVAL6472H Rev 1.0 board: four-layer FR4 PCB with a dissipating copper surface of about 40 cm 2 on each layer and 15 via holes below the IC. 2. POWERSO36 mounted on EVAL6472PD Rev 1.0 board: four-layer FR4 PCB with a dissipating copper surface of about 40 cm 2 on each layer and 22 via holes below the IC C/W 10/69 Doc ID Rev 1

11 Electrical characteristics 3 Electrical characteristics V SA = V SB = 36 V; V DD = 3.3 V; internal 3 V regulator; T J = 25 C, unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit General V SthOn V S UVLO turn-on threshold V V SthOff V S UVLO turn-off threshold V V V S UVLO threshold SthHyst V hysteresis I q Quiescent motor supply current Internal oscillator selected; V REG = 3.3V ext; CP floating ma T j(wrn) Thermal warning temperature 130 C T j(sd) Thermal shutdown temperature 160 C Charge pump V pump f pump,min f pump,max I boot Voltage swing for charge pump oscillator 10 V Minimum charge pump oscillator frequency (1) 660 khz Maximum charge pump oscillator frequency (1) 800 khz Average boot current f sw,a = f sw,b = 15.6kHz POW_SR = ma Output DMOS transistor R DS(on) I DSS High-side switch onresistance Low-side switch onresistance Leakage current t r Rise time (3) T j = 25 C, I out = 3A 0.37 T j = 125 C, (2) I out = 3A 0.51 T j = 25 C, I out = 3A 0.18 T j = 125 C, (2) I out = 3A 0.23 OUT = V S 3.1 OUT = GND -0.3 POW_SR = '00', I out = +1A 100 POW_SR = '00', I out = -1A 80 POW_SR = 11, I out = ±1A 100 POW_SR = 10, I out = ±1A 200 POW_SR = 01, I out = ±1A 300 Ω ma ns Doc ID Rev 1 11/69

12 Electrical characteristics L6472 Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit POW_SR = '00'; I out = +1A 90 t f Fall time (3) SR out_r SR out_f Output rising slew rate Output falling slew rate Dead time and blanking t DT Dead time (1) tblank Blanking time (1) Source-drain diodes POW_SR = '00'; I out = -1A 110 POW_SR = 11, I out = ±1A 110 POW_SR = 10, I out = ±1A 260 POW_SR = 01, I load = ±1A 375 POW_SR = '00', I out = +1A 285 POW_SR = '00', I out = -1A 360 POW_SR = 11, I out = ±1A 285 POW_SR = 10, I out = ±1A 150 POW_SR = 01, I out = ±1A 95 POW_SR = '00', I out = +1A 320 POW_SR = '00', I out = -1A 260 POW_SR = 11, I out = ±1A 260 POW_SR = 10, I out = ±1A 110 POW_SR = 01, I out = ±1A 75 POW_SR = '00' 250 POW_SR = 11, f OSC = 16MHz POW_SR = 10, f OSC = 16MHz POW_SR = 01, f OSC = 16MHz POW_SR = '00' 250 POW_SR = 11, f OSC = 16MHz POW_SR = 10, f OSC = 16MHz POW_SR = 01, f OSC = 16MHz ns V/µs V/µs ns ns V SD,HS V SD,LS t rrhs High-side diode forward ON voltage Low-side diode forward ON voltage High-side diode reverse recovery time I out = 1A V I out = 1A V I out = 1A 30 ns 12/69 Doc ID Rev 1

13 Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit t rrls Low-side diode reverse recovery time I out = 1A 100 ns Logic inputs and outputs V IL Low logic level input voltage 0.8 V V IH High logic level input voltage 2 V I IH I IL High logic level input current (4) V IN = 5V 1 µa Low logic level input current (5) V IN = 0V -1 µa V OL Low logic level output voltage (6) V DD = 3.3V, I OL = 4mA 0.3 V DD = 5V, I OL = 4mA 0.3 V V OH High logic level output voltage V DD = 3.3V, I OH = 4mA 2.4 V DD = 5V, I OH = 4mA 4.7 V R PU R PD CS pull-up and STBY pulldown resistors CS = GND; STBY/RST = 5V kω I logic Internal logic supply current 3.3V V REG externally supplied, internal oscillator ma I logic,stby Standby mode internal logic supply current 3.3V V REG externally supplied µa f STCK Step-clock input frequency 2 MHz Internal oscillator and external oscillator driver f osc,i Internal oscillator frequency T j = 25 C, V REG = 3.3V -3% 16 +3% MHz f osc,e Programmable external oscillator frequency 8 32 MHz V OSCOUT H OSCOUT clock source high level voltage Internal oscillator 3.3V V REG externally supplied; I OSCOUT = 4mA 2.4 V V OSCOUTL OSCOUT clock source low level voltage Internal oscillator 3.3V V REG externally supplied; I OSCOUT = 4mA 0.3 V t roscout t foscout SPI t extosc t intosc OSCOUT clock source rise and fall time Internal to external oscillator switching delay External to internal oscillator switching delay Internal oscillator 20 ns 3 ms 1.5 µs f CK,MAX Maximum SPI clock frequency (7) 5 MHz Doc ID Rev 1 13/69

14 Electrical characteristics L6472 Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit t rck t fck t hck t lck SPI clock rise and fall time (7) C L = 30pF 25 ns SPI clock high and low time (7) 75 ns t setcs Chip select setup time (7) 350 ns t holcs Chip select hold time (7) 10 ns t discs De-select time (7) 800 ns t setsdi Data input setup time (7) 25 ns t holsdi Data input hold time (7) 20 ns t ensdo Data output enable time (7) 38 ns t dissdo Data output disable time (7) 47 ns t vsdo Data output valid time (7) 57 ns t holsdo Data output hold time (7) 37 ns Switch input (SW) R PUSW SW input pull-up resistance SW = GND kω Current control I STEP,max I STEP,min Max. programmable reference current Min. programmable reference current 4 A 31 ma Overcurrent protection I OCD,MAX Maximum programmable overcurrent detection threshold OCD_TH = A I OCD,MIN Minimum programmable overcurrent detection threshold OCD_TH = A I OCD,RES Programmable overcurrent detection threshold resolution t OCD,Flag OCD to flag signal delay time di out /d t = 350A/µs ns t OCD,SD Standby I qstby OCD to shutdown delay time Quiescent motor supply current in standby conditions di out /d t = 350A/µs POW_SR = '10' A 600 µs V S = 8V VS = 36V t STBY,min Minimum standby time 10 µs t logicwu Logic power-on and wake-up time µs µa 14/69 Doc ID Rev 1

15 Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit t cpwu Charge pump power-on and wake-up time Power bridges disabled, C p = 10nF, C boot = 220nF 650 µs Internal voltage regulator V REG I REG V REG, drop I REG,STBY Voltage regulator output voltage Voltage regulator output current Voltage regulator output voltage drop Voltage regulator standby output current V 40 ma I REG = 40mA 50 mv 10 ma Integrated analog-to-digital converter N ADC V ADC,ref f S Analog-to-digital converter resolution Analog-to-digital converter reference voltage Analog-to-digital converter sampling frequency 5 bit V REG f OSC / 512 V khz 1. Accuracy depends on oscillator frequency accuracy. 2. Tested at 25 C in a restricted range and guaranteed by characterization. 3. Rise and fall time depends on motor supply voltage value. Refer to SR out values in order to evaluate the actual rise and fall time. 4. Not valid for the STBY/RST pin which has an internal pull-down resistor. 5. Not valid for the SW and CS pins which have an internal pull-up resistor. 6. FLAG, BUSY and SYNC open drain outputs included. 7. See Figure 20 SPI timings diagram for details. Doc ID Rev 1 15/69

16 Pin connection L Pin connection Figure 2. HTSSOP28 pin connection (top view) Figure 3. POWERSO36 pin connection (top view) 16/69 Doc ID Rev 1

17 Pin connection 4.1 Pin list Table 6. Pin description No. Name Type Function 17 VDD Power Logic output supply voltage (pull-up reference) 6 VREG Power 7 OSCIN Analog input 8 OSCOUT Analog output Internal 3 V voltage regulator output and 3.3 V external logic supply 10 CP Output Charge pump oscillator output 11 Vboot Supply voltage Oscillator pin 1. To connect an external oscillator or clock source. If this pin is unused, it should be left floating. Oscillator pin 2. To connect an external oscillator. When the internal oscillator is used this pin can supply 2/4/8/16 MHz. If this pin is unused, it should be left floating. Bootstrap voltage needed for driving the high-side power DMOS of both bridges (A and B) 5 ADCIN Analog input Internal analog-to-digital converter input VSA Power supply Full bridge A power supply pin. It must be connected to VSB VSB Power supply Full bridge B power supply pin. It must be connected to VSA PGND Ground Power ground pin 1 OUT1A Power output Full bridge A output 1 28 OUT2A Power output Full bridge A output 2 14 OUT1B Power output Full bridge B output 1 15 OUT2B Power output Full bridge B output 2 9 AGND Ground Analog ground. 4 SW Logical input 21 DGND Ground Digital ground 22 BUSY\SYNC Open drain output External switch input pin. If not used the pin should be connected to VDD. By default, this BUSY pin is forced low when the device is performing a command. Otherwise the pin can be configured to generate a synchronization signal. 18 SDO Logic output Data output pin for serial interface 20 SDI Logic input Data input pin for serial interface 19 CK Logic input Serial interface clock 23 CS Logic input Chip select input pin for serial interface 24 FLAG Open drain output Status flag pin. An internal open drain transistor can pull the pin to GND when a programmed alarm condition occurs (step loss, OCD, thermal pre-warning or shutdown, UVLO, wrong command, non-performable command) Doc ID Rev 1 17/69

18 Pin connection L6472 Table 6. Pin description (continued) No. Name Type Function 3 STBY\RST Logic input Standby and reset pin. LOW logic level resets the logic and puts the device into standby mode. If not used, it should be connected to VDD 25 STCK Logic input Step-clock input EPAD Exposed pad Ground Internally connected to PGND, AGND and DGND pins 18/69 Doc ID Rev 1

19 Typical applications 5 Typical applications Table 7. Name Typical application values Value C VS 220 nf C VSPOL 100 µf C REG 100 nf C REGPOL 47 µf C DD 100 nf C DDPOL 10 µf D1 Charge pump diodes C BOOT 220 nf C FLY 10 nf R PU 39 kω R SW 100 Ω C SW 10 nf Figure 4. Bipolar stepper motor control application using the L6472 Doc ID Rev 1 19/69

20 Functional description L Functional description 6.1 Device power-up At the end of power-up, the device state is the following: Registers are set to default, Internal logic is driven by the internal oscillator and a 2 MHz clock is provided by the OSCOUT pin, Bridges are disabled (High Z), UVLO bit in the STATUS register is forced low (fail condition), FLAG output is forced low. During power-up the device is under reset (all logic IO disabled and power bridges in highimpedance state) until the following conditions are satisfied: V S is greater than V SthOn V REG is greater than V REGth = 2.8 V (typ.) Internal oscillator is operative. Any motion command causes the device to exit from High Z state (HardStop and SoftStop included). 6.2 Logic I/O Pins CS, CK, SDI, STCK, SW and STBY\RST are TTL/CMOS 3.3 V-5 V compatible logic inputs. Pin SDO is a TTL/CMOS compatible logic output. The VDD pin voltage sets the logic output pin voltage range; when it is connected to VREG or a 3.3 V external supply voltage, the output is 3.3 V compatible. When VDD is connected to a 5 V supply voltage, SDO is 5 V compatible. VDD is not internally connected to V REG, an external connection is always needed. A 10 µf capacitor should be connected to the VDD pin in order to obtain a proper operation. Pins FLAG and BUSY\SYNC are open drain outputs. 6.3 Charge pump To ensure the correct driving of the high-side integrated MOSFETs, a voltage higher than the motor power supply voltage needs to be applied to the Vboot pin. The high-side gate driver supply voltage Vboot is obtained through an oscillator and a few external components realizing a charge pump (see Figure 5). 20/69 Doc ID Rev 1

21 Functional description Figure 5. Charge pump circuitry 6.4 Microstepping The driver is able to divide the single step into up to 16 microsteps. Step mode can be programmed by the STEP_SEL parameter in the STEP_MODE register (see Table 19). Step mode can only be changed when bridges are disabled. Every time step mode is changed, the electrical position (i.e. the point of microstepping sinewave that is generated) is reset to the first microstep, and the absolute position counter value (see Section 6.5) becomes meaningless. Figure 6. Normal mode and microstepping (16 microsteps) Doc ID Rev 1 21/69

22 Functional description L Automatic full-step mode When motor speed is greater than a programmable full-step speed threshold, the L6472 switches automatically to full-step mode (see Figure 7); the driving mode returns to microstepping when motor speed decreases below the full-step speed threshold. The fullstep speed threshold is set through the FS_SPD register (see Section 9.1.9). Figure 7. Automatic full-step switching 6.5 Absolute position counter An internal 22-bit register (ABS_POS) keeps track of the motor motion according to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). The position range is from to (µ) steps (see Section 9.1.1). 6.6 Programmable speed profiles The user can easily program a customized speed profile, independently defining acceleration, deceleration, maximum and minimum speed values through the ACC, DEC, MAX_SPEED and MIN_SPEED registers respectively (see Section 9.1.5, 9.1.6, and 9.1.8). When a command is sent to the device, the integrated logic generates the microstep frequency profile that performs a motor motion compliant to speed profile boundaries. All acceleration parameters are expressed in step/tick 2 and all speed parameters are expressed in step/tick; the unit of measurement does not depend on selected step mode. Acceleration and deceleration parameters range from 2-40 to (2 12-2) 2-40 step/tick2 (equivalent to to step/s2). Minimum speed parameter ranges from 0 to (2 12-1) 2-24 step/tick (equivalent to 0 to step/s). Maximum speed parameter ranges from 2-18 to (2 10-1) 2-18 step/tick (equivalent to to step/s). 22/69 Doc ID Rev 1

23 Functional description Infinite acceleration/deceleration mode When the ACC register value is set to max. (0xFFF), the system works in infinite acceleration mode : acceleration and deceleration phases are totally skipped, as shown in Figure 8. It is not possible to skip the acceleration or deceleration phase independently. Figure 8. Speed profile in infinite acceleration/deceleration mode 6.7 Motor control commands The L6472 can accept different types of commands: constant speed commands (Run, GoUntil, ReleaseSW) absolute positioning commands (GoTo, GoTo_DIR, GoHome, GoMark) motion commands (Move) stop commands (SoftStop, HardStop, SoftHiz, HardHiz). For detailed command descriptions refer to Section Constant speed commands A constant speed command produces a motion in order to reach and maintain a user defined target speed starting from the programmed minimum speed (set in the MIN_SPEED register) and with the programmed acceleration/deceleration value (set in the ACC and DEC registers). A new constant speed command can be requested anytime. Doc ID Rev 1 23/69

24 Functional description L6472 Figure 9. Constant speed commands examples Positioning commands An absolute positioning command produces a motion in order to reach a user-defined position that is sent to the device together with the command. The position can be reached by performing the minimum path (minimum physical distance) or forcing a direction (see Figure 10). The performed motor motion is compliant to programmed speed profile boundaries (acceleration, deceleration, minimum and maximum speed). Note that with some speed profiles or positioning commands, the deceleration phase can start before the maximum speed is reached. Figure 10. Positioning command examples 24/69 Doc ID Rev 1

25 Functional description Motion commands Motion commands produce a motion in order to perform a user-defined number of microsteps in a user-defined direction that are sent to the device together with the command (see Figure 11). The performed motor motion is compliant to programmed speed profile boundaries (acceleration, deceleration, minimum and maximum speed). Note that with some speed profiles or motion commands, the deceleration phase can start before the maximum speed is reached. Figure 11. Motion command examples Stop commands A stop command forces the motor to stop. Stop commands can be sent anytime. The SoftStop command causes the motor to decelerate with a programmed deceleration value until the MIN_SPEED value is reached and then stops the motor maintaining the rotor position (a holding torque is applied). The HardStop command stops the motor instantly, ignoring deceleration constraints and maintaining the rotor position (a holding torque is applied). The SoftHiZ command causes the motor to decelerate with a programmed deceleration value until the MIN_SPEED value is reached and then forces the bridges into highimpedance state (no holding torque is present). The HardHiZ command instantly forces the bridges into high-impedance state (no holding torque is present) Step-clock mode In step-clock mode the motor motion is defined by the step-clock signal applied to the STCK pin. At each step-clock rising edge, the motor is moved by one microstep in the programmed direction and the absolute position is consequently updated. When the system is in step-clock mode the SCK_MOD flag in the STATUS register is raised, the SPEED register is set to zero and the motor status is considered stopped whatever the STCK signal frequency (the MOT_STATUS parameter in the STATUS register equal to g00h). Doc ID Rev 1 25/69

26 Functional description L GoUntil and ReleaseSW commands In most applications the power-up position of the stepper motor is undefined, so an initialization algorithm driving the motor to a known position is necessary. The GoUntil and ReleaseSW commands can be used in combination with external switch input (see Section 6.13) to easily initialize the motor position. The GoUntil command makes the motor run at the target constant speed until the SW input is forced low (falling edge). When this event occurs, one of the following actions can be performed: ABS_POS register is set to zero (home position) and the motor decelerates to zero speed (as a SoftStop command) ABS_POS register value is stored in the MARK register and the motor decelerates to zero speed (as a SoftStop command). If the SW_MODE bit of the CONFIG register is set to e0f, the motor does not decelerate but it immediately stops (as a HardStop command). The ReleaseSW command makes the motor run at the programmed minimum speed until the SW input is forced high (rising edge). When this event occurs, one of the following actions can be performed: ABS_POS register is set to zero (home position) and the motor immediately stops (as a HardStop command) ABS_POS register value is stored in the MARK register and the motor immediately stops (as a HardStop command). If the programmed minimum speed is less than 5 step/s, the motor is driven at 5 step/s. 26/69 Doc ID Rev 1

27 Functional description 6.8 Internal oscillator and oscillator driver The control logic clock can be supplied by the internal 16-MHz oscillator, an external oscillator (crystal or ceramic resonator) or a direct clock signal. These working modes can be selected by the EXT_CLK and OSC_SEL parameters in the CONFIG register (see Table 24). At power-up the device starts using the internal oscillator and provides a 2-MHz clock signal on the OSCOUT pin. Attention: In any case, before changing clock source configuration, a hardware reset is mandatory. Switching to different clock configurations during operation could cause unexpected behavior Internal oscillator In this mode the internal oscillator is activated and OSCIN is unused. If the OSCOUT clock source is enabled, the OSCOUT pin provides a 2, 4, 8 or 16-MHz clock signal (according to the OSC_SEL value); otherwise it is unused (see Figure 12) External clock source Two types of external clock source can be selected: crystal/ceramic resonator or direct clock source. Four programmable clock frequencies are available for each external clock source: 8, 16, 24 and 32 MHz. When an external crystal/resonator is selected, the OSCIN and OSCOUT pins are used to drive the crystal/resonator (see Figure 12). The crystal/resonator and load capacitors (CL) must be placed as close as possible to the pins. Refer to Table 8 for the choice of the load capacitor value according to the external oscillator frequency. Table 8. CL values according to external oscillator frequency Crystal/resonator freq. (1) 1. First harmonic resonance frequency. CL (2) 8 MHz 25 pf (ESR max = 80 Ω) 16 MHz 18 pf (ESR max = 50 Ω) 24 MHz 15 pf (ESR max = 40 Ω) 32 MHz 10 pf (ESR max = 40 Ω) 2. Lower ESR value allows the driving of greater load capacitors. If a direct clock source is used, it must be connected to the OSCIN pin, and the OSCOUT pin supplies the inverted OSCIN signal (see Figure 12). Doc ID Rev 1 27/69

28 Functional description L6472 Figure 12. OSCIN and OSCOUT pin configurations Note: When OSCIN is UNUSED, it should be left floating. When OSCOUT is UNUSED it should be left floating. 6.9 Overcurrent detection When the current in any of the Power MOSFETs exceeds a programmed overcurrent threshold, the STATUS register OCD flag is forced low until the overcurrent event expires and a GetStatus command is sent to the IC (see Section and ). The overcurrent event expires when all the Power MOSFET currents fall below the programmed overcurrent threshold. The overcurrent threshold can be programmed through the OCD_TH register in one of 16 available values ranging from 375 ma to 6 A with steps of 375 ma (see Table 17). It is possible to set if an overcurrent event causes or not the MOSFET turn-off (bridges in high-impedance status) acting on the OC_SD bit in the CONFIG register (see Section ). The OCD flag in the STATUS register is raised anyway (see Table 25). When the IC outputs are turned-off by an OCD event, they cannot be turned on until the OCD flag is released by a GetStatus command. Attention: The overcurrent shutdown is a critical protection feature. It is not recommended to disable it. 28/69 Doc ID Rev 1

29 Functional description 6.10 Undervoltage lockout (UVLO) The L6472 provides motor supply UVLO protection. When the motor supply voltage falls below the VSthOff threshold voltage, the STATUS register UVLO flag is forced low. When a GetStatus command is sent to the IC, and the undervoltage condition expires, the UVLO flag is released (see Section and ). The undervoltage condition expires when the motor supply voltage goes over the VSthOn threshold voltage. When the device is in the undervoltage condition, no motion command can be performed. The UVLO flag is forced low by logic reset (power-up included) even if no UVLO condition is present Thermal warning and thermal shutdown An internal sensor allows the L6472 to detect when the device internal temperature exceeds a thermal warning or an overtemperature threshold. When the thermal warning threshold (T j(wrn) ) is reached, the TH_WRN bit in the STATUS register is forced low (see Section ) until the temperature decreases below T j(wrn) and a GetStatus command is sent to the IC (see Section and ). When the thermal shutdown threshold (T j(off) ) is reached, the device goes into the thermal shutdown condition: the TH_SD bit in the STATUS register is forced low, the power bridges are disabled bridges in high-impedance state and the HiZ bit in the STATUS register is raised (see Section ). The thermal shutdown condition only expires when the temperature goes below the thermal warning threshold (T j(wrn) ). On exiting the thermal shutdown condition, the bridges are still disabled (HiZ flag high); whichever motion command makes the device exit from High Z state (HardStop and SoftStop included) Reset and standby The device can be reset and put into standby mode through a dedicated pin. When the STBY\RST pin is driven low, the bridges are left open (High Z state), the internal charge pump is stopped, the SPI interface and control logic are disabled, and the internal 3 V voltage regulator maximum output current is reduced to IREG,STBY; as a result, the L6472 heavily reduces the power consumption. At the same time the register values are reset to default and all protection functions are disabled. STBY\RST input must be forced low at least for tstby,min, in order to ensure the complete switch to standby mode. On exiting standby mode, as well as for IC power-up, a delay of up to tlogicwu must be given before applying a new command to allow proper oscillator and logic startup and a delay of up to tcpwu must be given to allow the charge pump startup. On exiting standby mode the bridges are disabled (HiZ flag high) and whichever motion command causes the device to exit High Z state (HardStop and SoftStop included). Attention: It is not recommended to reset the device when outputs are active. The device should be switched to high-impedance state before being reset. Doc ID Rev 1 29/69

30 Functional description L External switch (SW pin) The SW input is internally pulled-up to VDD and detects if the pin is open or connected to ground (see Figure ). The SW_F bit of the STATUS register indicates if the switch is open ( 0 ) or closed ( 1 ) (see Section ); the bit value is refreshed at every system clock cycle (125 ns). The SW_EVN flag of the STATUS register is raised when a switch turn-on event (SW input falling edge) is detected (see Section ). A GetStatus command releases the SW_EVN flag (see Section ). By default a switch turn-on event causes a HardStop interrupt (SW_MODE bit of the CONFIG register set to 0 ). Otherwise (SW_MODE bit of the CONFIG register set to 1 ), switch input events do not cause interrupts and the switch status information is at the user s disposal (see Table 25). The switch input can be used by the GoUntil and ReleaseSW commands as described in Section and If the SW input is not used, it should be connected to VDD. Figure 13. External switch connection 6.14 Programmable DMOS slew rate, dead time and blanking time Using the POW_SR parameter in the CONFIG register, it is possible to set the commutation speed of the power bridge output (see Table 27) Integrated analog-to-digital converter The L6472 integrates an NADC bit ramp-compare analog-to-digital converter with a reference voltage equal to VREG. The analog-to-digital converter input is available through the ADCIN pin and the conversion result is available in the ADC_OUT register (see Section ). The sampling frequency is equal to the clock frequency divided by 512. The ADC_OUT value can be used for the torque regulation or can remain at the user s disposal. 30/69 Doc ID Rev 1

31 Functional description 6.16 Internal voltage regulator The L6472 integrates a voltage regulator which generates a 3 V voltage starting from motor power supply (VSA and VSB). In order to make the voltage regulator stable, at least 22 µf should be connected between the VREG pin and ground (the suggested value is 47 µf). The internal voltage regulator can be used to supply the VDD pin in order to make the device digital output range 3.3 V compatible (Figure 14). A digital output range 5 V compatible can be obtained connecting the VDD pin to an external 5 V voltage source. In both cases, a 10 µf capacitance should be connected to the VDD pin in order to obtain a correct operation. The internal voltage regulator is able to supply a current up to IREG,MAX, internal logic consumption included (I logic ). When the device is in standby mode the maximum current that can be supplied is I REG, STBY, internal consumption included (I logic, STBY ). If an external 3.3 V regulated voltage is available, it can be applied to the VREG pin in order to supply all the internal logic and avoid power dissipation of the internal 3 V voltage regulator (Figure 14). The external voltage regulator should never sink current from the VREG pin. Figure 14. Internal 3 V linear regulator 6.17 BUSY\SYNC pin This pin is an open drain output which can be used as the busy flag or synchronization signal according to the SYNC_EN bit value (STEP_MODE register) BUSY operation mode The pin works as busy signal when the SYNC_EN bit is set low (default condition). In this mode the output is forced low while a constant speed, absolute positioning or motion command is under execution. The BUSY pin is released when the command has been executed (target speed or target position reached). The STATUS register includes a BUSY flag that is the BUSY pin mirror (see Section ). In the case of daisy chain configuration, BUSY pins of different ICs can be hard-wired to save host controller GPIOs. Doc ID Rev 1 31/69

32 Functional description L SYNC operation mode The pin works as a synchronization signal when the SYNC_EN bit is set high. In this mode a step-clock signal is provided on the output according to a SYNC_SEL and STEP_SEL parameter combination (see Section ) FLAG pin By default an internal open drain transistor pulls the FLAG pin to ground when at least one of the following conditions occur: Power-up or standby/reset exit Overcurrent detection Thermal warning Thermal shutdown UVLO Switch turn-on event Wrong command Non-performable command. It is possible to mask one or more alarm conditions by programming the ALARM_EN register (see Table 22). If the corresponding bit of the ALARM_EN register is low, the alarm condition is masked and it does not cause a FLAG pin transition; all other actions imposed by alarm conditions are performed anyway. In the case of daisy chain configuration, the FLAG pins of different ICs can be OR-wired to save host controller GPIOs. 32/69 Doc ID Rev 1

33 Phase current control 7 Phase current control The L6472 performs a new current control technique, named predictive current control, allowing the device to obtain the target average phase current. This method is described in detail in Section 7.1. Furthermore, the L6472 automatically selects the better decay mode in order to follow the current profile. Current control algorithm parameters can be programmed by the T_FAST, TON_MIN, TOFF_MIN and CONFIG registers (see Section , , and for details). Different current amplitude can be set for acceleration, deceleration and constant speed phases and when the motor is stopped through the TVAL_ACC, TVAL_DEC, TVAL_RUN and TVAL_HOLD registers (see Section 7.4). The output current amplitude can also be regulated by the ADCIN voltage value (see Section 6.15). Each bridge is driven by an independent control system that shares the control parameters only with other bridges. 7.1 Predictive current control Unlike a classical peak current control system, that causes the phase current decay when the target value is reached, this new method keeps the power bridge on for an extra time after reaching the current threshold. At each cycle the system measures the time required to reach the target current (t SENSE ). After that the power stage is kept in a predictive ON state (t PRED ) for a time equal to the mean value of t SENSE in the last two control cycles (actual one and previous one), as shown in Figure 15. Figure 15. Predictive current control At the end of the predictive ON state the power stage is set in the OFF state for a fixed time, as in a constant t OFF current control. During the OFF state both slow and fast decay can be performed; the better decay combination is automatically selected by the L6472, as described in Section 7.2. Doc ID Rev 1 33/69

34 Phase current control L6472 As shown in Figure 15, the system is able to center the triangular wave on the desired reference value improving dramatically the accuracy of the current control system: in fact the average value of a triangular wave is exactly equal to the middle point of each of its segments and at steady-state the predictive current control tends to equalize the duration of the t SENSE and the t PRED time. Furthermore, the t OFF value is recalculated each time a new current value is requested (microstep change) in order to keep the PWM frequency as near as possible to the programmed one (TSW parameter in the CONFIG register). The device can be forced to work using a classic peak current control setting the PRED_EN bit in the CONFIG register low (default condition). In this case, after the sense phase (t SENSE ) the power stage is set in the OFF state, as shown in Figure 16. Figure 16. Non-predictive current control 34/69 Doc ID Rev 1