KAF-4301E. 2084(H) x 2084(V) Pixel. Enhanced Response Full-Frame CCD Image Sensor. Performance Specification. Eastman Kodak Company

Transcription

1 KAF-4301E 2084(H) x 2084(V) Pixel Enhanced Response Full-Frame CCD Image Sensor Performance Specification Eastman Kodak Company Image Sensor Solutions Rochester, New York Revision 2 September 23, 2002

2 TABLE OF CONTENTS 1.0 Device Description Features Functional Description Architecture Image Acquisition Charge Transport Output Structure Pin Description Performance Electro-Optical CCD Parameters CCD Parameters Common To both Outputs CCD Parameters Specific to High Gain Output Amplifier CCD Parameters Specific to Low Gain (high dynamic range) Output Amplifier Cosmetic Specification Operation Absolute Minimum/Maximum Ratings DC Operating Conditions AC Clock Level Conditions AC Timing Chart Storage and Handling Storage Conditions ESD Quality Assurance and Reliability Mechanical Drawings and Specifications Imager Flatness Ordering Information Appendix 1 Revision Changes FIGURES Figure 1 - Functional Block Diagram... 3 Figure 2 - Output Structure... 4 Figure 3 - Pinout Diagram... 7 Figure 4 - Spectral Response... 8 Figure 5 - Dark Current... 9 Figure 6 - Typical Output Structure Load Diagram Figure 7 - Timing Diagrams Figure 8 - Package Mechanical Drawing Figures 9, 10, 11 - Surface Profiles Image Sensor Surface Revision No. 2

3 1.0 Device Description 1.1 Features Front Illuminated Full-Frame Architecture with Blue Plus Transparent Gate True Two Phase Technology 24µm(H) x 24µm(V) Pixel Size 2084(H) x 2084(V) Photosensitive Pixels mm x mm Photo active Area 100% Fill FactorTwo Clock Selectable Outputs High Gain Output (11 µv/e - ) High Dynamic Range Output (2.0 µv/e - ) Low Dark Current (<15 pa/cm T=25 o C). 1.2 Functional Description The KAF-4301E is a high performance silicon chargecoupled device (CCD) designed for a wide range of image sensing applications in the 0.4µm to 1.1µm wavelength band. Common applications include medical, scientific, military, machine and industrial vision. The sensor is built with a true two-phase CCD technology employing a transparent gate. This technology simplifies the support circuits that drive the sensor and reduces the dark current without compromising charge capacity. The transparent gate results in spectral response increased ten times at 400 nm, compared to a front side illuminated standard poly silicon gate technology. The sensitivity is increased 50% over the rest of the visible wavelengths. The clock selectable on-chip output amplifiers have been specially designed to meet two different needs. The first is a high sensitivity 2-stage output with 11µV/e- charge to voltage conversion ratio. The second is a single stage output with 2µV/e- charge to voltage conversion 4 Dark Lines φh22 Sub Vdd2 Vout2 Vss Vdd1 Vout1 φr Vrd Vog φh21 KAF-4301E Usable Active Image 2084 (H) x 2084(V) 24 x 24 µm 2084 Active Pixels/Line 4 Dark 8 Dark 4 Inactive 2 Inactive φv1 φv2 Guard 4 Dark φh1 φh2 Figure 1 - Functional Block Diagram Shaded areas represent 8 non-imaging pixels at the beginning and 10 non-imaging pixels at the end of each line. There are also 4 non-imaging lines at the top and bottom of each frame. 3 Revision No. 2

4 Sub Vdd2 φh22 Vout2 FD1 FD2 φh2 Vlg Vss Vdd1 Vout1 φr φh1 Vrd Vog φh21 Figure 2 - Output Structure 1.3 Architecture Refer to the block diagram in Figure 1 - Functional Block Diagram The KAF-4301E consists of 2092 vertical (parallel) CCD shift registers, one horizontal (serial) CCD shift register and a selectable high or low gain output amplifier. Both registers incorporate two level polysilicon and true two-phase buried channel technology. The vertical registers contain 24 µm x 24 µm photocapacitor sensing elements (pixels) that also serves as the transport mechanism. The pixels are arranged in a 2084(H) x 2084(V) array; an additional 8 columns (4 at the left and 4 at the right) and 8 rows (4 each at top and bottom) of non-imaging pixels are added as dark reference. This device must be synchronized with strobe illumination or shuttered during readout because there is no storage array. 1.4 Image Acquisition An image is acquired when incident light, in the form of photons, falls on the array of pixels in the vertical CCD register and creates electron-hole pairs (or simply electrons) within the silicon substrate. This charge is collected locally by the formation of potential wells created at each pixel site by induced voltages on the vertical register clock lines (φv1, φv2). These same clock lines are used to implement the transport mechanism as well. The amount of charge collected at each pixel is linearly dependent on light level and exposure time and non-linearly dependent on wavelength until the potential well capacity is exceeded. At this point charge will 'bloom' into vertically adjacent pixels. 1.5 Charge Transport Integrated charge is transported to the output in a two-step process. Rows of charge are first shifted line by line into the horizontal CCD. 'Lines' of charge are then shifted to the output pixel by pixel. Referring to the timing diagram, integration of charge is performed with φv1 and φv2 held low. Transfer to horizontal CCD begins when φv1 is brought high causing charge from the φv1 and φv2 gates to combine under the φv1 gate. φv1 and φv2 now reverse their polarity causing the charge packets to 'spill' forward under the φv2 gate of the next pixel. The rising edge of φv2 also transfers the first line of charge into the horizontal CCD. A second phase transition places the charge packets under the φv1 electrode of the next pixel. The sequence completes when φv1 is brought low. Clocking of the vertical register in this way is known as accumulation mode clocking. Next, the horizontal CCD reads out the first line of charge using traditional complementary 4 Revision No. 2

5 clocking (using φh1 and φh2 pins) as shown. The falling edge of φh2 forces a charge packet over the output gate (OG) onto one of the output nodes (floating diffusion) that controls the output amplifier. The cycle repeats until all lines are read. 1.6 Output Structure The final gate of the horizontal register is split into two sections, φh21 and φh22 as shown in Figure 2 - Output Structure The split gate structure allows the user to select either of the two output amplifiers. To use the high dynamic range singlestage output (Vout1), tie φh22 to a negative voltage to block charge transfer, and tie φh21 to φh2 to transfer charge. To use the high sensitivity two-stage output (Vout2), tie φh21 to a negative voltage and φh22 to φh2. The charge packets are then dumped onto the appropriate floating diffusion output node whose potential varies linearly with the quantity of charge in each packet. The amount of potential change is determined by the simple expression Vfd= Q/Cfd. The translation from electrons to voltages is called the output sensitivity or charge-to-voltage conversion. After the output has been sensed offchip, the reset clock (φr) removes the charge from the floating diffusion via the reset drain (VRD). This, in turn, returns the floating diffusion potential to the reference level determined by the reset drain voltage. 5 Revision No. 2

6 1.7 Pin Description Pin Number Symbol Description Notes 1, 2, 27, 39, 40 φv2 Vertical (Parallel) CCD Clock - Phase 2 1 3, 4, 28, 37, 38 φv1 Vertical (Parallel) CCD Clock - Phase 1 2 5, 10, 20, 21, 29, 36 VSUB Substrate 3 9, 22, 30 VGUARD Guard Ring 4 11 VDD2 High Sensitivity Two-Stage Amplifier Supply 12 VOUT2 Video Output from High Sensitivity Two-Stage Amplifier 13 VLG First Stage Load Transistor Gate for Two-Stage Amplifier 14 VSS High Sensitivity Two-Stage Amplifier Return 15 VRD Reset Drain 16 φr Reset Clock 17 VDD1 High Dynamic Range Single-Stage Amplifier Supply 18 VOUT1 Video Output from High Dynamic Range Single-Stage Amplifier 19 VOG Output Gate 23 φh21 Last Horizontal (Serial) CCD Phase - Split Gate 24 φh22 Last Horizontal (Serial) CCD Phase - Split Gate 25 φh2 Horizontal (Serial) CCD Clock - Phase 1 26 φh1 Horizontal (Serial) CCD Clock - Phase 2 6, 7, 8, 31, 32, 33, 34, 35 N/C No Connect Notes: 1 - Pins 1, 2, 27, 39 and 40 must be connected together - only one Phase 2-clock driver is required 2 - Pins 3, 4, 28, 37 and 38 must be connected together - only one Phase 1-clock driver is required 3 - Pins 5, 10, 20, 21, 29 and 36 should be connected to a common potential 4 - Pins 9, 22 and 30 should be connected to a common potential 6 Revision No. 2

7 φv φv2 φv2 φv1 2 3 Pixel (2084,2084) φv2 φv1 φ V φv1 VSUB 5 36 VSUB N/C 6 35 N/C N/C 7 34 N/C N/C VGUARD SUB VDD2 VOUT2 VLG VSS VRD φr VDD N/C 32 VESD 31 N/C 30 VGUARD 29 VSUB 28 φv1 27 φv2 26 φh1 25 φh2 24 φh22 VOUT1 VOG Pixel (1,1) φh21 VGUARD VSUB VSUB Figure 3 - Pinout Diagram 7 Revision No. 2

8 2.0 Performance All values derived using nominal operating conditions with the recommended timing. Correlated doubling sampling of the output is assumed and recommended. Many units are expressed in electrons - to convert to a voltage, multiply by the amplifier sensitivity, Vout/Ne Electro-Optical Symbol Parameter Min. Nom. Max. Units Condition F F Optical Fill Factor 100 % PRNU Photoresponse Non-uniformity % rms Full Array QE Quantum Efficiency (450, 550, 650 nm) See Figure 4 - Spectral Response KAF-4301E Wavelength (nm) Figure 4 - Spectral Response 8 Revision No. 2

9 2.2 CCD Parameters CCD Parameters Common To both Outputs Symbol Parameter Min. Nom. Max. Units Condition Ne - sat Sat. Signal - Vccd register ke Note 2 Jd Dark Current pa/cm 2 e - pixel/sec 25ºC (mean of all pixels) DCDR Dark Current Doubling Temp o C DSNU Dark Signal Non-uniformity 540 e-/pix/sec Note 4 CTE Charge Transfer Efficiency Note 5 TVH V-H CCD Transfer Time 32 µs Note 6, 7,1 0 Bs Blooming Suppression none 1000 KAF-4301E Dark Current Temperature (C) Figure 5 - Dark current 9 Revision No. 2

10 2.2.2 CCD Parameters Specific to High Gain Output Amplifier Symbol Parameter Min. Nom. Max. Units Condition Vout/Ne- Output Sensitivity uv/electron Ne - sat Sat. Signal ke - Note 1 ne - total Total Sensor Noise e - rms Note 8 FH Horizontal CCD Frequency: MHz Note 6 DR Dynamic Range : db Note CCD Parameters Specific to Low Gain (high dynamic range) Output Amplifier Symbol Parameter Min. Nom. Max. Units Condition Vout/Ne- Output Sensitivity uv/electron Ne - sat Sat. Signal ke - Note 3 ne - total Total Sensor Noise e - rms Note 8 FH Horizontal CCD Frequency: MHz Note 6 DR Dynamic Range : db Note 9 Notes: 1. Point where the output saturates when operated with nominal voltages. 2. Signal level at the onset of blooming in the vertical (parallel) CCD register 3. Maximum signal level at the output of the high dynamic range output. This signal level will only be achieved when binning pixels containing large signals. 4. None of 256 sub arrays (128 x 128) exceed the maximum dark current specification. 5. For 2MHz data rate and T = 30ºC to -40ºC. 6 Using maximum CCD frequency and/or minimum CCD transfer times may compromise performance 7. Time between the rising edge of φ V1 and the first falling edge of φ H1 8. At Tintegration = 0; data rate = 1 MHz; temperature = -30ºC 9. Uses 20LOG(Ne - sat / ne - total) where Ne - sat refers to the appropriate saturation signal. 10. CTE corresponds to a signal level of e - /pix at 25 C and φh1, φh2 of 1MHz 10 Revision No. 2

11 2.3 Cosmetic Specification Grade Point Defects Cluster Defects Column Defects Double Columns C C C C Dark Defect A pixel which deviates by more than 20% from neighboring pixels when illuminated to 70% of saturation Bright Defect A pixel whose dark current exceeds 4500 electrons/pixel/second at 25ºC Cluster Defect Column Defect Neighboring Pixels A grouping of not more than 5 adjacent point defects. 1) A grouping point defects along a single column. (Dark Column) 2) A column that contains a pixel whose dark current exceeds 150,000 electrons/pixel/second at 25 C. (Bright Column) 3) A column that does not exhibit the minimum charge capacity specification. (Low charge capacity) 4) A column that loses >500 electrons when the array is illuminated to a signal level of 2000 electrons/pix. (Trap like defects) The surrounding 128 x 128 pixels of ± 64 columns/rows Cluster defects are separated by no less than 2 pixels from other column and cluster defects. Column defects are separated by no less than 5 pixels from other column defects. 1, ,2084 1,1 2084,1 11 Revision No. 2

12 3.0 Operation 3.1 Absolute Minimum/Maximum Ratings Min. Max. Units Conditions Temperature Storage C At Device Operating All Clocks Voltage VOG, VLG 0 +8 V VSUB = OV VRD, VSS, VDD, GUARD Current Output Bias Current (IDD) 10 ma Capacitance Output Load Capacitance (CLOAD) 10 pf φv1, φv2 Pulse Width 70 µs Frequency/Time φh1, φh2 2.5 MHz φr Pulse Width 20 ns Warning: For maximum performance, built-in gate protection has been added only to the VOG and VLG pin. These devices require extreme care during handling to prevent electrostatic discharge (ESD) induced damage. 3.2 DC Operating Conditions Min. Nom. Max. Units Pin Impedance VSUB Substrate V Common VDD Output Amplifier Supply V 5 pf, 2KΩ VSS Output Amplifier Return V 5 pf, 2KΩ VRD Reset Drain V 5 pf, 1MΩ VOG Output Gate V 5 pf, 10MΩ VGUARD Guard Ring V 350 pf, 10MΩ VLG Load Gate Vss-1.0 Vss Vss+1.0 V Notes: 1. An output load sink must be applied to Vout to activate output amplifier - see Figure below. +15V 0.1uF Vout ~5ma 2N3904 or equivalent R1 Ω 1k Ω Buffered Output The value of R1 depends on the desired output current according the following formula: R1 = 0.7 / Iout The optimal output current depends on the capacitance that needs to be driven by the amplifier and the bandwidth required. 5 ma is recommended for capacitance of 12 pf and pixel rates up to 20 MHz. Figure 6 - Typical Output Structure Load Diagram (For operation of up to 10 MHz) 12 Revision No. 2

13 3.3 AC Clock Level Conditions Min. Nom. Max. Units Pin Impedance φv1 Vertical Clock - Phase 1 Low V 700 nf, 10MΩ High V φv2 Vertical Clock - Phase 2 Low V 800 nf, 10MΩ High V φh1 Horizontal Clock - Phase 1 Low V 1200 pf, 10MΩ High V φh2 Horizontal Clock - Phase 2 Low V 1200 pf, 10MΩ High V φr Reset Clock Low V 10 pf, 10MΩ φh21 Horizontal Clock - Phase 1 φh22 Horizontal Clock - Phase 2 High V Using the High Gain Output (Vout 2) Using the High Dynamic Range Output (Vout1) Min. Nom. Max. Min. Nom. Max. Units Pin Impedance Low -4 φh2 φh2 φh2 V 10 pf, 10MΩ low low High -4 φh2 low φh2 low φh2 V Low φh2-4 φh2 φh2 V 10 pf, 10MΩ low low High φh2-4 φh2 φh2 V low low Note: When using Vout1 φh21 is clocked identically with φh2 while φh22 is held at a static level. When using Vout2 φh21 and φh22 are exchanged so that φh22 is identical to φh2 and φh21 is held at a static level. The static level should be the same voltage as φh2 low. Note: The AC and DC operating levels are for room temperature operation. Operation at other temperatures may require adjustments of these voltages. Pins shown with impedances greater than 1 MOhm are expected resistances. These pins are only verified to 1 MOhm. Note: φv1,2 and φh 1,2 capacitances are accumulated gate oxide capacitance, and so are an over-estimate of the capacitance. Note: This device is suitable for a wide range of applications requiring a variety of different operating conditions. Consult Eastman Kodak in those situations in which operating conditions meet or exceed minimum or maximum levels. 13 Revision No. 2

14 3.4 AC Timing Chart Description Symbol Min. Nom. Max. Units Notes fh1, fh2 Clock Frequency f H MHz 1, 2, 3 Pixel Period t pix ns fh1, fh2 Setup Time t φhs µs fv1 Clock Pulse Width t φv1 100 µs 2 fv2 Clock Pulse Width t φv2 150 µs 2 fv2, V1 Clock Pulse Overlap t φv2 150 µs 2 Reset Clock Pulse Width t φr ns 4 Readout Time t readout ms 5 Notes: 1. 50% duty cycle values. 2. CTE may degrade above the nominal frequency. 3. Rise and fall times (10/90% levels) should be limited to 5-10% of clock period. Crossover of register clocks should be between 40-60% of amplitude. 4. φr should be clocked continuously 5. t readout = (2092 * t line ) 6. Integration time (t int ) is user specified. Longer integration times will degrade noise performance due to dark signal fixed pattern and shot noise 7. t line = (3 * t φv ) + t φhs * t pix + t pix 14 Revision No. 2

15 Line Timing Detail Pixel Timing Detail φv1 tφv 1 1 line φr tφr φv2 tφv 2 φh1 te 1 count tφv- tφhs t e φh2 φh1 Vpix φh2 φr 2102 counts Vout Vsat Vdark Vodc Vsub Vertical Clock Timing Detail tφv1 = 100 µsec φv1 50 µsec φv2 t V-ovrlap = 50 µsec tφv2 = 150 µsec t V-ovrlap = 50 µsec Line Content Vsat Vdark Vpix Vodc Vsub Saturated pixel video output signal Video output signal in no light situation, not zero due to Jdark Pixel video output signal level, more electrons =more Video level offset with respect to vsub Analog Ground Photoactive Pixels Dummy Pixels * See Image Aquisition section Dark Reference Pixels Figure 7 - Timing diagrams 15 Revision No. 2

16 4.0 Storage and Handling 4.1 Storage Conditions Image sensors with temporary cover glass should be stored at room temperature (nominally 25ºC.) in dry nitrogen. 4.2 ESD CAUTION: This device contains limited protection against Electrostatic Discharge (ESD). This device is rated as Class 0 (<250V per JESD22 Human Body Model test), or Class A (<200V JESD22 Machine Model test.) Devices should be handled in accordance with strict ESD protection procedures. For more information see Application Note MTD/PS-0224, Electrostatic Discharge Control. 16 Revision No. 2

17 5.0 Quality Assurance and Reliability 5.1 Quality Strategy: All image sensors will conform to the specifications stated in this document. This will be accomplished through a combination of statistical process control and inspection at key points of the production process. Typical specification limits are not guaranteed but provided as a design target. For further information refer to ISS Application Note MTD/PS-0292, Quality and Reliability. 5.2 Replacement: All devices are warranted against failure in accordance with the terms of Terms of Sale. This does not include failure due to mechanical and electrical causes defined as the liability of the customer below. 5.3 Liability of the Supplier: A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer 5.4 Liability of the Customer: Damage from mechanical (scratches or breakage), electrical (ESD), or other electrical misuse of the device beyond the stated absolute maximum ratings, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. 5.5 Cleanliness: Devices are shipped free of mobile contamination inside the package cavity. Immovable particles and scratches that are within the imager pixel area and the corresponding cover glass region directly above the pixel sites are also not allowed. The cover glass is highly susceptible to particles and other contamination. Touching the cover glass must be avoided. See ISS Application Note DS , Cover Glass Cleaning, for further information. 5.6 ESD Precautions: Devices are shipped in static-safe containers and should only be handled at static-safe workstations. See ISS Application Note MTD/PS-0224 for handling recommendations. 5.7 Reliability: Information concerning the quality assurance and reliability testing procedures and results are available from the Image Sensor Solutions and can be supplied upon request. For further information refer to ISS Application Note MTD/PS-0292, Quality and Reliability. 5.8 Test Data Retention: Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for a period of 2 years after date of delivery. 5.9 Mechanical: The device assembly drawing is provided as a reference. The device will conform to the published package tolerances. 17 Revision No. 2

18 6.0 Mechanical Drawings and Specifications. Figure 8 - Package Mechanical Drawing - Page 1 18 Revision No. 2

19 Figure 8 - Package Mechanical Drawing - Page 2 19 Revision No. 2

20 6.1 Imager Flatness The flatness of the die is defined as a peak-to-peak distortion in the image sensor surface. The parallelism between the image sensor surface and any of the package components is not specified or guaranteed. The non-parallelism is removed when measuring the distortion in the image sensor surface. Minimum Nominal Maximum Unit Die Flatness Peak-to-Peak distortion microns Some examples of profiles from typical image sensors surfaces are shown below. Figure 9 - Surface Profile of Image Sensor Surface 20 Revision No. 2

21 Figure 10 - Surface Profile of Image Sensor Surface Figure 11 - Surface Profile of Image Sensor Surface 21 Revision No. 2

22 7.0 Ordering Information Address all inquiries and purchase orders to: Image Sensor Solutions Eastman Kodak Company Rochester, New York Phone: (716) Fax: (716) Kodak reserves the right to change any information contained herein without notice. All information furnished by Kodak is believed to be accurate. WARNING: LIFE SUPPORT APPLICATIONS POLICY Image Sensor Solutions, Eastman Kodak Company products are not authorized for and should not be used within Life Support Systems without the specific written consent of the Eastman Kodak Company. Product warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. Appendix 1: Revision Changes: Revision No. Date Changes 1 3/12/02 Initial formal version 2 9/19/02 Added Section 6.1 Imager Flatness 22 Revision No. 2