KAI-0373 IMAGE SENSOR 768 (H) X 484 (V) INTERLINE CCD IMAGE SENSOR MAY 20, 2013 DEVICE PERFORMANCE SPECIFICATION REVISION 2.

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1 KAI-0373 IMAGE SENSOR 768 (H) X 484 (V) INTERLINE CCD IMAGE SENSOR MAY 20, 2013 DEVICE PERFORMANCE SPECIFICATION REVISION 2.0 PS-0020

2 TABLE OF CONTENTS Summary Specification... 5 Description... 5 Features... 5 Applications... 5 Ordering Information... 6 Device Description... 7 Architecture... 7 Image Acquisition... 8 Charge Transport... 8 Output Structure... 8 Electronic Shutter... 9 Color Filter Array (optional, for KAI-0373-EBA only)... 9 On-Chip Gate Protection Physical Description Pin Description and Device Orientation Imaging Performance Specifications CCD Output V DD =15 V, V SS = 0.5 V General Electro-Optical for KAI-0373-ABA Monochrome with Microlens Electro-Optical for KAI-0373-CBA Color with Microlens Defect Definitions Typical Performance Curves Operation Absolute Maximum Ratings DC Bias Operating Conditions AC Operating Conditions Clock Levels Clock Line Capacitances Timing Requirements and Characteristics Frame Timing Line Timing Pixel Timing Electronic Shutter Timing CCD Clock Waveform Conditions Storage and Handling Storage Conditions ESD Cover Glass Care and Cleanliness Environmental Exposure Soldering Recommendations Mechanical Information Completed Assembly Die to Package Alignment Glass Revision 2.0 PS-0020 Pg 2

3 Glass Transmission Quality Assurance and Reliability Quality and Reliability Replacement Liability of the Supplier Liability of the Customer Test Data Retention Mechanical Life Support Applications Policy Revision Changes MTD/PS PS Revision 2.0 PS-0020 Pg 3

4 TABLE OF FIGURES Figure 1: Block Diagram... 7 Figure 2: Output Structure... 8 Figure 3: CFA Pattern... 9 Figure 4: Internal Protection Circuit for φh1 and φh Figure 5: Pin Description Figure 6: Typical KAI-0373 Photoresponse Figure 7: Color with Microlens Quantum Efficiency Figure 8: Monochrome with Microlens Quantum Efficiency Figure 9: Frame Timing Figure 10: Line Timing Figure 11: Pixel Timing Figure 12: Electronic Shutter Timing Figure 13: CCD Clock Waveform Figure 14: Completed Assembly Figure 15: Die to Package Alignment Figure 16: Glass Drawing Figure 17: Glass Transmission Revision 2.0 PS-0020 Pg 4

5 Summary Specification KAI-0373 Image Sensor DESCRIPTION The KAI-0373 is a high-performance silicon chargecoupled device (CCD) designed for video image sensing and electronic still photography. The device is built using an advanced true two-phase, double-polysilicon, NMOS CCD technology. The p+npn- photodetector elements eliminate image lag and reduce image smear while providing antiblooming protection and electronicexposure control. The total chip size is 9.9 (H) mm x 7.7 (V) mm. The KAI-0373 comes in monochrome and color versions, both with microlens for sensitivity improvement. FEATURES High resolution High sensitivity High dynamic range Low noise architecture High frame rate Binning capability for higher frame rate Electronic shutter APPLICATIONS Intelligent Traffic Systems Surveillance Parameter Architecture Number of Active Pixels Number of Outputs 1 Pixel Size Active Pixels Optical Size Active Pixels Size Aspect Ratio 3:2 Value Output Sensitivity 9 μv/e - Photometric Sensitivity KAI-0373-ABA Photometric Sensitivity KAI-0373-CBA Charge Capacity 55 ke - Maximum Pixel Clock Speed Maximum Frame Rate Package Type Package Size Package Pins 24 Interline Transfer CDD; Progressive Scan 768 (H) x 484 (V) 11.6 μm(h) x 13.6 μm (V) mm (diagonal) 2/3 optical format 8.91 mm (H) x 6.58 mm (V) 2.2 V/lux-sec 0.8 (B), 1.0 (G), 0.4 (R) V/lux-sec MHz 30 fps CerDIP [20.32 mm] width [30.48 mm] length Package Pin Spacing (2.54 mm) All parameters above are specified at T = 40 C Revision 2.0 PS-0020 Pg 5

6 Ordering Information Catalog Number 4H0407 4H0409 4H0408 4H0410 4H0412 4H0411 Product Name Description Marking Code KAI AAA-CP-BA KAI ABA-CB-AE KAI ABA-CB-BA KAI ABA-CP-BA KAI EBA-CB-AE KAI EBA-CB-BA Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass (no coatings), Standard Grade Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Sealed Clear Cover Glass (no coatings), Engineering Grade Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Sealed Clear Cover Glass (no coatings), Standard Grade Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass (no coatings), Standard Grade Color (3 stagger), Telecentric Microlens, CERDIP Package (sidebrazed), Sealed Clear Cover Glass (no coatings), Engineering Grade Color (3 stagger), Telecentric Microlens, CERDIP Package (sidebrazed), Sealed Clear Cover Glass (no coatings), Standard Grade KAI-0373-AAA Serial Number KAI-0373-ABA Serial Number KAI-0373-EBA Serial Number See Application Note Product Naming Convention for a full description of the naming convention used for Truesense Imaging image sensors. For reference documentation, including information on evaluation kits, please visit our web site at Please address all inquiries and purchase orders to: Truesense Imaging, Inc Lake Avenue Rochester, New York Phone: (585) info@truesenseimaging.com Truesense Imaging reserves the right to change any information contained herein without notice. All information furnished by Truesense Imaging is believed to be accurate. Revision 2.0 PS-0020 Pg 6

7 12 Dark Columns KAI-0373 Image Sensor Device Description ARCHITECTURE V2B V2B V1B V1B V2A V2A V1A KAI-0373 V1A Usable Active Image Area 768(H) x 484(V) 11.6 m X 13.6 m pixels LTSH Vrd R VLG Vdd Vout Vss WELL 5 Dark Rows 768 Active Pixels/Line H1 H = 791 Pixels/Line SUBS OG Figure 1: Block Diagram The KAI-0373 consists of 371,712 photodiodes, 768 vertical (parallel) CCD shift registers (VCCDs), one horizontal (serial) CCD shift register and one output amplifier. The advanced, progressive-scan architecture of the device allows the entire image area to be read out in a single scan. The pixels are arranged in a 768 (H) x 484 (V) array in which an additional 12 columns and 5 rows of light shielded pixels are added as dark reference. Revision 2.0 PS-0020 Pg 7

8 IMAGE ACQUISITION An electronic representation of an image is formed when incident photons falling on the sensor plane create electronhole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the photodiode's charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. CHARGE TRANSPORT The accumulated or integrated charge from each photodiode is transported to the output by a three step process. The charge is first transported from the photodiodes to the VCCDs by applying a large positive voltage to the phase-one vertical clock (φv2). This reads out every row, or line, of photodiodes into the VCCDs. The charge is then transported from the VCCDs to the HCCDs line by line. Finally, the HCCDs transport these rows of charge packets to the output structures pixel by pixel. On each falling edge of the horizontal clock, φh2, these charge packets are dumped over the output gate (OG, Figure 2) onto the floating diffusion (FD Figure 2). Both the horizontal and vertical shift registers use traditional two-phase complementary clocking for charge transport. Transfer to the horizontal CDD begins when φv2 is brought low (and φv1 high) causing a line of charge to transfer from φv2 to φv1 and subsequently into the horizontal register. The sequence completes when φv1 is brought low before the horizontal CCD reads the first line of charge. OUTPUT STRUCTURE Charge packets contained in the horizontal register are dumped pixel by pixel, onto the floating diffusion output node whose potential varies linearly with the quantity of charge in each packet. The amount of potential change is determined by the expression ΔVfd=ΔQ/Cfd. A three stage source-follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. The translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of µv/e -. After the signal has been sampled off-chip, the reset clock (φr) removes the charge from the floating diffusion and resets its potential to the reset-drain voltage (VRD). Vdd R VRD FD SUB Vout WELL VLG Vss FD = Floating Diffusion Figure 2: Output Structure Revision 2.0 PS-0020 Pg 8

9 ELECTRONIC SHUTTER The KAI-0373 provides a structure for the prevention of blooming which may be used to realize a variable exposure time as well as performing the anti-blooming function. The anti-blooming function limits the charge capacity of the photodiode by draining excess electrons vertically into the substrate (hence the name Vertical Overflow Drain or VOD). This function is controlled by applying a large potential to the device substrate (device terminal SUB). If a sufficiently large voltage pulse (VES 40V) is applied to the substrate, all photodiodes will be emptied of charge through the substrate, beginning the integration period. After returning the substrate voltage to the nominal value, charge can accumulate in the diodes and the charge packet is subsequently readout onto the VCCD at the next occurrence of the high level on φv2. The integration time is then the time between the falling edges of the substrate shutter pulse and φv2. This scheme allows electronic variation of the exposure time by a variation in the clock timing while maintaining a standard video frame rate. Application of the large shutter pulse must be avoided during the horizontal register readout or an image artifact will appear due to feedthrough. The shutter pulse VES must be hidden in the horizontal retrace interval. The integration time is changed by skipping the shutter pulse from one horizontal retrace interval to another. The smear specification is not met under electronic shutter operation. Under constant light intensity and spot size, if the electronic exposure time is decreased, the smear signal will remain the same while the image signal will decrease linearly with exposure. Smear is quoted as a percentage of the image signal and so the percent smear will increase by the same factor that the integration time has decreased. This effect is basic to interline devices. Extremely bright light can potentially harm solid state imagers such as Charge-Coupled Devices (CCDs). Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. COLOR FILTER ARRAY (OPTIONAL, FOR KAI-0373-EBA ONLY) The pattern used is the staggered 3G color mosaic filter pattern (Figure 3), The CFA contains 75% green photosites and 25% red and blue photosites. Other CFA patterns may be available upon request. G G G R G B G G G G G R Output G B G G First Active Pixel Figure 3: CFA Pattern Revision 2.0 PS-0020 Pg 9

10 ON-CHIP GATE PROTECTION Gates OG, φr, VLG, VSS, φh1 and φh2 are internally connected to transistors as shown in Figure 4 to provide active ESD protection. For the protection to work, pin 11 (Horizontal ESD well) and pin 13 (Vertical ESD well) must be biased to 10V. The ESD bias must be at least 1V more negative that φh1 and φh2 during sensor operation and during camera power turn on. This sensor, like most other MOS-based image sensors, is extremely sensitive to electrostatic discharge (ESD) damage. The handling and environment of the sensor must be controlled to protect this device from ESD damage. PIN CONNECTION GATE Snap-back field FET Horizontal ESD Well Figure 4: Internal Protection Circuit for φh1 and φh2 Revision 2.0 PS-0020 Pg 10

11 Physical Description Pin Description and Device Orientation OG 1 24 V2A R 2 23 V1A VRD 3 22 V2B VSS 4 Pixel 1,1 21 V1B VLG 5 20 WELL VOUT 6 19 SUB VDD 7 18 LTSH WELL 8 17 V1A H V2A H V1B ESD V2B NC ESD Pin 1 Locator Side View Of Package Figure 5: Pin Description Pin Name Description Pin Name Description 1 OG Output Gate 24 φv2a Vertical CCD Clock Phase 2 2 φr Reset Clock 23 φv1a Vertical CCD Clock Phase 1 3 VRD Reset Drain 22 φv2b Vertical CCD Clock Phase 2 4 VSS Output Amplifier Return 21 φv1b Vertical CCD Clock Phase 1 5 VLG Output Amplifier Load Gate 20 WELL Ground 6 VOUT Video Output 19 SUB Substrate 7 VDD Output Amplifier Supply 18 LTSH Lightshield 8 WELL Ground 17 φv1a Vertical CCD Clock Phase 1 9 φh2 Horizontal CCD Clock Phase 2 16 φv2a Vertical CCD Clock Phase 2 10 φh1 Horizontal CCD Clock Phase 1 15 φv1b Vertical CCD Clock Phase 1 11 ESD Horizontal ESD Well 14 φv2b Vertical CCD Clock Phase 2 12 NC No Connect 13 ESD Vertical ESD Well Notes: 1. The pins are on a spacing 2. Pins 14, 16, 22, and 24 must be connected together only one Phase 2 clock driver is required. 3. Pins 15, 17, 21, and 23 must be connected together only one Phase 1 clock driver is required. Revision 2.0 PS-0020 Pg 11

12 Imaging Performance All following values were derived for the KAI-0373-ABA series devices (with microlens array) using nominal operating conditions and the recommended timing. Unless otherwise stated, readout time = 33 msec, integration time = 33 msec, no electronic shutter pulse is applied, and sensor temperature = 40 C. Correlated double sampling of the output is assumed and recommended. Defects are excluded from the following tests and the signal output is referenced to the dark pixels at the end of each line unless otherwise specified. SPECIFICATIONS CCD Description Symbol Min. Nom. Max. Units Notes Saturation Signal VCCD Ne - sat 55 ke - Output Saturation Signal Vsat 500 mv 1, 2, 6 Photodiode Dark Current Id 0.5 na Charge Transfer Efficiency CTE , 3 Horizontal CCD Frequency f H 14.3 MHz Image Lag IL negligible Blooming Margin Xab 300 4, 6 Smear Smr % 5 Notes: 1. Vsat is the mean value at saturation as measured at the output of the device with Xab=300. This value is guaranteed only when Vsub=Vab as indicated on the sensor package. Vsat can be varied by adjusting Vsub. 2. Measured at the sensor output. 3. With stray load capacitance of C L = 10 pf between the output and AC ground. 4. Xab represents the increase above the saturation-irradiance level (Hsat) that the device can be exposed to before blooming of the vertical shift register will occur. It should be noted that Vout rises above Vsat for irradiance levels above Hsat. 5. Measured under 10% (~48 lines) image height illumination with white light source and without electronic shutter operation and below Vsat. 6. It should be noted that there is a tradeoff between Xab and Vsat. Output V DD =15 V, V SS = 0.5 V Description Symbol Min. Nom. Max. Units Notes Output DC Offset Vodc V Power Dissipation Pd 75 mw Output Amplifier Bandwidth f- 3db 100 MHz 1 Sensitivity (Output Referred) ΔVo/ΔN 9 μv/e - Off-Chip Load C L 10 pf Notes: 1. With stray output load capacitance of CL = 10 pf between output and AC ground. Revision 2.0 PS-0020 Pg 12

13 GENERAL Description Symbol Min. Nom. Max. Units Notes Total Sensor Noise Ne - total 55 e - rms 1 Dynamic Range DR 60 db 2 Notes: 1. Includes amplifier noise, dark pattern noise and dark current shot noise at data rates of 14 MH z. 2. Uses 20 LOG (Ne - sat/ne total) where Ne - sat refers to the vertical CCD saturation signal. Electro-Optical for KAI-0373-ABA Monochrome with Microlens Description Symbol Min. Nom. Max. Units Notes Saturation Exposure Esat μj/cm 2 1 Peak Quantum Efficiency QE 35 % 2 Photoresponse Non-uniformity PRNU 2.0 % rms 3 Photoresponse Non-linearity PRNL 2.0 % Photoresponse Shading Rs 10 % 4 Notes: 1. For λ = 530 nm wavelength, and Nsat= 55 ke Refer to typical values from Figure For a 100 x 100 pixel region under uniform illumination with output signal equal to 80% of saturation signal. Saturation signal, Vsat, is the output voltage at the knee of the output vs illumination curve as shown in Figure This is the global variation in chip output across the entire chip measured at 80% saturation and is expressed as a percentage of the mean pixel value. Saturation signal, Vsat, is the output voltage at the knee of the output vs illumination curve as shown in Figure 6. Revision 2.0 PS-0020 Pg 13

14 Output Signal - Vout - (mv) KAI-0373 Image Sensor Electro-Optical for KAI-0373-CBA Color with Microlens Description Symbol Min. Nom. Max. Units Notes Green Pixel Saturation Exposure Esat μj/cm 2 1 Red Peak Quantum Efficiency λ = 650 nm QEr 29 % 2 Green Peak Quantum Efficiency λ = 530 nm QEg 34 % 2 Blue Peak Quantum Efficiency λ = 450 nm QEb 37 % 2 Photoresponse Non-uniformity PRNU 5.0 % rms 3 Photoresponse Non-linearity PRNL 2.0 % Green Photoresponse Shading Rgs 10 % 4 Notes: 1. For λ = 530nm wavelength, and Vsat = 55 ke Refer to typical values from Figure For a 100 x 100 pixel region under uniform illumination with output signal equal to 80% of saturation signal. Saturation signal, Vsat, is the output voltage at the knee of the output vs illumination curve as shown in Figure This is the global variation in chip output for green pixels across the entire chip measured at 80% saturation and is expressed as a percentage of the mean pixel value. Saturation signal, Vsat, is the output voltage at the knee of the output vs illumination curve as shown in Figure (Hsat, Vsat) Sensor Plane Irradiance - H - (arb) Figure 6: Typical KAI-0373 Photoresponse Revision 2.0 PS-0020 Pg 14

15 DEFECT DEFINITIONS All values are derived under normal operating conditions at 40 C operating temperature. Defect Type Defect Definition Number Allowed Notes Defective Pixel Bright Defect Under uniform illumination with mean pixel output of 400mV, a defective pixel deviates by more than 15% from the mean value of all active pixels in its section Under dark field conditions, a bright defect deviates more than 15 mv from the mean value of all pixels in its section 5 1, 2, 3 0 1, 2, 3 Cluster Defect Two or more vertically or horizontally adjacent defective pixels 0 2, 3 Notes: 1. Sections are 256 (H) x 242 (V) pixel groups, which divide the imager into six equal areas as shown below. 2. For the color device, KAI-0373-EBA, a defective pixel deviates by more than 15% from the mean value of all active pixels in its section with the same color. 3. Test conditions: Junction temperature = 40 C, integration time = 33 msec and readout time = 33 msec. (1,484) (768,484) (1,1) (768,1) Revision 2.0 PS-0020 Pg 15

16 Q u a n tu m E ffic ie n c y (% ) Quantum Efficiency (%) KAI-0373 Image Sensor Typical Performance Curves 40% 35% 30% 25% Blue Green Red 20% 15% 10% 5% 0% Wavelenght (nm) Figure 7: Color with Microlens Quantum Efficiency 40% 35% 30% 25% 20% 15% 10% 5% 0% W a v e le n g th (n m ) Figure 8: Monochrome with Microlens Quantum Efficiency Revision 2.0 PS-0020 Pg 16

17 Operation ABSOLUTE MAXIMUM RATINGS Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or the condition is exceeded, the device will be degraded and may be damaged. Rating Description Min Max Units Notes Temperature (@ 10% 5% RH) Voltage (Between Pins) Operation to Specification C Operation Without Damage C Storage C SUB-WELL V 1, 3 VRD, VDD, and VSS-WELL V 2 All Clocks - WELL 17 V 2 φv1 - φv2 17 V 2 φh1 - φh2 17 V 2 φh1, φh2 - φv2 17 V 2 φh2 - OG 17 V 2 All Clocks - LTSH 17 V 2 VLG, OG - WELL 17 V 2 All Gates LTSH 17 V 2 Current Output Bias Current (IDD) ma Capacitance Output Load Capacitance (CLOAD) pf Notes: 1. Under normal operating conditions the substrate voltage should be above +7 V, but may be pulsed to 40 V for electronic shuttering. 2. Care must be taken in handling so as not to create static discharge which may permanently damage the device. 3. Refer to Application Note Using Interline CCD Image Sensors s in High Intensity Visible Lighting Conditions. Revision 2.0 PS-0020 Pg 17

18 DC BIAS OPERATING CONDITIONS Description Symbol Minimum Nominal Maximum Units Notes Output Gate OG V Reset Drain VRD V Output Amplifier Return VSS V Output Amplifier Load Gate VLG V Output Amplifier Supply VDD V Well WELL 0.0 V Lightshield LTSH 0.0 V Substrate SUB +7.0 Vab +25 V 1, 4 Output Bias Current IOUT ma 2 ESD Bias ESD -10 V 3 Notes: 1. The operating value of the substrate voltage, Vab, will be marked on the shipping container for each device. The substrate is clocked in electronic shutter mode operation. A shutter pulse with voltage less than 50V for less than 100 μs is allowed. See AC Clock Level Conditions and AC Timing Requirements. Well and substrate biases should be established before other gate and diode potentials are applied. 2. A 1.8 k resistor between VOUT and ground is recommended to obtain IOUT = 5 ma. VOUT must not be shorted to ground. 3. Pins 11 and 13 are biased to 10V. The ESD bias must be at least 1V more negative than φh1 and φh2 during sensor operation AND during camera power turn on. 4. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. Revision 2.0 PS-0020 Pg 18

19 AC OPERATING CONDITIONS Clock Levels Description Symbol Minimum Nominal Maximum Units Notes Vertical CCD Clocks - High φv1h, φv2h V 1 Vertical CCD Clocks - Mid φv1m, φv2m V 1 Vertical CCD Clocks - Low φv1l, φv2l V 1 Horizontal CCD Clocks - High φh1h, φh2h V 1 Horizontal CCD Clocks - Low φh1l, φh2l V 1 Reset Clock - High φrh V Reset Clock - Low φrl V For Electronic Shutter Pulse Only VES (SUB) V 2, 3 Notes: 1. For best results, the CCD clock swings must be maintained at (or greater than) the values indicted by the nominal level conditions noted above. 2. This pulse, used only for electronic shutter mode operation, is applied to the substrate, as described in the Electronic Shutter section of this document. Dynamic resistance is 3 kω and typical DC current is 3 ma at VSUB = 40 V. 3. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. CLOCK LINE CAPACITANCES Description Symbol Typical Units Vertical CCD Clocks - Well VCCD Clock Phase 1 - VCCD Clock Phase 2 C φv1, φv2 (A, B combined) C φv1 - φv2 (A, B combined) 10 nf 1.5 nf Horizontal CCD Clocks - Well C φh1, φh2 150 pf HCCD Clock Phase 1 - HCCD Clock Phase 2 C φh1 - φh2 60 pf Reset Clock - Well C φr 5 pf For Electronic Shutter Pulse C SUB 400 pf Revision 2.0 PS-0020 Pg 19

20 Timing REQUIREMENTS AND CHARACTERISTICS Description Symbol Minimum Nominal Maximum Units Notes Vertical High Level Duration t φvh μsec Vertical Transfer Time t φv 2.8 μsec Vertical Pedestal Delay t φvpd 10 μsec Horizontal Delay t φhd 5.3 μsec Reset Duration t φr nsec 1 Horizontal Clock Frequency f φh MHz Line Time t L 63.5 μsec Vertical Delay t φvd 200 nsec Horizontal Delay with Electronic Shutter t φhves 1.0 μsec Clamp Delay t cd nsec 2 Sample Delay t sd nsec 2 Electronic Shutter Pulse Duration t es 4 5 μsec 3 Notes: 1. The rising edge of φr should be coincident with the rising edge of φh2, within ±5 nsec. 2. The clamp delay and sample delay should be adjusted for optimum results. 3. This pulse is used only with electronic shuttering and should not be used during horizontal readout. The electronic shutter pulse should be hidden in the horizontal retrace interval. Revision 2.0 PS-0020 Pg 20

21 KAI-0373 Image Sensor FRAME TIMING 525 V1 (A & B) V2 (A & B) Integration Time t int VES (SUB) (Electronic Shutter Mode Only) tl V1 (A & B) V2 (A & B) 1 Line Time = tl = 63.5 sec t VPD t VH t VPD Vertical Overclocking Figure 9: Frame Timing Note: When no electronic shutter is used, the integration time is equal to the frame time. Revision 2.0 PS-0020 Pg 21

22 KAI-0373 Image Sensor LINE TIMING 1 Line = 791 Pixels t V tl = 63.5 sec V1 V2 t VD t HD H1 H sec R Line Content H1/ H2 Count Empty Shift Register Phases Dark Reference Pixels Photoactive Pixels Figure 10: Line Timing Revision 2.0 PS-0020 Pg 22

23 Signal Signal KAI-0373 Image Sensor PIXEL TIMING H1 1 count = 1 Pixel 69.8 nsec H2 R t R VOUT Reference CLAMP t cd SAMPLE Video After Correlated Double Sampling (Inverted) t sd Reference Figure 11: Pixel Timing Revision 2.0 PS-0020 Pg 23

24 ELECTRONIC SHUTTER TIMING t VH V2 t V t VD t HD H1 t HVES VES (SUB) t es t int Figure 12: Electronic Shutter Timing CCD Clock Waveform Conditions Description Symbol twh twl tr tf Units Notes Vertical CCD Clocks - Phase 1 φv1m μsec 1 Vertical CCD Clocks - Phase 2 φv2m μsec 1 Vertical CCD Clocks - Phase 2, High φv2h μsec 1 Horizontal CCD Clocks - Phase 1 φh nsec 1 Horizontal CCD Clocks - Phase 2 φh nsec 1 Reset Clock φμr nsec 1 For Electronic Shutter Pulse Only VES(SUB) μsec 1 Notes: 1. Typical values measured with clocks connected to image sensor device. 90% tr twh tf High 100% twl 10% Low 0% Figure 13: CCD Clock Waveform Revision 2.0 PS-0020 Pg 24

25 Storage and Handling STORAGE CONDITIONS Item Description Min Max Units Conditions Notes Operation to Specification Temperature % 5% RH 1, 2 Humidity C Temp. 1, 2 Operation Without Damage Temperature % 5% RH 2, 3 Storage Temperature % 5% RH 2, 4 Humidity C Temp. 2, 4 Notes: 1. The image sensor shall meet the specifications of this document while operating at these conditions. 2. The tolerance on all relative humidity values is provided due to limitations in measurement instrument accuracy. 3. The image sensor shall continue to function but not necessarily meet the specifications of this document while operating at the specified conditions. 4. The image sensor shall meet the specifications of this document after storage for 15 days at the specified conditions. ESD 1. This device contains limited protection against Electrostatic Discharge (ESD). ESD events may cause irreparable damage to a CCD image sensor either immediately or well after the ESD event occurred. Failure to protect the sensor from electrostatic discharge may affect device performance and reliability. 2. Devices should be handled in accordance with strict ESD procedures for Class 0 (<250 V per JESD22 Human Body Model test), or Class A (<200 V JESD22 Machine Model test) devices. Devices are shipped in static-safe containers and should only be handled at static-safe workstations. 3. See Application Note Image Sensor Handling Best Practices for proper handling and grounding procedures. This application note also contains workplace recommendations to minimize electrostatic discharge. 4. Store devices in containers made of electro-conductive materials. COVER GLASS CARE AND CLEANLINESS 1. The cover glass is highly susceptible to particles and other contamination. Perform all assembly operations in a clean environment. 2. Touching the cover glass must be avoided. 3. Improper cleaning of the cover glass may damage these devices. Refer to Application Note Image Sensor Handling Best Practices. ENVIRONMENTAL EXPOSURE 1. Extremely bright light can potentially harm CCD image sensors. Do not expose to strong sunlight for long periods of time, as the color filters and/or microlenses may become discolored. In addition, long time exposures to a static high contrast scene should be avoided. Localized changes in response may occur from color filter/microlens aging. For Interline devices, refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible lighting Conditions. 2. Exposure to temperatures exceeding maximum specified levels should be avoided for storage and operation, as device performance and reliability may be affected. Revision 2.0 PS-0020 Pg 25

26 3. Avoid sudden temperature changes. 4. Exposure to excessive humidity may affect device characteristics and may alter device performance and reliability, and therefore should be avoided. 5. Avoid storage of the product in the presence of dust or corrosive agents or gases, as deterioration of lead solderability may occur. It is advised that the solderability of the device leads be assessed after an extended period of storage, over one year. SOLDERING RECOMMENDATIONS 1. The soldering iron tip temperature is not to exceed 370 C. Higher temperatures may alter device performance and reliability. 2. Flow soldering method is not recommended. Solder dipping can cause damage to the glass and harm the imaging capability of the device. Recommended method is by partial heating using a grounded 30 W soldering iron. Heat each pin for less than 2 seconds duration. Revision 2.0 PS-0020 Pg 26

27 Mechanical Information COMPLETED ASSEMBLY Figure 14: Completed Assembly Notes: 1. See Ordering Information for Marking Code. 2. Cover Glass is manually placed and visually aligned over die location accuracy is not guaranteed. Revision 2.0 PS-0020 Pg 27

28 DIE TO PACKAGE ALIGNMENT Figure 15: Die to Package Alignment Revision 2.0 PS-0020 Pg 28

29 GLASS 4X C EPOXY Notes: 1. Dust/Scratch Count: 10 microns max 2. Epoxy Thickness: Glass: Schott D-263T eco or equivalent 8X C Figure 16: Glass Drawing Revision 2.0 PS-0020 Pg 29

30 Transmission (%) KAI-0373 Image Sensor GLASS TRANSMISSION Wavelength (nm) Figure 17: Glass Transmission Revision 2.0 PS-0020 Pg 30

31 Quality Assurance and Reliability QUALITY AND RELIABILITY All image sensors conform to the specifications stated in this document. This is accomplished through a combination of statistical process control and visual inspection and electrical testing at key points of the manufacturing process, using industry standard methods. Information concerning the quality assurance and reliability testing procedures and results are available from Truesense Imaging upon request. For further information refer to Application Note Quality and Reliability. REPLACEMENT All devices are warranted against failure in accordance with the Terms of Sale. Devices that fail due to mechanical and electrical damage caused by the customer will not be replaced. LIABILITY OF THE SUPPLIER A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. Product liability is limited to the cost of the defective item, as defined in the Terms of Sale. LIABILITY OF THE CUSTOMER Damage from mishandling (scratches or breakage), electrostatic discharge (ESD), or other electrical misuse of the device beyond the stated operating or storage limits, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. TEST DATA RETENTION Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for a period of 2 years after date of delivery. MECHANICAL The device assembly drawing is provided as a reference. Truesense Imaging reserves the right to change any information contained herein without notice. All information furnished by Truesense Imaging is believed to be accurate. Life Support Applications Policy Truesense Imaging image sensors are not authorized for and should not be used within Life Support Systems without the specific written consent of Truesense Imaging, Inc. Revision 2.0 PS-0020 Pg 31

32 Revision Changes MTD/PS-0660 Revision Number Description of Changes 1.0 Initial formal release 2.0 Updated format Updated package drawings to show new part marking. Updated ordering information with new part markings. 3.0 Moved and updated Ordering Information Page 3.1 Changed glass reference to Schott D-263T eco or equivalent 4.0 Added the note Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions to the following sections o Electronic Shutter o Absolute Maximum Ratings o DC Bias Operating Conditions o AC Operating Conditions o Storage and Handling PS-0020 Revision Number 1.0 Description of Changes Initial release with new document number, updated branding and document template Updated Storage and Handling and Quality Assurance and Reliability sections 2.0 For each catalog number in the Ordering Information table, clarified if the cover glass is taped or sealed Revision 2.0 PS-0020 Pg 32 Truesense Imaging Inc., TRUESENSE is a registered trademark of Truesense Imaging, Inc.

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