123 CHAPTER 4 CARBON NANOTUBE TRASISTOR BASED LOW POWER ANALOG ELECTRONIC CIRCUITS REALIZATION 4.1 INTRODUCTION Operational amplifiers (usually referred to as OPAMPs) are key elements of the analog and mixed signal circuit. Designing high-performance analog integrated circuits is becoming increasingly exigent with the relentless trend towards reduced supply voltages. At large supply voltages, there is a tradeoff among speed, power, and gain, amid other performance parameters. CMOS technology is approaching its limits in the presence of challenges like extreme short-channel effects, lithographic limitations, process variations, leakage current and source-to-drain tunneling (Thompson et al 2006). Many technological and device structure variations have been proposed in the literature like ultra-thin body single or multiple-gate FETs, SOI FETs, FinFETs, and CNFETs etc. to provide improvements in electrostatics over CMOS. Among that, FinFETs and CNFETs have been recently becoming a key technology for low-power, low-voltage mixed analog-digital applications (Chau et al 2005). Carbon nanotube based transistor has significant potential to replace CMOS in the future due to its better electrostatics and higher mobility (Appenzeller et al 2008). There is a need to explore circuit designs and its application in new emerging technologies for their rapid commercialization to extend Moore s law beyond 32 nm technology node.
124 4.2 LITERATURE REVIEW ABOUT CARBON NANOTUBE TRANSISTOR BASED ANALOG CIRCUITS The potential to exploit single-walled carbon nanotubes (SWNTs) in advanced electronics represents a continuing, major source of interest in these materials. However, scalable integration of SWNTs into circuits is challenging because of difficulties in controlling the geometries, spatial positions, and electronic properties of individual tubes. The following Table 4.1 shows the literature review of the CNT based analog circuits for high frequency application. Table. 4.1 Literature review of the CNFET based analog circuits CNT based Analog Circuits RF Circuit Model for Carbon Nanotubes Nanowire and Nanotube based Antenna Experimental or Simulation Study CNT GHz nano-resonators Experimental Study Reference Simulation Study Burke et al 2003 Simulation Study Burke et al 2004 Shengdong et al 2004 Narrow band amplifiers Experimental Study Kocabas et al 2008 By utilizing the property of the CNT transistor, GHz frequency operation, there is a need to explore analog circuit and its application for their rapid commercialization. Even though, there has been a lot of work available in the literature on the digital (Wang et al 2012) and analog circuit (Usmani & Hasan 2010), In this research work, we proposed optimum design and analysis of low-power, low-voltage two stage operational amplifier and its application circuits using CNFET technology are presented. Simulation result of the proposed CNFET technology based operational amplifier performance
125 characteristics and its application circuit s power consumptions are compared with conventional CMOS technology. From the comparison result, The CNFET OPAMP effectiveness and its advantages for low-power, low-voltage analog circuit applications are observed. 4.3 DESIGN AND ANALYSIS OF CNFET BASED TWO STAGE OPERATIONAL AMPLIFIER (OPAMP) CIRCUIT 4.3.1 Design Methodology In this section, we designed and implemented the operational amplifiers based on the CNFET technology at 32nm node. Synopsys HSPICE are the electrical circuit simulator. CNFET based two-stage Miller compensated operational amplifier is shown in Figure 4.1. CNFET based operational amplifier circuit is designed in terms of optimum structural device parameters namely Number of nanotubes (N), diameter of CNT, uniform inter-nanotube spacing pitch (S) and input supply voltage (V). The main design issue for the analog designer, when dealing with a CNFET technology, is the sizing of the transistors in order to achieve the desired electrical characteristics. In the CMOS version the optimization variables are the width (W) and length (L) of the transistors, and in the CNFET version the variables are N, S and V. The operational amplifier design parameter values are chosen from the literature for both CMOS and CNFET (Usmani & Hasan 2010) version which are shown in Table 4.2.
126 Table 4.2 Optimized circuit parameters and its value of CNFET OPAMP Parameter 32nm CMOS design 32nm CNFET design DCNT= 1.5nm W L N S M 1 and M 2 8.38 µm 0.47 µm 45 12 M 3 and M 4 0.29 µm 0.59 µm 22 12 M 5 2.15 µm 0.31 µm 92 12 M 6 9.99 µm 0.10 µm 257 8 M 7 3.40 µm 0.16 µm 128 8 M 8 3.40 µm 0.16 µm 3 12 I Bias 3 µa 1.81 µa V DD = [-V SS ] 1V 0.9V C c 5pF 3pF C L 15pF 10pF V dd M 3 M 4 M 6 C c V in- M 1 M 2 V in+ M 8 C L V in+ V in- + - V out M 5 M 7 V bias V ss Figure 4.1 Two stage CNFET OPAMP with Miller compensation
127 4.3.1.1 Optimizing the number of CNTs It is important to determine the number of CNTs to be used in an array in order to ensure suf cient current supply for driving xed capacitive loads as single nanotube based transistor does not provide competitive performance over traditional silicon devices (Deng et al 2007a, Balijepalli et al 2007). Therefore, we need to choose optimum value of N for better current driving capability of CNFET with reduced output resistance, thereby allowing greater fan-out factor. From the Analytical results, it can be inferred that, the CNFET OPAMP circuits gain, bandwidth, power delay product (PDP) value changes occur corresponding increase in N value as shown in Figure 4.2. I CNFET NgCNT ( VDD Vth ) 1 g L CNT s S (4.1) It is important to investigate the problem associated with large number of tubes in addition to geometrical constraints. Here, the current per tube I PERTUBE (~20 ma) is constant owing to non-varying S but laying of more tubes increases the net width W and the on-current approximately given by Equation (4.1). This is due to the signi cant increase in transconductance (g CNT ) with the increase in number of nanotubes (Mintmire et al 1998, Sinha et al 2008). The increase in transconductance further increases the parasitics of the devices. Hence, the upper limit on the number of CNTs used is determined by the power-performance trade-off but still looking at the overall performance merits obtained, sufficient number of tubes must be chosen.
128 (a) (b) (c) Figure 4.2 (a) Variation of DC Gain with number of CNTs (b) Variation of bandwidth with number of CNTs (c) Variation of power consumption with number of CNTs
129 4.3.1.2 Optimizing CNT diameter CNFET circuit performance and electrical behavior directly depends on the CNT diameter. Diameter is the main parameter that affects the oncurrent proportionally in a CNFET apart from barrier height at the S/D contact (or RS/D), chirality and oxide thickness but for larger diameters, current tends to saturate due to large screening and scattering effects (Saito et al 1998). From the Analytical results, it can be inferred that, the CNFET OPAMP circuits gain, bandwidth, power-delay product (PDP) value changes occur corresponding increase in diameter of the nanotube as shown in Figure 4.3. This is because the transconductance goes up with the increase in diameter of the nanotubes. The DC gain reduces with diameter due to the fact that the lowering of output resistance with diameter is more than the increase in its transconductance. The bandwidth of the amplifier increases with diameter due to the reduction in gate-to-channel capacitance on account of enhanced CNT to CNT screening and higher value of transconductance (Deng et al 2007a). Therefore, opting for a suitable value of diameter is a compromise between conflicting requirements. Making a selection for the optimal diameter requires the cross-points obtained on the graphs which indicate the optimum value of diameter, corresponding to power limited, moderate bandwidth, high gain application to be around 1.5 nm. Moreover, a slight shift could also be observed when opting for optimizing one parameter over the other such as a diameter of 2.0 nm is best for high power, wide bandwidth and moderate gain applications.
130 (a) (b) (c) Figure 4.3 (a) Variation of DC Gain with CNT diameter (b) Variation of bandwidth with CNT diameter (c) Variation of power consumption with CNT diameter
131 4.3.1.3 Optimizing spacing between CNTs It is clear from Figure 4.4, that with the increase in inter-tube spacing S (i.e. pitch) the gain decreases while the bandwidth goes up. This is due to the fact that as CNTs are brought closer, the capacitance from the gate to each CNT channel decreases because each CNT can mirror a small amount of charge from the gate. With larger spacing, the number of current carrying CNTs decreases, thereby, reducing the universal density of states (DOS). This indirectly affects the transconductance given by Equation 4.1. Power dissipation goes up due to higher parasitics with the increase in pitch. Compact packing of tubes deteriorates the overall performance and so many tradeoffs are involved which make it difficult to go for an optimum choice of pitch S. (a) (b)
132 Figure 4.4 (a)variation of DC Gain with inter-cnt pitch (b) Variation of bandwidth with inter-cnt pitch (c) Variation of power consumption with inter-cnt pitch 4.3.2 Result and Discussion 4.3.2.1 Performance evaluation of CNFET OPAMP with CMOS OPAMP The performances characteristics and robustness of the proposed CNFET based operational amplifier are examined extensively in terms of the OPAMP circuit specifications, such as open loop gain (Av 0 ), unity gain bandwidth, slew rate (SR), phase margin (PM), common-mode rejection ratio (CMRR), power supply rejection ratio (PSRR), slew rate (SR), output swing (OS) and power consumption. Thus the performance characteristics of the operational amplifier are studied using state-of-the-art 32nm-CMOS and 32nm-CNFET technology. Simulation results show that the proposed CNFET OPAMP circuit achieve high DC gain more than 45dB, high Gain Bandwidth up to 198MHz, phase margin is 48 degrees, the output swing is ±0.9V, settling time is 0.754ns, CMRR is 52.45dB, power supply rejection ratio is 54.35dB and low static power dissipation of 13µW which are shown in Figures 4.5, 4.6, 4.7, 4.8 and 4.9 respectively. Results of the simulation (as shown in Table 4.3) demonstrate that CNFET-based OPAMP have a
133 considerable improvement in terms of settling time and power consumption in comparison with the other conventional state-of-the-art 32-nm CMOS and 32- nm CNFET technology. The results obtained suggest that the carbon nanotube (CNT) OPAMP has a promising potential for low-power, high-speed applications in both analog and mixed-signal nanoelectronic circuits. Figure 4.5 Voltage transfer characteristic of the CNFET OPAMP Figure 4.6 Frequency response of the CNFET OPAMP
134 Figure 4.7 Common mode rejection ratio (CMRR) variation of the CNFET OPAMP with respect to operating frequency Figure 4.8 Power supply rejection ratio (PSRR) variation of the CNFET OPAMP with respect to operating frequency Figure 4.9 Input and output slew rate (SR) of the CNFET OPAMP
135 Table 4.3 OPAMP performance summary and comparisons Parameter 32nm BSIM CMOS OPAMP 32nm CNFET OPAMP DC gain (db) 46.27 49.12-3dB frequency (MHz) 161 198 Phase margin (degree) 44 48 CMRR (db) 43.12 52.45 PSRR (db) 45.69 54.35 Output Swing (OS) ±0.8 ±0.9 Settling time (ns) 52 0.75 Slew Rate (V/µs) 7613.4 5841.2 Output resistance (k ) 56 67 Power dissipation (µw) 45.91 13 4.4 CNFET OPAMP BASED APPLICATION CIRCUITS Operational amplifiers (OPAMPs) are key elements of the analog and mixed signal circuit. Designing high-performance analog integrated circuits is becoming increasingly exigent with the relentless trend toward reduced supply voltages. The DC and AC performance of a CNFET OPAMP has already been analyzed and measured (Usmani & Hasan 2010). There is a need to explore circuit application in new emerging technologies for their rapid commercialization as the CMOS technology is approaching its limits. Carbon Nanotube Field-Effect Transistor (CNFET) is a promising candidate for future electronic devices for low-power low-voltage digital or analog circuit application. There has been a lot of work available in the literature on the digital circuit applications of CNFET but its analog applications have not been explored. In this work, for the first time CNFET operational amplifier (OPAMP) based analog arithmetic computing circuits (such as inverting
136 amplifier, non-inverting amplifier, summer, substractor, differentiator and integrator) has been proposed for their suitability in a wide range of future high performance, low-power analog system applications such as signal processing, remote sensing and portable bio-instrumentation. The proposed computing circuits operation are studied by using HSPICE software for circuit simulation at 0.9V input supply voltage. CNFET OPAMP Based Analog Computing Circuits In this section, the proposed and designed the CNFET operational amplifier (OPAMP) based analog computing circuits such as non-inverting amplifier, inverting amplifier, summer, substractor, differentiator, and integrator. The designed analog computing circuits operate well at the input supply voltage V DD to V SS and room temperature T=30 o C. 4.4.1 CNFET OPAMP based Non-Inverting Amplifier Figure 4.10 (a) shows the circuit diagram of a CNFET OPAMP based non-inverting amplifier. The input voltage V1 is applied to the noninverting terminal of opamp. A voltage divider consisting of resistors R 2 and R 1 connects from the output node to the inverting terminal of opamp. The circuit is called a non-inverting amplifier because its voltage gain is positive. This means that if the input voltage is increasing or going positive, the output voltage will also be increasing or going positive. For the designed noninverting amplifier voltage gain is 3 and the output voltage of the noninverting amplifier is calculated by using the Equation (4.2). V Out V In * 1 R R 2 1 (4.2)
137 V in + - R 1 =4k R 2 =8k Vout V in R 1 =4k R f =8k + - Vout V 2 R 1 =4k V 1 R 2 =4k R f =4k - + V out (a) (b) (c) R 1 =4k V 1 V 2 R 2 =4k R f =4k - + R g =4k V out R f =4k C 1 =10nf V in - + V out V in R 1 =4k C 1 =15nf - + Vout (d) (e) (f) Figure 4.10 CNFET based Analog Computing circuits (a) Non-Inverting Amplifier (b) Inverting Amplifier (c) Summer (d) Substractor (e) Differentiator (f) Integrator 4.4.2 CNFET OPAMP based Inverting Amplifier Figure 4.10 (b) shows the circuit diagram of a CNFET OPAMP based inverting amplifier. The input signal is applied through resistor R1 to the inverting terminal of the opamp. Resistor RF is the feedback resistor which connects from the output to the inverting input. The circuit is called an inverting amplifier because its voltage gain is negative. This means that if the input voltage is increasing or going positive, the output voltage will be decreasing or going negative, and vice versa. The non-inverting input to the op amp is not used in the inverting amplifier circuit. The Figure 4.10 (b) shows this input grounded so that V + = 0. If the circuit diagrams of the inverting and the non-inverting amplifiers are compared, it can be seen that the circuits are the same if V + = 0. Thus the only difference between the two circuits is the node at which the input voltage is applied. For the designed
138 inverting amplifier voltage gain is 2 and the output voltage of the inverting amplifier is calculated by using the Equation (4.3). V Out R 2 VIn * R1 (4.3) 4.4.3 CNFET OPAMP based Inverting Summer The inverting summer is the basic inverting opamp circuit that is used to sum two or more signal voltages. An inverting summer with two inputs is shown in Figure 4.10 (c). For the designed inverting summer voltage gain is 1 and the output voltage of the inverting summer is calculated using the Equation (4.4). The output of the summer is the inversion of the sum of the two input signal. V Out R * V V f R R 1 2 1 2 (4.4) 4.4.4 CNFET OPAMP based Substractor A Differential amplifier with unity gain can be used to provide an output voltage that is equal to the difference of two input voltages. Such a circuit is called a subtractor and is shown in Figure 4.10 (d). This circuit provides an output voltage that is equal to the difference between input voltage V 1 and V 2 applied at the inverting and non-inverting terminal of the opamp. For the designed substractor voltage gain is 1 and the output voltage of the substractor is calculated using the Equation (4.5). V V V (4.5) Out 1 2
139 4.4.5 CNFET OPAMP based Differentiator A differentiator is a circuit which has an output voltage that is proportional to the time derivative of its input voltage. Figure 4.10 (e) gives the circuit diagram of a CNFET opamp based differentiator. The circuit is similar to the inverting amplifier in Figure 4.10 (b) with the exception that resistor R 1 is replaced by capacitor C 1. For the designed differentiator output voltage is calculated by using the Equation (4.6). dvin V RC (4.6) dt Out f 1 4.4.6 CNFET OPAMP based Integrator An integrator is a circuit which has an output voltage that is proportional to the time integral of its input voltage. The circuit for the integrator can be obtained by interchanging the resistor and the capacitor in the differentiator of Figure 4.10 (e). The circuit is shown in Figure 4.10 (f). For the designed integrator output voltage is calculated by using the Equation (4.7). t 1 1 VOut Vin dt RC f (4.7) 4.4.7 CNFET OPAMP based Rectifier Circuit Hall-Wave Rectifier Figure 4.11 (a) shows an ideal half-wave rectifier circuit. During the positive half cycle of the input waveform, the opamp goes positive and turns ON the diode (D 1 ). The circuit then acts as a conventional non-inverting amplifier, and the positive half-cycle waveform appears across the output
140 terminal (V o ). On the other hand, during the negative half cycle of the input waveform, the opamp output goes negative and turns OFF the diode (D 1 ). Since the diode is open, no voltage appears across the output terminal (V o ). The overall result is perfect half-wave rectification, as represented by the transfer characteristic in Figure 4.13 (a). Full Wave Rectifier Figure 4.11 (b) shows an ideal full-wave rectifier circuits. During the positive half cycle of the input waveform at A. The output of opamp A 2 will go positive, mining diode D 2 ON. A virtual short circuit will thus be established between the two input terminals of opamp A 2, and the voltage at the negative-input terminal, which is the output voltage of the circuit, which will become equal to the input. Thus no current will flow through R 1 and R 2, and the voltage at the inverting input of opamp A 1 will be equal to the input and hence positive. Therefore the output terminal (F) of opamp A 1 will go negative until A 1 saturates. This causes D 1 to be turned OFF. Next consider during the negative half cycle of the input waveform at A. The tendency for a negative voltage at the negative input of opamp A 1, causes F to rise, making diode D 1 conduct. Thus a virtual ground appears at the negative input of A l and the two equal resistances R 1 and R 2 force the voltage at C, which is the output voltage, to be equal to the negative of the input voltage at A and thus positive. The combination of positive voltage at C and negative voltage at A causes the output of A 2 to saturate in the negative direction, thus keeping D 2 OFF. The overall result is perfect full-wave rectification, as represented by the transfer characteristic in Figure 4.13 (b). This precision is, of course, a result of placing the diodes in opamp feedback loops, thus masking their nonidealities. This circuit is one of many possible precision full-wave rectifier or absolute-value circuits.
141 (a) (b) (c) (d) (e) (f) Figure 4.11 CNFET OPAMP based Analog Signal Processing Circuits (a) Half-wave Rectifier (b) Full-wave Rectifier (c) Clamper (d) Clipper (e) Comparator (f) Peak Detector 4.4.8 CNFET OPAMP based Clamper Circuit In clamper circuits, a predetermined DC level is added to the input voltage. In other words, the output is clamped to a desired DC level. If the clamped DC level is positive, the clamper is called a positive clamper. On the other hand, if the clamped DC level is negative, it is called a negative
142 clamper. The other equivalent terms for clamper are DC inserter or DC restorer. A clamper circuit with a variable DC level is shown in Figure 4.11 (c). Here the input wave form is clamped at +V ref and hence the circuit is called a positive clamper. The output voltage of the clamper is a net result of AC and DC input voltages applied to the inverting and non-inverting input terminals respectively. Therefore, to understand the circuit operation, each input must be considered separately. First, consider V ref at the non-inverting input. Since this voltage is positive, the output voltage (V o ) is also positive, which forward biases diode D1. This closes the feedback loop and the op-amp operates as a voltage follower. This is possible because C 1 is an open circuit for DC voltage. Therefore V o = V ref. The voltage V in at the inverting input is concerned during its negative half-cycle D1 conducts and charging C 1 to the negative peak value of the voltage (V P ). However, during the positive halfcycle of V in diode D 1 is reverse biased and hence the peak voltage (V P ) across the capacitor acquired during the negative half-cycle is retained. Since this voltage V P is in series with the positive peak voltage VP, the output peak voltage V O = 2V P. Thus the net output is V o = V ref + V P, so the negative peak of 2V Pb is at V ref. The input and output wave forms are shown in Figure 4.13 (c) 4.4.9 CNFET OPAMP based Clipper Circuit Clipper is a circuit that is used to clip off (remove) a certain portion of the input signal to obtain a desired output wave shape. In op-amp clipper circuits, a rectified diode may be used to clip off certain parts of the input signal. Figure 4.11 (d) shows an active positive clipper, a circuit that removes positive parts of the input signal. The clipping level is determined by the reference voltage V ref. When the V ref is ZERO and the non-inverting input is grounded. When V in goes positive, the error voltage drives the op-amp output negative and turns ON the diode. This means the final output V O is ZERO
143 (same as V ref ) for any positive value of V in. When V in goes negative, the opamp output is positive, which turns OFF the diode and opens the loop. When this happens, the final output V O is free to follow the negative half cycle of the input voltage. This is why the negative half cycle appears at the output. To change the clipping level, all we do is adjust V ref as needed. 4.4.10 CNFET OPAMP based Comparator Circuit A comparator, as its name implies, compares a signal voltage on one input of op-amp with a known voltage called the reference voltage on the other input. Figure 4.11 (e) shows an opamp comparator used as a voltage level detector. Consider a fixed reference voltage V ref of +0.3V which is applied to the inverting input and the other time varying signal voltage Vin is applied to the non-inverting input. Because of this arrangement, the circuit is of non-inverting type. When V in is less than V ref, the output voltage Vo is Vsat because the voltage at the inverting input is higher than Vin is greater than non-inverting input. On the other hand, when V in is greater than V ref, Vo goes to +V sat. This V o changes from one level to another level whenever V in =V ref as shown in Figure 4.11 (e). At any given time, the circuit shows whether V in is greater than or less than V ref. The circuit is hence called a Voltage level detector. The comparators are interface circuits between analog and digital domains, converting a continuous linear analog signal into a twostate digital signal. Comparators are used in circuits such as Digital interfacing, Schmitt triggers, Discriminators, Voltage level detectors, Oscillators, etc. 4.4.11 CNFET OPAMP based Peak Detector Circuit Square, saw-tooth, pulse waves and triangular are typical examples of non-sinusoidal wave forms. A conventional AC voltmeter cannot be used to measure the RMS value of the pure sine wave. One possible solution for
144 this problem is to measure the peak values of the non-sinusoidal wave forms. Figure 4.11 (f) shows a peak detector that measures the positive peak values of the input. During the positive half-cycle of the input wave form V in, the output of the opamp drives diode D 1 ON charging capacitor C 1 to the positive peak value V P of the input voltage Vin. Thus when diode D1 is forward biased, the op-amp acts as a voltage follower. On the other hand, during the negative half-cycle of the input wave form V in, the diode D 1 is reverse biased, and the voltage across C 1 is retained. The only discharge path for C 1 is through output terminal V o. 4.5 RESULT AND DISCUSSION The simulation result of the proposed CNFET based analog computing circuits such as non-inverting amplifier, inverting amplifier, summer, substractor, differentiator, Integrator, half-wave rectifier, full-wave rectifier, clamper, clipper, comparator and peak detector are presented in the Figure 4.12 and Figure 4.13. The performance of the proposed CNFET technology based analog computing circuits are compared with 32nm CMOS technology based analog computing circuits in term of power consumption. The proposed and conventional analog computing circuit s power consumption are shown in Table 4.4. Thus the proposed analog computing circuit characteristics are studied using state-of-the-art 32nm CNFET technology. Simulation results show that the proposed computing circuits well suited for low-power low-voltage signal processing application for their lower power consumption. The conventional 32nm CMOS technology based analog computing circuits and its power consumption are also shown in Table 4.4.
145 Table 4.4 Power consumption of the CNFET OPAMP basedanalog computing and signal processing circuits 32nm CMOS 32nm CNFET Technology Technology Analog Computing Power Power Circuits Consumption Consumption (µw) (µw) Non-Inverting Amplifier 696 55.55 Inverting Amplifier 789 58.96 Summer 821 61.18 Substractor 1073 60.23 Differentiator 1290 59.94 Integrator 1342 59.40 Half-wave Rectifier 1256 42.44 Full-wave Rectifier 1421 78.09 Clamper 969 20.80 Clipper 1011 50.82 Comparator 893 38.96 Peak Detector 1103 50.60 Figure 4.12 Simulation output of the CNFET based analog computing circuits (a) Non-Inverting amplifier (b) Inverting amplifier (c) Summer (d) Substractor (e) Differentiator (f) Integrator
146 Figure 4.13 Simulation output of the CNFET OPAMP based analog signal processing circuits (a) Half-wave rectifier (b) Fullwave rectifier (c) Clamper (d) Clipper (e) Comparator (f) Peak detector 4.6 SUMMARY The first section, explores the advantages offered by newly emerging CNFET technology over the existing CMOS technology in analog circuits. The Opamp performance depending on the choice of the diameter of
147 the CNT, which play an important role on the design. With CNFET technology, we obtain the high DC gain, high unity gain bandwidth, minimum settling time and power dissipation. The proposed Op-Amp is suitable for high frequency applications. We demonstrated that it is possible to minimize the power consumption in the CNFET version, taking advantage of the promising electrical characteristics of this type of device. In the second section, A low-power, low-voltage CNFET operational amplifier (OPAMP) based analog arithmetic computing circuit such as inverting amplifier, non-inverting amplifier, summer, substractor, differentiator, integrator, half-wave rectifier, full-wave rectifier, clamper, clipper, comparator and peak detector for analog signal processing application are discussed. Proposed circuits are simple and much efficient than that their conventional CMOS based circuits especially for low-power analog circuit application. From the simulation result, an analog circuit application aspects of CNFET is a promising nano device. The major contribution of this work is the direct comparison between emerging technologies, demonstrating that CNFET are candidates to compete with the well-established CMOS devices for the implementation of low-power analog circuits when nanotube fabrication challenges will be surpassed, such as yield and mismatch among them. The CNFET motivates future works in the field of nano computing and analog mixed signal integrated circuit application. Moreover, as a future scope of this work, more complex circuits could be investigated along with their hybrids and other nanoscale alternatives could also be taken up for performance comparison to explore their capabilities for future analog and mixed-signal designs along with some demonstrated fabrication experiments.