n mproved ctve Front End on- egeneratve ectfer ystem Employng a Fve-mb nductor ahesh wamy, rves esearch and evelopment Chef Engneer, Yaskawa merca, nc., ember, EEE teven chfko, rves Product Engneer, Yaskawa merca, nc., ember, EEE bstract Varable frequency drves (VFs) draw dscontnuous current from the power system resultng n current dstorton and consequently voltage dstorton. mtng current dstorton to levels recommended n EEE 519-199 mproves system effcency, ncreases relablty, and lmts voltage dstorton that can adversely nfluence senstve loads. hs paper revsts a non regeneratve actve front end system that has been studed n the past but offers sgnfcant mprovements to make t acceptable to the drves ndustry. three-phase current njectng nductor, requred n the topology, s constructed n a fve fashon and s shown to be helpful n lmtng non characterstc harmoncs. nce the current njected nto the splt dc bus capactor s a 60Hz rpple, t s proposed that the man dc bus capactor be splt nto flm capactor for rpple current and optmally reduced electrolytc capactor for the man energy storage requrements. Expermental results are gven based on the suggested mprovement and low dstorton levels that were not acheved n the past have been shown to be attanable. Comparson between a standard three- nductor and a fve- nductor s made to hghlght the performance mprovements achevable. dopton of the topology for common dc bus applcatons s also proposed. ndex erms ctve Harmonc Flter, Fve- nductor, Harmonc tgaton, on-regeneratve ctve Flter.. UC here are many technques, both passve and actve, that are employed to mprove the nput power factor of a VF and reduce the overall current harmoncs. he actve technques have an advantage over the passve technques n sze and performance. he cost of certan type of actve technques can be hgher than passve technque. hs paper proposes mprovements to a low cost actve crcut that was reported n 1997 []. he basc crcut s shown n Fg. 1 and employs bdrectonal swtches that are rated to handle the harmonc compensaton current only, whch s about 5% of the rated current of the VF. he crcut of Fg. 1 does not support regeneraton. nce most HVC applcatons do not need regeneraton, bulky and expensve four quadrant converters are not needed. he topology shown n Fg. 1 s a three-phase boost converter that forces current conducton n phases that do not carry current durng a typcal sx-pulse operaton. he boost converter requres a boost nductor and snce t s swtched at twce the supply frequency, t s large n sze, but there s no concern of addtonal conducted E. B C (a) 1 5 4 6 B C C C C (b) Fg. 1: on regeneratve actve front end crcut. (a) rgnal crcut; (b) odfed crcut []., B, and C are bdrectonal swtches. Fg. 1(a) shows the orgnal method that needed access to the neutral of nput ac source. By splttng the dc bus to create a mdpont, the orgnal crcut was modfed [] to the one shown n Fg. 1(b). hs allows the mplementaton of the actve flter crcut wthout the need to access the neutral of the ac source. he topology shown n Fg. 1(b) s very smlar to the popular Venna ectfer []. nce the swtches n Fg. 1 are rated to handle only the harmonc current, t s easy to scale ths topology for large power applcatons. Bdrectonal conducton can be obtaned by usng four dodes and an GB or two GBs confgured n seres wth common emtter or common collector; or one could use two ant-parallel reverse blockng GBs. From a swtch loss pont of vew, four dodes and a swtch opton s the worst whle usng reverse blockng GBs s the best.
. PCPE F PE t s well known that there are sx dstnct dode pars that conduct n one electrcal cycle n a typcal phase ac to dc rectfer. Each conducton nterval nvolves one par of dodes and lasts 60 electrcal degrees, whch means that one phase does not conduct every 60 electrcal degrees. ypcal rectfer nput waveforms are shown n Fg.. ph. C C bus voltage Phase voltage 6 1 1 1 5 4 ectfer nput current 4 6 4 5 C C Fg. : sx pulse ac to dc rectfer system wth ts assocated voltage and current waveforms. By employng a swtch, current can be forced through the non conductng phase nto the mdpont of the dc bus. o store energy durng ths perod, nductors are employed. he current through the non conductng phase s mantaned untl ts turn to naturally conduct occurs. t that pont, the swtch s turned FF. urnng FF of the swtch causes the energy n the nductor to be transferred to the dc bus smlar to a boost converter. By turnng and FF the swtch at the approprate tme (Fg. ), contnuous current can be mantaned n all the phases. V g V gc V gb 6 1 1. fferent odes of peraton n ths subsecton the operatng modes of the crcut shown n Fg. 1(b) are dscussed, concentratng on one half of the electrcal cycle of phase. 0 to 0 n Fg. 1(b), s the lne-neutral voltage correspondng to phase. he swtch connected to the nductor n phase s turned at 0. t remans for a maxmum duraton of 0 at whch pont, t s turned FF. urng the perod, the nductor of phase s connected to the md-pont of the dc bus formed by the splt capactors. hs nterval s shown n Fg. 4(a). Current ncreases n a co-snusodal manner through the nductor. urng ths nterval, t s also assumed that dodes 5 and 6 are conductng. hey reman n conducton durng ths nterval. 0 to 60 t the end of the frst nterval, swtch s turned FF and due to the nductance n the crcut, the current forward bases the dode connectng nductor to the postve of the dc bus as shown n Fg. 4(b). urng ths nterval, dode 1 starts conductng brngng the total number of dodes n conducton from two to three. Current contnues to flow through phase. 60 to 90 urng ths nterval, dode stops conductng snce swtch C n phase C s turned per the sequence shown n Fg.. Current n Phase C reverses snce the mdpont voltage s hgher than the nstantaneous voltage of Phase C. Current contnues to flow through Phase and returns va Phase B. Fg. 4(c) s the equvalent crcut durng ths nterval. 90 to10 t the end of the prevous nterval, swtch C s turned FF. nce current through the nductor cannot be stopped abruptly, dode connectng the nductor to the negatve bus gets forward based and allows current to reman flowng through Phase C. Currents n Phases and B contnue to flow. hree dodes conduct n ths nterval Fg. 4(d). 10 to150 From Fg., t s seen that durng ths tme nterval, swtch B connectng Phase B to the mdpont of the dc bus capactor needs to be turned. hs turns FF dode 6. Current n Phase B changes ts drecton snce the voltage of Phase B s hgher than the mdpont of the dc bus capactor. urng ths nterval, there are two dodes and one swtch conductng, as shown n Fg. 4(e). Current n Phase contnues to flow. 150 to180 wtch B connectng Phase B to the mdpont of the dc bus capactor turns FF at the begnnng of ths nterval. ue to nductance n the crcut, current n Phase B contnues to flow as dode gets forward based and connects nductor to the postve of the dc bus as shown n Fg. 4(f). Current n phase s now wanng and s ready to change drecton n the next nterval. he voltage stress across the swtch s dscussed later. t s shown that the stress across the swtch depends on how the dc bus mdpont s confgured. Fg. : wtchng nstances for the swtches n Fg. 1(b) [].
5 1 B C 6 C C C (a) (f) Fg. 4: equence of events durng one half of the electrcal cycle nvolvng phase. C C C 1 5 6 (b) 1 6 (c) 1 6 (d) C C C C C B. nductor esgn he nductor s desgned for rated current condton. By selectng the nductor approprately, the current at the end of the swtch conductng perod s made equal to about one-half of the peak value of the rated current m /. hs sets up the desgn equaton for the nductor. urng the 0 to 0 nterval, t can be seen that voltage of pont n Fg 4(a) s same as the voltage of the neutral pont, snce s connected to the postve bus and s connected to the negatve bus. he equaton for current flow through durng ths nterval s derved next. t wll help n determnng the value of nductor. nductors,, and are assumed to have the same nductance value. V m s the peak lne-neutral voltage. d v dt t v V sn( ) dt m d 0 0 V m (1 cos( )) t m 0, the value of nductor current s V m (1 ) P o V m (1 V m V m (1 P o ) ) assumed to reach m / C (e) 1 B C Z pu (0.1) 0.66 Z pu. PPE PVEE. Fve mb nductor pton From equaton (1), t s seen that the nput nductor s large and s predcted to occupy much space. ngle phase nductors are preferred over three-phase nductor snce the sngle-phase nductors offer common mode mpedance and (1)
any preexstng mbalance n the source voltage wll not create undue non-characterstc current harmoncs. However, snglephase nductors occupy more space and the cost of three sngle-phase nductors s typcally hgher than the cost of one three-phase nductor. Gven ths fact, t s dffcult to justfy use of three sngle-phase nductors. However, as a compromse, a fve- nductor s proposed to be used here. fve- nductor offers common mode mpedance and can help reduce the nfluence of pre-exstng voltage mbalance on the current harmoncs flowng through the system. n a typcal three- nductor, the thrd harmonc flux cancels out and no thrd harmonc flux crculates n the core. n other words, t can be sad that a typcal three- nductor offers hgh reluctance to thrd harmonc flux. he hgh reluctance to thrd harmonc flux pushes the flux pattern more towards the fundamental. he slght ncrease n fundamental flux creates a hgher ffth and seventh harmonc current when such nductors are used n a typcal phase ac to dc rectfer crcuts. n other words, usng a standard three- nductor can cause hgher ffth and seventh harmonc current to flow due to pre-exstng thrd harmonc voltage n the ac system. he pre-exstng thrd harmonc voltage s typcally due to preexstng phase voltage mbalance. f the nductor has a fve core, the thrd harmonc flux wll exst n the core snce t has a path to flow. he flow of thrd harmonc current wll nfluence the fundamental voltage n a way to reduce ts value. he slght reducton n the fundamental voltage wll reduce the ffth and seventh harmonc currents n the system when ths nductor s used n front of a three-phase ac to dc rectfer crcut. By desgnng the reluctance of the path for the thrd harmonc flux n an optmal manner, t s possble to sgnfcantly reduce the ffth and seventh harmonc fluxes n the core. Fg. 5 shows how the thrd harmonc flux does not exst n a three- nductor and how a path can be provded for ths flux n a fve nductor. Expermental results shown later prove the beneft of usng a fve nductor n ths topology. B. eparaton of pple Current Capactor from Electrolytc Capactor From the dscussons n ecton on the operatng modes, t s well understood that durng the operaton of the swtch, a rpple current flows nto and out of the dc bus mdpont. he current flows sx tmes back and forth nto and out of the dc bus mdpont. he 180Hz rpple current wll have peak ampltude of one-half of the rated maxmum current, as shown n equaton (1). he current shape s shown n Fg. 6 and the rms value of the capactor rpple current s derved next. From Fg. 6, the capactor current can be defned as follows: C 0 m m 0 sn( ) sn( ) 0 / 6 / 6 / / / / / () =f / f -phase f / f / f / f =0 f / f / -phase -phase f / f / (a) f f / f / -phase =0 f f (b) -phase f / f / f f / f / f / f / -phase =0 Fg. 5: a. hree- nductor wth no thrd harmonc flux; b. Fve nductor wth thrd harmonc flux n the s and yokes. ue to half-wave symmetry, the rms capactor current can be computed as follows: 0.08 0.9 m n( rms) C1 C 0.6 0.4 0. 0-0. -0.4-0.6 / 6 sn ( ) d m 0 / 6 m (1 cos( ) d 0 m sn( / ) 6 0.1 n( rms) (cap) (pu) 0 90 180 70 60 Fg. 6: heoretcal current flowng nto the dc bus mdpont. () =f /
From (), t s clear that the dc bus mdpont capactors need to handle sgnfcant amount of rpple current. ypcal electrolytc capactors used n VFs do not have hgh rpple current carryng capacty. n order to provde the necessary rpple current, many electrolytc capactors need to be used n parallel. he use of multple electrolytc capactors across the dc bus ncreases the sze and cost of VFs. o allevate ths problem, t s proposed to separate the rpple handlng capactors from the bulk dc bus electrolytc capactors. hs would optmze the dc bus structure and reduce cost sgnfcantly. By separatng the rpple handlng capactors from the bulk electrolytc capactors, the voltage stress across the swtches,, B, and C s greatly altered. he stress across the swtches s dscussed next. f the dc bus mdpont was formed usng bg bulky electrolytc capactors, the voltage across swtch would vary from close to zero when t s, to V C / when t s FF. However, due to the proposed separaton of flter capactor from the bulk electrolytc capactors, the voltage across s no longer stff snce the mdpont voltage moves dependng on whether the mdpont s beng charged or dscharged. urng the frst nterval (Fg. 4(a)), swtch s and so the voltage across t s the on-state drop across the GB plus the conductng dode forward voltage drop. he total voltage s low across the conductng swtch. t the end of the frst nterval, swtch s turned FF. nce the current through nductor cannot stop flowng mmedately, dode 1 gets forward based and the nductor gets pulled up to the postve dc bus. he collector of comes close to V C but snce the mdpont gets dsconnected from all the phases, the mdpont voltage s held at the value t had at the end of the frst nterval. hs voltage s close to V m / where V m s the maxmum value of the lne-neutral voltage. V m can be expressed n terms of V C as follows: V C V m V m 0.604 V C Hence, voltage across at the end of nterval 1 s close to V m / or 0.V C. t the end of the second nterval, swtch C turns and the mdpont dscharges nto phase C. he voltage across swtch ncreases snce the collector of s stll connected to nductor. he voltage across ncreases n a quas snusodal manner from V m / to V m / or from 0.V C to 0.9V C (v -v C at = 90 o ) as expermental results show. urng the 90 o to 10 o nterval, the mdpont gets dsconnected from the swtches and s nether beng charged nor dscharged. he voltage across remans at the value that s had at the end of the prevous nterval 0.9V C. From 10 o to 150 o, the mdpont gets charged from phase B snce swtch B turns. he voltage across swtch starts (4) fallng down snce mdpont voltage moves up along wth phase B voltage, v B. he voltage across swtch moves down from an ntal value of 0.9V C, followng a path carved by v -v B. he fnal voltage across swtch s thus computed to be (V m /- ()V m /) or 0.8V C. Fnally, from 150 o to 180 o, the mdpont remans dsconnected from all the three phases and so the voltage across swtch remans at 0.8V C. n the subsequent nterval, the voltage across s close to zero snce swtch turns to dscharge the mdpont voltage nto phase. C. daptng to elta Connected ource ll the explanatons ncludng the varous ntervals of operaton have been explaned assumng that the source s connected n a wye confguraton wth a floatng neutral. n many ndustral applcatons, the source can be connected n delta. hs would requre the logc controller to accommodate the desred phase shft. low cost method to acheve the desred phase shft of 0 electrcal degrees s proposed here. For a gven operatng condton f the conducton angle s wth the nput confgured n wye, then t wll need to be 0+ when the nput s confgured n delta. o accommodate ths, a hgh mpedance resstor network confgured n wye s used. he phase to neutral voltage out of the phase resstor network s used as the reference voltage for zero crossng. hs phase shfted voltage reference yelds the desred 0 degrees phase shfted needed to accommodate ac sources confgured n delta. f the nput s already confgured n wye, the output from the resstor network does not undergo any phase shft and so the resstor network can reman rrespectve of the confguraton of the nput ac source. he vector representaton of the delta system and the correspondng phase shft acheved usng a wye confgured resstor network s shown n Fg. 7. Fg. 7: Phase shftng scheme to acheve the desred 0 degree phase shft to accommodate delta connected source usng a wye connected resstor network.. Change n locaton of Current ensor he orgnal topology dscussed n [4] uses a current sensor n the dc bus to allow for power control. However, the emphass n the modfed topology s towards dc bus voltage control rather than dc bus power control. hs change n strategy s geared towards the man objectve of usng the actve front end topology for VF loads fed from a regulated dc voltage. he VF tself s typcally equpped wth sophstcated algorthms to control speed and torque n ac motors and so the actve front end converter need not be -0 o
burdened wth power control. t s thus proposed here to remove the current sensor from the dc bus and use a current sensor to sense the dc bus mdpont current to protect the swtches due to abnormal operatng condton. Hence, the rpple current nto the mdpont of the dc bus capactor s montored and s used as a protecton feature to reduce n cases where the current exceeds the desgned maxmum value. By changng the current montorng locaton and ts purpose from regulaton to protecton, the ratng and cost of the current sensor s sgnfcantly reduced. E. Use of opology n Common dc Bus pplcatons By separatng the rpple carryng capactor from the man electrolytc capactors and by changng the role of the current sensor from power control to protecton whch facltated ts move from dc lnk to dc bus mdpont, t s possble to have an actve front end topology that has three phase ac as nput and a regulated dc bus voltage as the output. hs proposal helps n optmzng the sze and cost of the actve front end system to make t power multple VFs on a common dc bus. uch a topologcal modfcaton s shown n Fg. 8. V. E EU ll of the mprovements suggested above have been adopted n the unt tested. he schematc of the test setup s shown n Fg, 9. he components used are lsted below.. Components Used 1. n = 0.64mH, 171rms, a. nductor; b. nductor. C1~C4= 0F, 700Vdc (Flter Capactors). CC: HC-45V4B15 (45 = 4V) (lower current ratng than old method) 4. U1~U: ctve wtch modules Q115001-E (Custom odule from Powerex 150, 1) 5. nubber Capactors (not shown n Fg. 9) rated at 0.F, 600Vdc across U1, U, and U are employed. B. est Plan and est esults system rated at 40V, 75hp was bult and was tested at varous power condtons. he test setup s shown n Fg. 9. Followng tests were conducted:. 75hp rated system was tested at 8hp load correspondng to approxmately 50% power; B. 75hp rated system was tested at 56hp load correspondng to approxmately 75% power; and C. 75hp rated system was tested at 75hp load correspondng to 100% power; t the test ponts, the nput current and voltage H were measured. he dc bus voltage regulaton was also montored. he dc bus was regulated to be at about 16Vdc. est results are shown n Fgs. 10 and 11. he results are tabulated n ables 1 and, where s defned as the rato of harmonc current to the EC rated current for the C motor. VF 1 1 C1 + C C C otor ph, C source phase reactors Current ensor C + _ V C ctve wtch Controller _ C C VF C otor rpple Conducton ngle, -0 tandalone and mproved ctve Front End ectfer ystem = es. network C C VF n C otor Fg. 8: chematc of proposed crcut for common dc bus mplementaton.
40Vac, ph, 60Hz n n 1 V C 0V, 75hp 460V, 50hp G phase reactors CC 11 1 1 C1~C4 0V, 45kW VF (test motor) oad motor From 1- Gr Er Gs Es Gt Et wtch V C EX-on CVE FE CE U1 U U V Gr Er Gs Es Gt Et es. etwork Fg. 9: est crcut setup. able 1: Harmonc data for the 40V, 75hp, non regeneratve actve front end converter system oad 5 7 9 11 1 17 () () () () () () () () (hp) 8 77.5 79.1 5.6 1.7 7. 4.1 4.9.1 0.8 0.8.1 4.6 0..7 1. 0.5 56 117.8 115.4.6 1.1 6.6 4.4 5.6. 1. 1.1.6 4.7 0..7 1.9 0.4 75 154. 15. 1.6 1.0 5.1 4.6.4 4.1 1.6 0.6..7 0.8 1.1 1.1 1.0 able : ummary block of harmonc data for the 40V, 75hp, non regeneratve actve front end converter system EC ated mps= 19 (used for computng ) oad (hp) V (V) Voltage H (%) Current H% (%) 8 10.7 16.1 1.5 1. 14. (5.7) 9.9 (4.1) 56 10. 15.8 1.4 1. 8.4 (5.1) 7.0 (4.) 75 19.4 14.0 1.7 1. 4.9 (.9) 4.9 (.9)
VG VG VG V V 00 00 00 V V V V (a) 8hp (b) 56hp (c) 75hp Fg. 10: est results at the three dfferent operatng power levels employng tradtonal boost nductor 00 00 00 V V G V V G V G V V V V (a) 8hp (b) 56hp (c) 75hp Fg. 11: est results at the three dfferent operatng power levels employng the custom boost nductor C. Power oss Comparson he effect of usng a fve- structure to crculate the thrd order harmoncs through the core can be observed n the power loss measurements. Expermental loss measurements are gven here that show that the power loss ncreases when the fve structure s used manly because of the hgher core loss. hough core loss was not specfcally measured, everythng remanng the same, one can say that the hgher observed loss s prmarly due to harmonc flux n the core. able shows the loss results. P shaft 8hp (8.5kW) 56hp (41.77kW) 75hp (55.95kW) able : ystem effcency test results Pn for Pn for ystem eff. for ystem eff. for 0.45kW.19kW 9.1% 88.1% 46.76kW 47.15kW 89.% 88.6% 60.0kW 6.51kW 9.% 89.5% V. CCU From the dscussons above, the followng mportant conclusons are made: he fve- nductor s seen to perform well and s shown to reduce thrd order harmoncs; eparatng the flter capactor from the electrolytc capactors reduced the man dc capactors by % ; he nductance used s 0.64mH - 0.87pu. he new current sensor locaton does not nterfere wth the operaton of the crcut. ensor ratng s lower and so s less expensve; he proposed wye connected resstve voltage sensor network s seen to create the proper phase shft; he nput current at rated load condton s seen to be about 155, whch s much less than the E ratng. hs s because of the mproved power factor. ower value of nput rms current sgnfcantly reduces loss n the power system, whch s a prmary motvaton for actve flterng; Power measurement shows that the fve- structure ncurs more loss than the tradtonal structure. hs s prmarly due to hgher core loss n the fve structure snce the core n the fve structure has to handle the thrd order harmonc flux. EFEECE [1] EEE ecommended Practces and equrements for Harmonc Control n Electrcal Power ystems, EEE td. 519-199. [] Evaldo.. ehl, and vo Barb, n mproved Hgh-Power Factor and ow Cost hree Phase ectfer, EEE rans. on ndustry pplcatons, Vo., o., arch/prl 1997, pp: 4849. [] J.W. Kolar, H. Ertl, F.C. Zach, "esgn and Expermental nvestgaton of a hree-phase Hgh Power ensty Hgh Effcency Unty Power Factor PW (VE)ectfer Employng a ovel ntegrated Power emconductor odule", 11th nnual PEC Conference Proceedngs, Vol., pp.514-5, 1996. [4] l. aswood, and Fangru u, ovel Unty Power Factor nput tage for C rve pplcatons, EEE rans. on Power Electroncs, Vol. 0, o. 4, July 005, pp: 89-846. [5] ahesh wamy, hree Phase ctve ectfer ystem, UP pplcaton: 1/47,097, 10 January 01.