Analogue Integration AISC11 High Voltage and Temperature Auto Zero Op-Amp Cell Rev.1 12-1-5 Features High Voltage Operation: 4.5-3 V Precision, Auto-Zeroed Input Vos High Temperature Operation Low Quiescent Supply Current: 24 µa typ Gain-Bandwidth Product: 1.1 MHz Slew rate: 1.2 V/µs Applications Sensor Interface Strain Gauge Signal Conditioning Precision Instrumentation Process Technology XFAB CX8H High voltage CMOS.8 µ Product Description Introduction Analogue Integration's 'off the peg' analogue cells provide a quick and complete solution for mixed signal and analogue IC designs. Cells are fully simulated and characterised for the target semiconductor process and have a track record of use in existing designs. Once a customer has reviewed a cell's datasheet and determined its suitability for their design, a full schematic, netlist and layout in the target process can be down loaded upon payment of a one-off fee. AISC11 Precision Auto-zero Op-Amp Cell This Op-Amp cell periodically auto-zeros its offset voltage while processing signals in continuous time. To do this the cell comprises two amplifiers, a main amplifier which continuously amplifies the input signal and a nulling amplifier which on alternate phases of a clock signal nulls its own input offset and that of the main amplifier. The cell is designed for high voltage and high temperature operation. The cell requires an externally supplied clock signal and a bias current sink of 16 µa. As this cell is intended to be embedded into a larger design no ESD cells are provided. Simulation Data The rest of this datasheet contains AISP11 cell's characteristics obtained from SPICE simulation. Unless otherwise stated these simulations were conducted under the conditions of nominal process parameters and at a temperature of 27 o C. Process Technology AISC11 is initially available characterised for XFAB CX8HV.8 µ CMOS technology. Other technologies can be offered upon request. Absolute Maximum Ratings Parameter Unit Rating Supply voltage VDD V -.3 to 5.5 Supply voltage VDDHV V -.3 to 3 Control voltages V -.3 to 5.5 Operating Temperature o C - 4 to + 15 Operating Conditions Parameter Min Typ. Max Unit Supply voltage VDD 4.5 5 5.5 V Supply voltage VDDHV 4.5 15 3 V Clock frequency 32 khz Block Diagram VINP VINN IBIAS CLK VDD + _ VDDHV AVSS VOUT Analogue Integration Ltd., The Old Village, Store Corston, Malmesbury, Wiltshire, SN16 HJ, UK Tel. +44 ()1666 82329 Fax. +44 ()1666 825154 Email Sales@analog.co.uk Web http://www.analog.co.uk 25 Analogue Integration Ltd 1
AISC11 Functional Description Vinn Vinp Main Amp. Primary Vout1 Vout S1d S1c Aux. Vref S1a S1b S2c Nulling Amp. Primary Vout2 Aux. S2b S2a C m C mr S2d Vref C n 1/f CLK Clock-in Non-overlapping Clock Closed Open t Figure 1 AISC11 cell is an Op-Amp with a main amplifier that continuously amplifies the input signal while a nulling amplifier, operating on alternate phases of the clock signal, first zeros its own input offset voltage and then that of the main amplifier. The blocks comprising this auto-zero Op-Amp cell, figure 1, are a main amplifier, a nulling amplifier, CMOS switches, sampling capacitors and a non-overlapping clock generator. The inputs that need to be provided externally are a bias current sink of 16 µa, a voltage reference of half supply voltage and a clock input. The nulling amplifier is folded cascode differential stage with two input stages, a primary input PMOS differential pair and an auxiliary input NMOS differential pair. The primary input amplifies a differential signal in the usual way. The auxiliary input drives a circuit in the sources of the primary differential amplifier which compensates for the inherent input offset voltage of the primary input. This offset may be due to process or temperature variation. The main amplifier has the same primary and auxiliary inputs circuit as the nulling amplifier with the addition of an inverting output buffer. The clock input drives a non-overlapping two phase clock generator as shown in figure1. During the first phase,, of the auto-zero cycle the nulling amplifier zeros its own input offset voltage. The switches driven from shown in figure 1 are closed. S1a shorts the primary inputs of the nulling amplifier and S2a closes a negative feedback loop from Vout2 to the auxiliary inputs inverting input, the non-inverting input is fed from a half supply voltage reference source via S2c. Feedback action reduces offset at the primary inputs to zero. The zeroing voltage at the auxiliary inverting input is held on capacitor Cn. This maintains the zeroing voltage when switch S2a is open during the second half of the autozero cycle. A capacitor Cnr similarly holds the reference voltage, this is used to balance the errors that occur on Cn due to charge injection when switching. Analogue Integration Ltd., The Old Village, Store Corston, Malmesbury, Wiltshire, SN16 HJ, UK Tel. +44 ()1666 82329 Fax. +44 ()1666 825154 Email Sales@analog.co.uk Web http://www.analog.co.uk 25 Analogue Integration Ltd 2
AISC11 During the second,, phase of the auto-zero cycle, when switches S1b, S2b and S2c closed, a feedback loop is formed from the main amplifier primary input, through the primary input of the nulling amplifier to the auxiliary input of the main amplifier. The nulling amplifier, which has had its offset zeroed during phase, amplifies the main amplifiers offset to drive the main amplifiers auxiliary input to bring this offset to zero. The voltage that drives the main amplifier auxiliary inverting input is stored on capacitor Cm and holds this value during the phase. As with the nulling amplifier, the reference voltage to the main auxiliary non-inverting input is switched by S2d and stored on Cmr to balance switching errors at the inverting input. At high temperature the leakage current from the source and drain regions to bulk of the CMOS switches start to become significant at the input of the Op-Amp. As the AISC11 cell will be most commonly used in applications with resistive sensors such as strain gauge bridges, low input offset current is more important than low input current. For this reason switches S1c & S1d have been added to balanced switches S1a and S1b and give a low offset input current which does not alter with auto-zero phase. Analogue Integration Ltd., The Old Village, Store Corston, Malmesbury, Wiltshire, SN16 HJ, UK Tel. +44 ()1666 82329 Fax. +44 ()1666 825154 Email Sales@analog.co.uk Web http://www.analog.co.uk 25 Analogue Integration Ltd 3
AISC11 Electrical Characteristics Symbol Parameter Conditions Min Typ Unit DC Characteristics V DD = 5 V, V DDHV = 15 V, f CLK = 31.25 khz, No Load (except feedback resistors = 48.4 kω), unless otherwise stated. CMRR Common mode rejection 112 db ratio +PSRR Positive power supply @1 Hz 173.8 db rejection ratio -PSRR Negative power supply @ 1 Hz 167 db rejection ratio V CM Input common mode 4.187 V voltage range A V Large signal voltage gain Main Amplifier, No Load. 124 db Main + Null Amplfiers, No Load. 173 db Main Amplfier, 1 kω load. 11.4 db Main + Null Amplfiers, 1 kω load. 159.4 db V O Output swing 1 V DD = 5 V, V DDHV = 1 V, No Load. 9.99 V pp V DD = 5 V, V DDHV = 1 V,1 kω to V SS 9.76 V pp V DD = 5 V, V DDHV = 5 V, No Load. 4.99 V pp V DD = 5 V, V DDHV = 5 V,1 kω to V SS 4.85 V pp I SC Output short circuit V DD = 5 V, V DDHV = 15 V, Sourcing 66 ma current V DD = 5 V, V DDHV = 15 V, Sinking.69 ma V DD = 5 V, V DDHV = 5 V, Sourcing 15.27 ma V DD = 5 V, V DDHV = 5 V, Sinking.498 ma I SVDD Quiescent supply current V OUT = 5 V 114.5 µa from V DD I SVDDHV Quiescent supply current from V DDHV V OUT = 5 V, 89.7 µa AC Characteristics SR Slew Rate 1.2 V/µs GBW Gain-Bandwidth product 1.14 MHz phi M Phase margin 68 Deg e n Input refered noise voltage f = 1 Hz.12 µv/ Hz f = 1 khz.14 µv/ Hz THD Total Harmonic distortion V OUTPP = 9 V.1 % THD Notes: 1. These values represent the onset of clipping. Analogue Integration Ltd., The Old Village, Store Corston, Malmesbury, Wiltshire, SN16 HJ, UK Tel. +44 ()1666 82329 Fax. +44 ()1666 825154 Email Sales@analog.co.uk Web http://www.analog.co.uk 25 Analogue Integration Ltd 4
AISC11 Typical Performance Characteristics 5 Corrected vs Uncorrected Input Offset Voltage Temperature = 27 o C 1 Corrected vs Uncorrected Input Offset Voltage Temperature = 15 o C 4 8 Corrected Input Offset / µv 3 2 1-1 -2-3 Nominal Processing Corrected Input Offset /µv 6 4 2-2 -4-6 Nominal Processing -4 Worst Case Processing -8 Worst Case Processing -5-6 -5-4 -3-2 -1 1 2 3 4 5 6 Uncorrected Input Offset /mv -1-6 -5-4 -3-2 -1 1 2 3 4 5 6 Uncorrected Input offset /mv Corrected Input Offset / µv 5 4 3 2 1-1 -2-3 -4 Corrected vs Uncorrected Input Offset Voltage Temperature = -4 o C Nominal Processing Worst Case Processing -5-6 -5-4 -3-2 -1 1 2 3 4 5 6 Uncorrected Input Offset / mv Corrected Input Offset / µv 2 18 16 14 12 1 8 6 4 2-2 -4-6 -8-1 -12-14 -16 Corrected vs Uncorrected Input Offset Voltage Temperature 175 o C Nominal Processing Worst Case Processing -6-5 -4-3 -2-1 1 2 3 4 5 6 Uncorrected Input Offset / mv Analogue Integration Ltd., The Old Village, Store Corston, Malmesbury, Wiltshire, SN16 HJ, UK Tel. +44 ()1666 82329 Fax. +44 ()1666 825154 Email Sales@analog.co.uk Web http://www.analog.co.uk 25 Analogue Integration Ltd 5
AISC11 Typical Performance Characteristics Positive PSRR vs Frequency Negative PSRR vs Frequency 25 25 2 2 +PSRR /db 15 1 - PSRR /db 15 1 5 5 1 1 1 1 1 1 1 Frequency /Hz 1 1 1 1 1 1 1 Frequency / Hz 14 CMRR vs Frequency 2 Gain & Phase Response vs Frequency Main Amplifier, Load = 1 kω, Temp.= 27 o C, Nominal Processing. 12 15 Phase Gain CMRR /db 1 8 6 4 2 Gain / db & Phase /deg. 1 5 1 1 1 1 1 1 Frequency /Hz -5.1 1. 1. 1. 1. Frequency / Hz Analogue Integration Ltd., The Old Village, Store Corston, Malmesbury, Wiltshire, SN16 HJ, UK Tel. +44 ()1666 82329 Fax. +44 ()1666 825154 Email Sales@analog.co.uk Web http://www.analog.co.uk 25 Analogue Integration Ltd 6
AISC11 Typical Performance Characteristics 2 Gain & Phase Response vs Frequency Main Amplifier, RL= 1kΩ, CL= 5 pf Temp. =27 o C, Nominal Processing 2 Gain & Phase Response vs Frequency Main Amplifier, RL= 1kΩ, CL= 5pF, Temp. = 15 o C, Worst Case Processing Gain / db & Phase / Deg. 15 1 5 Phase Gain Gain /db & Phase 15 1 5 Phase Gain -5-5 -1.1 1 1 1 1 Frequency / Hz -1.1 1 1 1 1 Frequency / Hz 12 Slew Rate 1 Comparison of Equivalent Input Noise Voltage With and Without Auto-Zero Clock on 11 1 9 Without Auto-Zero Clock Vout / V 8 7 6 5 4 3 Input Noise / µv/ Hz 1.1 2 With Auto-Zero Clock 1 1 2 3 4 5 6.1 1 1 1 1 1 1 Time / µs Frequency /Hz Analogue Integration Ltd., The Old Village, Store Corston, Malmesbury, Wiltshire, SN16 HJ, UK Tel. +44 ()1666 82329 Fax. +44 ()1666 825154 Email Sales@analog.co.uk Web http://www.analog.co.uk 25 Analogue Integration Ltd 7
AISC11 Output Clock Noise with a Gain of 44 db 1.24237m 1.795299m 553.2627u 5.15 5.1 VOUT / V 5.5 5.3318 254.3562u 5.775 5 4.9995.6.8 1 1.2 1.4 1.6 1.8 2 2.2 Time/mSecs 2µSecs/div Analogue Integration Ltd., The Old Village, Store Corston, Malmesbury, Wiltshire, SN16 HJ, UK Tel. +44 ()1666 82329 Fax. +44 ()1666 825154 Email Sales@analog.co.uk Web http://www.analog.co.uk 25 Analogue Integration Ltd 8