a Ultralow Distortion, Wide Bandwidth Voltage Feedback Op Amps / FEATURES Wide Bandwidth, G = +, G = +2 Small Signal 32 MHz 25 MHz Large Signal (4 V p-p) 75 MHz 8 MHz Ultralow Distortion (SFDR), Low Noise 3 dbc Typ @ MHz 95 dbc Typ @ 5 MHz 72 dbc Typ @ 2 MHz 46 dbm Third Order Intercept @ 25 MHz 7. nv/ Hz Spectral Noise Density High Speed Slew Rate 3 V/ s Settling 6 ns to.%, 2 V Step 3 V to 5 V Supply Operation 7 ma Supply Current APPLICATIONS ADC Input Driver Differential Amplifiers IF/RF Amplifiers Pulse Amplifiers Professional Video DAC Current to Voltage Baseband and Video Communications Pin Diode Receivers Active Filters/Integrators/Log Amps GENERAL DESCRIPTION The and are very high speed and wide bandwidth amplifiers. They are an improved performance alternative to the AD962 and AD9622. The is unity gain stable. The is stable at gains of 2 or greater. Using a voltage feedback architecture, the / s exceptional settling time, bandwidth, and low distortion meet the requirements of many applications that previously depended on current feedback amplifiers. Its classical op amp structure works much more predictably in many designs. PIN CONFIGURATION 8-Lead PDIP (N) and SOIC (R) Packages / NC INPUT +INPUT V S 2 3 4 TOP VIEW NC = NO CONNECT 8 NC 7 +V S 6 OUTPUT 5 NC A proprietary design architecture has produced an amplifier that combines many of the best characteristics of both current feedback and voltage feedback amplifiers. The and exhibit exceptionally fast and accurate pulse response (6 ns to.%) as well as extremely wide small signal and large signal bandwidth and ultralow distortion. The achieves 72 dbc at 2 MHz, and 32 MHz small signal and 75 MHz large signal bandwidths. These characteristics position the / ideally for driving flash as well as high resolution ADCs. Additionally, the balanced high impedance inputs of the voltage feedback architecture allow maximum flexibility when designing active filters. The / are offered in the industrial ( 4 C to +85 C) temperature range. They are available in PDIP and SOIC. HARMONIC DISTORTION dbc 3 5 7 9 3 k R L = 5 V O = 2V p-p SECOND HARMONIC THIRD HARMONIC k M M M Figure. Harmonic Distortion vs. Frequency, G = + Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 96, Norwood, MA 262-96, U.S.A. Tel: 78/329-47 www.analog.com Fax: 78/326-873 23 Analog Devices, Inc. All rights reserved.
/ SPECIFICATIONS ELECTRICAL CHARACTERISTICS ( V S = 5 V; R LOAD = ; A V = (); A V = 2 (), unless otherwise noted.) A A Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Bandwidth ( 3 db) Small Signal V OUT.4 V p-p 22 32 8 25 MHz Large Signal V OUT = 4 V p-p 5 75 55 8 MHz Bandwidth for. db Flatness V OUT = 3 mv p-p, = 4 W; 3 3 MHz, = 425 W Slew Rate, Average ± V OUT = 4 V Step 3 2 5 V/ms Rise/Fall Time V OUT =.5 V Step.2.4 ns V OUT = 4 V Step 2.5 2. ns Settling Time To.% V OUT = 2 V Step ns To.% V OUT = 2 V Step 6 6 ns HARMONIC/NOISE PERFORMANCE Second Harmonic Distortion 2 V p-p; 2 MHz, R L = W 64 57 54 47 dbc R L = 5 W 72 65 72 65 dbc Third Harmonic Distortion 2 V p-p; 2 MHz, R L = W 76 69 74 67 dbc R L = 5 W 8 74 8 74 dbc Third Order Intercept 25 MHz 46 4 dbm Noise Figure R S = 5 W 8 4 db Input Voltage Noise MHz to 2 MHz 7. 4.3 nv/ Hz Input Current Noise MHz to 2 MHz 2.5 2. pa/ Hz Average Equivalent Integrated Input Noise Voltage. MHz to 2 MHz 6 mv rms Differential Gain Error (3.58 MHz) R L = 5 W.3.6.2.4 % Differential Phase Error (3.58 MHz) R L = 5 W.2.4.2.4 Degree Phase Nonlinearity DC to MHz.. Degree DC PERFORMANCE 2, R L = 5 W Input Offset Voltage 3 3 2 5 mv T MIN T MAX 3 8 mv Offset Voltage Drift ± ± mv/ C Input Bias Current 2 7 2 7 ma T MIN T MAX ma Input Offset Current. 3. 3 ma T MIN T MAX 5 5 ma Common-Mode Rejection Ratio V CM = ±2.5 V 7 9 7 9 db Open-Loop Gain V OUT = ±2.5 V 46 52 46 52 db T MIN T MAX 4 4 db INPUT CHARACTERISTICS Input Resistance 5 5 kw Input Capacitance.2.2 pf Input Common-Mode Voltage Range ±3.4 ±3.4 V OUTPUT CHARACTERISTICS Output Voltage Range, R L = 5 W ±3.2 ±3.9 ±3.2 ±3.9 V Output Current 7 7 ma Output Resistance.3.3 W Short Circuit Current 24 24 ma POWER SUPPLY Operating Range ±3. ±5. ±6. ±3. ±5. ±6. V Quiescent Current 7 8 6 7 ma T MIN T MAX 2 2 ma Power Supply Rejection Ratio T MIN T MAX 5 6 56 66 db NOTES See Absolute Maximum Ratings and Theory of Operation sections of this data sheet. 2 Measured at A V = 5. 3 Measured with respect to the inverting input. Specifications subject to change without notice. 2
/ ABSOLUTE MAXIMUM RATINGS Supply Voltage (+V S to V S )..................... 2.6 V Voltage Swing Bandwidth Product........... 55 V-MHz Internal Power Dissipation 2 Plastic Package (N)............................3 W Small Outline Package (R).......................9 W Input Voltage (Common Mode).................... ±V S Differential Input Voltage....................... ±.2 V Output Short Circuit Duration....................... Observe Power Derating Curves Storage Temperature Range N, R......... 65 C to +25 C Operating Temperature Range (A Grade).... 4 C to +85 C Lead Temperature Range (Soldering sec)......... 3 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead PDIP Package: q JA = 9 C/W 8-Lead SOIC Package: q JA = 4 C/W METALLIZATION PHOTO Dimensions shown in inches and (millimeters) Connect Substrate to V S IN 2 +V S 7 MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by these devices is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 5 C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 75 C for an extended period can result in device failure. While the and are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (5 C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. MAXIMUM POWER DISSIPATION W 2..5..5 8-LEAD PDIP PACKAGE 8-LEAD SOIC PACKAGE T J = +5 C.46 (.7) 6 OUT 5 4 3 2 2 3 4 5 6 7 8 9 AMBIENT TEMPERATURE C Figure 2. Maximum Power Dissipation vs. Temperature ORDERING GUIDE.46 (.7) 3 +IN IN 2 4 V S.5 (.27) +V S 7 6 OUT Temperature Package Package Model Range Description Option AN 4 C to +85 C PDIP N-8 AR 4 C to +85 C SOIC R-8 AR-REEL 4 C to +85 C SOIC R-8 AR-REEL7 4 C to +85 C SOIC R-8 CHIPS Die AN 4 C to +85 C PDIP N-8 AR 4 C to +85 C SOIC R-8 AR-REEL 4 C to +85 C SOIC R-8 AR-REEL7 4 C to +85 C SOIC R-8 3 +IN 4 V S CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although the / features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 3
/ Typical Performance Characteristics PULSE GENERATOR T R /T F = 35ps V IN 3 R T 49.9 +V S F. F. F F V OUT R L = PULSE GENERATOR T R /T F = 35ps V IN 267 R T 49.9 +V S F. F. F F V OUT R L = V S V S TPC. Noninverting Configuration, G = + TPC 4. Inverting Configuration, G = V 5ns V 5ns TPC 2. Large Signal Transient Response; V O = 4 V p-p, G = +, = 25 W TPC 5. Large Signal Transient Response; V O = 4 V p-p, G =, = R IN = 267 W mv 5ns mv 5ns TPC 3. Small Signal Transient Response; V O = 4 mv p-p, G = +, = 4 W TPC 6. Small Signal Transient Response; V O = 4 mv p-p, G =, = R IN = 267 W 4
/ PULSE GENERATOR T R /T F = 35ps R IN +V S F. F PULSE GENERATOR T R /T F = 35ps R IN V IN +V S F. F V IN 3 R T 49.9. F F V OUT R L = R T 49.9. F F V OUT R L = V S V S TPC 7. Noninverting Configuration, G = +2 TPC. Inverting Configuration, G = V 5ns V 5ns TPC 8. Large Signal Transient Response; V O = 4 V p-p, G = +2, = R IN = 422 W TPC. Large Signal Transient Response; V O = 4 V p-p, G =, = R IN = 422 W, R T = 56.2 W mv 5ns mv 5ns TPC 9. Small Signal Transient Response; V O = 4 mv p-p, G = +2, = R IN = 274 W TPC 2. Small Signal Transient Response; V O = 4 mv p-p, G =, = R IN = 267 W, R T = 6.9 W 5
/ GAIN db 2 3 4 5 6 7 R L = V O = 3mV p-p 5 5 2 3dB BANDWIDTH MHz 45 4 35 3 R L = GAIN = + N PACKAGE R PACKAGE 3 R L 8 9 M M M G TPC 3. Small Signal Frequency Response, G = + 25 2 4 6 8 2 4 6 8 2 22 24 VALUE OF FEEDBACK RESISTOR ( ) TPC 6. Small Signal 3 db Bandwidth vs.. 5 25 GAIN db..2.3.4.5 R L = G = + V O = 3mV p-p 2 4 OUTPUT db 2 3 4 5 R L = V O = 4V p-p = 5 TO 25 BY 5.6 6.7 7.8 8.9 M M M 5M TPC 4.. db Flatness, N Package (for R Package Add 2 W to ) 9 M M M TPC 7. Large Signal Frequency Response, G = + 5M GAIN db 9 8 8 7 6 PHASE 6 4 5 2 4 3 2 2 GAIN 4 6 8 2 2 k k M M M G TPC 5. Open-Loop Gain and Phase Margin vs. Frequency, R L = W PHASE MARGIN Degrees GAIN db 2 3 4 5 6 7 8 9 M R L = V O = 3mV p-p 267 M M G TPC 8. Small Signal Frequency Response, G = 6
/ HARMONIC DISTORTION dbc 3 5 7 9 3 k R L = 5 G = + V O = 2V p-p SECOND HARMONIC THIRD HARMONIC k M M TPC 9. Harmonic Distortion vs. Frequency, R L = 5 W M DIFF GAIN %..5..5. ST 2ND 3RD 4TH 5TH DIFF PHASE Degrees..5..5. ST 2ND 3RD 4TH 5TH 6TH 6TH 7TH 7TH 8TH 9TH TH TH 8TH 9TH TH TH TPC 22. Differential Gain and Phase Error, G = +2, R L = 5 W 3.3 HARMONIC DISTORTION dbc 5 7 9 R L = G = + V O = 2V p-p SECOND HARMONIC THIRD HARMONIC ERROR %.2....2 3 k k M M TPC 2. Harmonic Distortion vs. Frequency, R L = W M.3 2 3 4 5 6 7 8 SETTLING TIME ns TPC 23. Short-Term Settling Time, 2 V Step, R L = W 6.3 55 5.2 INTERCEPT dbm 45 4 35 ERROR %.. 3. 25 2 2 3 4 FREQUENCY MHz 5 6 7 8 9 TPC 2. Third Order Intercept vs. Frequency.2 2 3 4 5 6 7 8 SETTLING TIME s 9 TPC 24. Long-Term Settling Time, 2 V Step, R L = W 7
/ GAIN db 7 6 5 4 3 2 2 R L = V O = 3mV p-p 25 225 325 425 3dB BANDWIDTH MHz 35 3 25 2 5 R L = GAIN = +2 49.9 R IN R L N PACKAGE R PACKAGE 3 M M M G TPC 25. Small Signal Frequency Response, G = +2 5 2 25 3 35 4 45 5 55 VALUE OF, R IN TPC 28. Small Signal 3 db Bandwidth vs., R IN. 7 6 525 OUTPUT db..2.3.4.5 R L = G = +2 V O = 3mV p-p 275 325 375 425 OUTPUT db 5 4 3 2 R L = V O = 4V p-p = 25 TO 525 BY.6.7.8 2.9 M M M TPC 26.. db Flatness, N Package (for R Package Add 2 W to ) 3 M M M TPC 29. Large Signal Frequency Response, G = +2 5M A OL db 65 6 55 5 45 5 4 PHASE 35 3 25 5 2 GAIN 5 5 5 5 2 5 25 k k M M M G TPC 27. Open-Loop Gain and Phase Margin vs. Frequency, R L = W PHASE Degrees GAIN db 2 3 4 5 6 7 8 9 M R L = V O = 3mV p-p, R IN 267 M M G TPC 3. Small Signal Frequency Response, G = 8
/ HARMONIC DISTORTION dbc 3 5 7 9 3 k R L = 5 G = +2 V O = 2V p-p SECOND HARMONIC THIRD HARMONIC k M M TPC 3. Harmonic Distortion vs. Frequency, R L = 5 W M DIFF GAIN %.4.2..2.4 ST 2ND 3RD 4TH 5TH DIFF PHASE Degrees.4.2..2.4 ST 2ND 3RD 4TH 5TH 6TH 6TH 7TH 7TH 8TH 9TH TH TH 8TH 9TH TH TH TPC 34. Differential Gain and Phase Error G = +2, R L = 5 W 3.2 HARMONIC DISTORTION dbc 5 7 9 R L = G = +2 V O = 2V p-p SECOND HARMONIC THIRD HARMONIC ERROR %....2 3 k k M M TPC 32. Harmonic Distortion vs. Frequency, R L = W M.3 2 3 4 5 6 7 8 SETTLING TIME ns TPC 35. Short-Term Settling Time, 2 V Step, R L = W 5.3 45 4.2 INTERCEPT dbm 35 3 25 ERROR %.. 2. 5 2 3 4 FREQUENCY MHz 5 6 7 8 9 TPC 33. Third Order Intercept vs. Frequency.2 2 3 4 5 6 7 8 SETTLING TIME s 9 TPC 36. Long-Term Settling Time, 2 V Step, R L = W 9
/ 24 7 2 5 INPUT NOISE VOLTAGE nv/ Hz 8 5 2 9 6 INPUT NOISE VOLTAGE nv/ Hz 3 9 7 5 3 k k k 3 k k k TPC 37. Noise vs. Frequency TPC 4. Noise vs. Frequency PSRR db 8 75 7 65 PSRR 6 55 +PSRR 5 45 4 35 3 25 2 5 5 k k M M M G TPC 38. PSRR vs. Frequency PSRR db 8 75 7 65 PSRR 6 55 +PSRR 5 45 4 35 3 25 2 5 5 k k M M M G TPC 4. PSRR vs. Frequency 9 V CM = V R L = 9 V CM = V R L = 8 8 CMRR db 7 6 5 CMRR db 7 6 5 4 4 3 3 2 k M M M G 2 k M M M G TPC 39. CMRR vs. Frequency TPC 42. CMRR vs. Frequency
/ 35 GAIN = + 25 R OUT OPEN-LOOP GAIN V/V 5 5 95 85 75 65 +A OL A OL.. k k M M M TPC 43. Output Resistance vs. Frequency 55 +A OL 45 A OL 35 6 4 2 2 4 6 8 2 4 JUNCTION TEMPERATURE C TPC 46. Open-Loop Gain vs. Temperature 76 GAIN = + 74 72 PSRR 7 R OUT PSRR db 68 66 64 +PSRR PSRR 62.. k k M M M TPC 44. Output Resistance vs. Frequency 6 58 56 6 +PSRR 4 2 2 4 6 8 2 4 JUNCTION TEMPERATURE C TPC 47. PSRR vs. Temperature 4. 4. 3.9 +V OUT V OUT R L = 5 98 96 OUTPUT SWING V 3.8 3.7 3.6 3.5 +V OUT R L = 5 CMRR db 94 92 9 3.4 V OUT 88 +CMRR CMRR 3.3 6 4 2 2 4 6 8 JUNCTION TEMPERATURE C 2 4 86 6 4 2 2 4 6 8 JUNCTION TEMPERATURE C 2 4 TPC 45. / Output Swing vs. Temperature TPC 48. / CMRR vs. Temperature
/ SUPPLY CURRENT ma 2 2 9 8 7 6 5 6V 6V 5V 5V SHORT CIRCUIT CURRENT ma 25 24 23 22 2 2 9 SINK SOURCE SINK SOURCE 4 6 4 2 2 4 6 8 JUNCTION TEMPERATURE C 2 4 8 6 4 2 2 4 6 8 JUNCTION TEMPERATURE C 2 4 TPC 49. Supply Current vs. Temperature TPC 52. Short Circuit Current vs. Temperature. 2..5.5 INPUT OFFSET VOLTAGE mv 2. 2.5 3. 3.5 4. V S = 6V INPUT BIAS CURRENT A..5..5. +I B I B I B 4.5 V S = 6V.5 +I B 5. 6 4 2 2 4 6 8 JUNCTION TEMPERATURE C 2 4 2. 6 4 2 2 4 6 8 JUNCTION TEMPERATURE C 2 4 TPC 5. Input Offset Voltage vs. Temperature TPC 53. Input Bias Current vs. Temperature COUNT 22 2 8 6 4 2 8 6 4 2 3 WAFER LOTS COUNT = 373 FREQ. DIST CUMULATIVE 9 8 7 6 5 4 3 2 PERCENT COUNT 8 6 4 2 8 6 4 2 3 WAFER LOTS COUNT = 573 FREQ. DIST CUMULATIVE 9 8 7 6 5 4 3 2 PERCENT 7 6 5 4 3 2 2 3 INPUT OFFSET VOLTAGE mv 4 5 6 7 7 6 5 4 3 2 2 3 INPUT OFFSET VOLTAGE mv 4 5 6 7 TPC 5. Input Offset Voltage Distribution TPC 54. Input Offset Voltage Distribution 2
/ THEORY OF OPERATION General The and are wide bandwidth, voltage feedback amplifiers. Since their open-loop frequency response follows the conventional 6 db/octave roll-off, their gain bandwidth product is basically constant. Increasing their closed-loop gain results in a corresponding decrease in small signal bandwidth. This can be observed by noting the bandwidth specification between the (gain of +) and (gain of +2). The / typically maintain 65 degrees of phase margin. This high margin minimizes the effects of signal and noise peaking. Feedback Resistor Choice The value of the feedback resistor is critical for optimum performance on the (gain of +) and less critical as the gain increases. Therefore, this section is specifically targeted at the. At minimum stable gain (+), the provides optimum dynamic performance with = 4 W. This resistor acts as a parasitic suppressor only against damped RF oscillations that can occur due to lead (input, feedback) inductance and parasitic capacitance. This value of provides the best combination of wide bandwidth, low parasitic peaking, and fast settling time. In fact, for the same reasons, a W 3 W resistor should be placed in series with the positive input for other noninverting and all inverting configurations. The correct connection is shown in Figures 3 and 4. When the is used in the transimpedance (I to V) mode, such as in photodiode detection, the value of and diode capacitance (C I ) are usually known. Generally, the value of selected will be in the kw range, and a shunt capacitor (C F ) across will be required to maintain good amplifier stability. The value of C F required to maintain optimal flatness (< db peaking) and settling time can be estimated as [ ] 2 2 F O I F O F C 2 C R / R @ ( ) where w O is equal to the unity gain bandwidth product of the amplifier in rad/sec, and C I is the equivalent total input capacitance at the inverting input. Typically w O = 8 6 rad/sec (see TPC 5). As an example, choosing = kw and C I = 5 pf requires C F to be. pf (Note: C I includes both source and parasitic circuit capacitance). The bandwidth of the amplifier can be estimated using the C F calculated as I I C I f 3d 6. @ 2 RC F C F F 2 V OUT G = + R G +V S F 3 V IN R R IN TERM R G /. F. F F V S V OUT Figure 3. Noninverting Operation G = R G +V S F Figure 5. Transimpedance Configuration For general voltage gain applications, the amplifier bandwidth can be closely estimated as f 3dB O @ 2 + R /R ( F G) This estimation loses accuracy for gains of +2/ or lower due to the amplifier s damping factor. For these low gain cases, the bandwidth will actually extend beyond the calculated value (see TPCs 3 and 25). As a general rule, capacitor C F will not be required if NG ( RF RG ) CI 4 O 3 R IN /. F V OUT where NG is the noise gain ( + /R G ) of the circuit. For most voltage gain applications, this should be the case. V IN R TERM R G. F F V S Figure 4. Inverting Operation 3
/ Pulse Response Unlike a traditional voltage feedback amplifier, where the slew speed is dictated by its front end dc quiescent current and gain bandwidth product, the and provide on-demand current that increases proportionally to the input step signal amplitude. This results in slew rates (3 V/ms) comparable to wideband current feedback designs. This, combined with relatively low input noise current (2. pa/ Hz), gives the and the best attributes of both voltage and current feedback amplifiers. Large Signal Performance The outstanding large signal operation of the and is due to a unique, proprietary design architecture. In order to maintain this level of performance, the maximum 55 V-MHz product must be observed (e.g., @ MHz, V O 5.5 V p-p). Power Supply Bypassing Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier s response. In addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than mf) will be required to provide the best settling time and lowest distortion. A parallel combination of at least 4.7 mf, and between. mf and. mf, is recommended. Some brands of electrolytic capacitors will require a small series damping resistor ª4.7 W for optimum results. Driving Capacitive Loads The and were designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, the best frequency response is obtained by the addition of a small series resistance as shown in Figure 6. The accompanying graph shows the optimum value for R SERIES versus capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of R SERIES and C L. R SERIES 4 3 2 5 5 C L pf 2 25 Figure 7. Recommended R SERIES vs. Capacitive Load APPLICATIONS The and are voltage feedback amplifiers well suited for applications such as photodetectors, active filters, and log amplifiers. The devices wide bandwidth (32 MHz), phase margin (65 ), low current noise (2. pa/ Hz), and slew rate (3 V/ms) give higher performance capabilities to these applications over previous voltage feedback designs. With a settling time of 6 ns to.% and ns to.%, the devices are an excellent choice for DAC I/V conversion. The same characteristics along with low harmonic distortion make them a good choice for ADC buffering/amplification. With superb linearity at relatively high signal frequencies, the and are ideal drivers for ADCs up to 2 bits. Operation as a Video Line Driver The and have been designed to offer outstanding performance as video line drivers. The important specifications of differential gain (.2%) and differential phase (.2 ) meet the most exacting HDTV demands for driving video loads. 274 274 R IN R IN / R SERIES R L k Figure 6. Driving Capacitive Loads C L V IN 75 CABLE 75 +V S / F. F. F F 75 75 CABLE V OUT 75 V S Figure 8. Video Line Driver 4
/ Active Filters The wide bandwidth and low distortion of the and are ideal for the realization of higher bandwidth active filters. These characteristics, while being more common in many current feedback op amps, are offered in the and in a voltage feedback configuration. Many active filter configurations are not realizable with current feedback amplifiers. A multiple feedback active filter requires a voltage feedback amplifier and is more demanding of op amp performance than other active filter configurations, such as the Sallen-Key. In general, the amplifier should have a bandwidth that is at least times the bandwidth of the filter if problems due to phase shift of the amplifier are to be avoided. Figure 9 is an example of a 2 MHz low-pass multiple feedback active filter using an. V IN R4 54 R 54 C2 pf R3 78.7 C 5pF 5V +5V F. F F. F Figure 9. Active Filter Circuit V OUT Choose F O = Cutoff Frequency = 2 MHz a = Damping Ratio = /Q = 2 H = Absolute Value of Circuit Gain = R4 R = Then k = 2 F C O 4C( H + ) C2 = 2 R = 2 HK R3 = 2K( H + ) R4 = H( R) A/D Converter Driver As A/D converters move toward higher speeds with higher resolutions, there becomes a need for high performance drivers that will not degrade the analog signal to the converter. It is desirable from a system s standpoint that the A/D be the element in the signal chain that ultimately limits overall distortion. This places new demands on the amplifiers that are used to drive fast, high resolution A/Ds. With high bandwidth, low distortion, and fast settling time, the and make high performance A/D drivers for advanced converters. Figure is an example of an used as an input driver for an AD872, a 2-bit, MSPS A/D converter. +5V DIGITAL ANALOG IN +5V ANALOG 4 F. F 3. F F 5V ANALOG +5V ANALOG 4 AV DD. F 5 AGND AD872 V INA 2 V INB 27 REF GND. F 28 REF IN 26 REF OUT F 7 DV DD 6 DGND 22 DV DD 23 DGND 2 CLK 2 OTR 9 MSB 8 BIT2 7 BIT3 6 BIT4 5 BIT5 4 BIT6 3 BIT7 2 BIT8 BIT9 BIT 9 BIT 8 BIT2. F +5V DIGITAL. F CLOCK INPUT 49.9 DIGITAL OUTPUT AGND AV SS AV SS 3 25. F. F 5V ANALOG Figure. Used as Driver for an AD872, a 2-Bit, MSPS A/D Converter 5
/ Layout Considerations The specified high speed performance of the and requires careful attention to board layout and component selection. Proper RF design techniques and low-pass parasitic component selection are mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing (see Figure ). One end should be connected to the ground plane, and the other within /8 inch of each power pin. An additional large (.47 mf mf) tantalum electrolytic capacitor should be connected in parallel, though not necessarily so close, to supply current for fast, large signal changes at the output. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than pf at the inverting input will significantly affect high speed performance. Stripline design techniques should be used for long signal traces (greater than about inch). These should be designed with a characteristic impedance of 5 W or 75 W and be properly terminated at each end. 6
/ OUTLINE DIMENSIONS 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters).375 (9.53).365 (9.27).355 (9.2).8 (4.57) MAX 8 5.295 (7.49).285 (7.24) 4.275 (6.98). (2.54) BSC.5 (.38) MIN.5 (3.8).3 (3.3) SEATING PLANE. (2.79).6 (.52).22 (.56).5 (.27).8 (.46).45 (.4).4 (.36).325 (8.26).3 (7.87).3 (7.62).5 (3.8).35 (3.43).2 (3.5).5 (.38). (.25).8 (.2) COMPLIANT TO JEDEC STANDARDS MO-95AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 5. (.968) 4.8 (.89) 4. (.574) 3.8 (.497) 8 5 4 6.2 (.244) 5.8 (.2284).25 (.98). (.4) COPLANARITY..27 (.5) BSC SEATING PLANE.75 (.688).35 (.532).5 (.2).3 (.22).25 (.98).7 (.67) 8.5 (.96) 45.25 (.99).27 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-2AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 7
/ Revision History Location Page 7/3 Data Sheet changed from REV. B to. Deleted Evaluation Boards information.................................................................universal Deleted military CERDIP version.....................................................................universal Change to ABSOLUTE MAXIMUM RATINGS............................................................... 3 Change to TPC 4....................................................................................... 4 Change to TPC...................................................................................... 5 Change to Figure 6..................................................................................... 4 Updated OUTLINE DIMENSIONS....................................................................... 7 /3 Data Sheet changed from REV. A to REV. B. Deleted DIP (N) Inverter, SOIC (R) Inverter, and DIP (N) Noninverter Evaluation Boards in Figures 2 4............... 7 Updated OUTLINE DIMENSIONS....................................................................... 8 8
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2 C6 7/3(C)