High-Speed, Low-Power Dual Operational Amplifier AD826

a FEATURES High Speed: MHz Unity Gain Bandwidth 3 V/ s Slew Rate 7 ns Settling Time to.% Low Power: 7. ma Max Power Supply Current Per Amp Easy to Use: Drives Unlimited Capacitive Loads ma Min Output Current Per Amplifier Specified for + V, V and V Operation 2. V p-p Output Swing into a Load (V S = + V) Good Video Performance Differential Gain & Phase Error of.7% &. Excellent DC Performance: 2. mv Max Input Offset Voltage APPLICATIONS Unity Gain ADC/DAC Buffer Cable Drivers 8- and -Bit Data Acquisition Systems Video Line Driver Active Filters PRODUCT DESCRIPTION The is a dual, high speed voltage feedback op amp. It is ideal for use in applications which require unity gain stability and high output drive capability, such as buffering and cable driving. The MHz bandwidth and 3 V/µs slew rate make the useful in many high speed applications including: video, CATV, copiers, LCDs, image scanners and fax machines. High-Speed, Low-Power Dual Operational Amplifier CONNECTION DIAGRAM 8-Lead Plastic Mini-DIP and SO Package OUT IN +IN V 2 3 4 8 7 6 V+ OUT2 The features high output current drive capability of ma min per amp, and is able to drive unlimited capacitive loads. With a low power supply current of ma max for both amplifiers, the is a true general purpose operational amplifier. The is ideal for power sensitive applications such as video cameras and portable instrumentation. The can operate from a single + V supply, while still achieving 2 MHz of bandwidth. Furthermore the is fully specified from a single + V to ± V power supplies. The excels as an ADC/DAC buffer or active filter in data acquisition systems and achieves a settling time of 7 ns to.%, with a low input offset voltage of 2 mv max. The is available in small 8-lead plastic mini-dip and SO packages. IN2 +IN2 3.3 F ns. F C L = pf HP PULSE GENERATOR V IN 3 2 TEKTRONIX P62 FET PROBE TEKTRONIX 7A24 FET PREAMP. F % C L = pf V S 3.3 F C L Driving a Large Capacitive Load Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 96, Norwood, MA 262-96, U.S.A. Tel: 78/329-47 www.analog.com Fax: Analog Devices, Inc.,

* PRODUCT PAGE QUICK LINKS Last Content Update: 2/23/27 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS Universal Evaluation Board for Dual High Speed Operational Amplifiers DOCUMENTATION Application Notes AN-36: User's Guide to Applying and Measuring Operational Amplifier Specifications AN-42: Replacing Output Clamping Op Amps with Input Clamping Amps AN-47: Fast Rail-to-Rail Operational Amplifiers Ease Design Constraints in Low Voltage High Speed Systems AN-8: Biasing and Decoupling Op Amps in Single Supply Applications AN-649: Using the Analog Devices Active Filter Design Tool Data Sheet : High Speed, Low Power Dual Operational Amplifier Data Sheet User Guides UG-28: Universal Evaluation Board for Dual High Speed Op Amps in SOIC Packages TOOLS AND SIMULATIONS Analog Filter Wizard Analog Photodiode Wizard Power Dissipation vs Die Temp VRMS/dBm/dBu/dBV calculators SPICE Macro-Model REFERENCE MATERIALS Product Selection Guide High Speed Amplifiers Selection Table Tutorials MT-32: Ideal Voltage Feedback (VFB) Op Amp MT-33: Voltage Feedback Op Amp Gain and Bandwidth MT-47: Op Amp Noise MT-48: Op Amp Noise Relationships: /f Noise, RMS Noise, and Equivalent Noise Bandwidth MT-49: Op Amp Total Output Noise Calculations for Single-Pole System MT-: Op Amp Total Output Noise Calculations for Second-Order System MT-2: Op Amp Noise Figure: Don't Be Misled MT-3: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR MT-6: High Speed Voltage Feedback Op Amps MT-8: Effects of Feedback Capacitance on VFB and CFB Op Amps MT-6: Choosing Between Voltage Feedback and Current Feedback Op Amps DESIGN RESOURCES Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

SPECIFICATIONS (@ T A = +2 C, unless otherwise noted) Parameter Conditions V S Min Typ Max Unit DYNAMIC PERFORMANCE Unity Gain Bandwidth ± V 3 3 MHz ± V 4 MHz, + V 2 29 MHz Bandwidth for. db Flatness Gain = + ± V 2 MHz ± V 2 MHz, + V 2 MHz Full Power Bandwidth = V p-p R LOAD = Ω ± V.9 MHz = 2 V p-p R LOAD = kω ± V.6 MHz Slew Rate R LOAD = kω ± V 2 2 V/µs Gain = ± V 3 3 V/µs, + V 2 V/µs Settling Time to.% 2. V to +2. V ± V 4 ns V V Step, A V = ± V 4 ns to.% 2. V to +2. V ± V 7 ns V V Step, A V = ± V 7 ns NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion F C = MHz ± V 78 db Input Voltage Noise f = khz ± V, ± V nv/ Hz Input Current Noise f = khz ± V, ± V. pa/ Hz Differential Gain Error NTSC ± V.7. % (R = Ω) Gain = +2 ± V.2. %, + V. % Differential Phase Error NTSC ± V.. Degrees (R = Ω) Gain = +2 ± V.2. Degrees, + V. Degrees DC PERFORMANCE Input Offset Voltage ± V to ± V. 2 mv T MIN to T MAX 3 mv Offset Drift µv/ C Input Bias Current ± V, ± V 3.3 6.6 µa T MIN µa T MAX 4.4 µa Input Offset Current ± V, ± V 2 3 na T MIN to T MAX na Offset Current Drift.3 na/ C Open-Loop Gain = ±2. V ± V R LOAD = Ω 2 4 V/mV T MIN to T MAX. V/mV R LOAD = Ω. 3 V/mV = ± V ± V R LOAD = kω 3. 6 V/mV T MIN to T MAX 2 V/mV = ±7. V ± V R LOAD = Ω ( ma Output) 2 4 V/mV INPUT CHARACTERISTICS Input Resistance 3 kω Input Capacitance. pf Input Common-Mode Voltage Range ± V +3.8 +4.3 V 2.7 3.4 V ± V +3 +4.3 V 2 3.4 V, + V +3.8 +4.3 V +.2 +.9 V Common-Mode Rejection Ratio V CM = ±2. V, T MIN T MAX ± V 8 db V CM = ± 2 V ± V 86 2 db T MIN to T MAX ± V 8 db 2

ABSOLUTE MAXIMUM RATINGS Supply Voltage............................... ± 8 V Internal Power Dissipation 2 Plastic (N)..................... See Derating Curves Small Outline (R)................ See Derating Curves Input Voltage (Common Mode)................... ± V S Differential Input Voltage....................... ± 6 V Output Short Circuit Duration....... See Derating Curves Storage Temperature Range (N, R)....... 6 C to +2 C Operating Temperature Range.......... 4 C to +8 C Lead Temperature Range (Soldering seconds)... +3 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-lead plastic package, θ JA = C/watt; 8-lead SOIC package, θ JA = C/watt. Parameter Conditions V S Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing R LOAD = Ω ± V 3.3 3.8 ± V R LOAD = Ω ± V 3.2 3.6 ± V R LOAD = kω ± V 3.3 3.7 ± V R LOAD = Ω ± V 2.8 3.4 ± V R LOAD = Ω, + V +., +3. V Output Current ± V ma ± V ma, + V 3 ma Short-Circuit Current ± V ma Output Resistance Open Loop 8 Ω MATCHING CHARACTERISTICS Dynamic Crosstalk f = MHz ± V 8 db Gain Flatness Match G = +, f = 4 MHz ± V.2 db Slew Rate Match G = ± V V/µs DC Input Offset Voltage Match T MIN T MAX ± V to ± V. 2 mv Input Bias Current Match T MIN T MAX ± V to ± V.6.8 µa Open-Loop Gain Match V O = ± V, R LOAD = kω, T MIN T MAX ± V.. mv/v Common-Mode Rejection Ratio Match V CM = ±2 V, T MIN T MAX ± V 8 db Power Supply Rejection Ratio Match ± V to ± V, T MIN T MAX 8 db POWER SUPPLY Operating Range Dual Supply ± 2. ± 8 V Single Supply + +36 V Quiescent Current/Amplifier ± V 6.6 7. ma T MIN to T MAX ± V 7. ma ± V 7. ma T MIN to T MAX ± V 6.8 7. ma Power Supply Rejection Ratio V S = ± V to ± V, T MIN to T MAX 7 86 db NOTES Full power bandwidth = slew rate/2 π V PEAK. Specifications subject to change without notice. ESD SUSCEPTIBILITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 volts, which readily accumulate on the human body and on test equipment, can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. MAXIMUM POWER DISSIPATION Watts 2.... 8-LEAD MINI-DIP PACKAGE 8-LEAD SOIC PACKAGE T J = + C 4 3 2 2 3 4 6 7 8 AMBIENT TEMPERATURE C Maximum Power Dissipation vs. Temperature for Different Package Types 3

Typical Characteristics INPUT COMMON-MODE RANGE Volts 2 +V CM V CM 2 SUPPLY VOLTAGE Volts QUIESCENT SUPPLY CURRENT PER AMP ma 7.7 7.2 +8 C +2 C 6.7 4 C 6.2.7 2 SUPPLY VOLTAGE Volts Figure. Common-Mode Voltage Range vs. Supply Figure 4. Quiescent Supply Current per Amp vs. Supply Voltage for Various Temperatures 2 4 OUTPUT VOLTAGE SWING Volts R L = R L = SLEW RATE V/ s 3 3 2 2 SUPPLY VOLTAGE Volts Figure 2. Output Voltage Swing vs. Supply 2 SUPPLY VOLTAGE Volts Figure. Slew Rate vs. Supply Voltage 2 3 OUTPUT VOLTAGE SWING Volts p-p 2 2 V S = V S = CLOSED-LOOP OUTPUT IMPEDANCE. k LOAD RESISTANCE k. k k k M M M Figure 3. Output Voltage Swing vs. Load Resistance Figure 6. Closed-Loop Output Impedance vs. Frequency 4

INPUT BIAS CURRENT A 7 6 4 3 2 6 4 2 2 4 6 8 2 4 TEMPERATURE C Figure 7. Input Bias Current vs. Temperature OPEN-LOOP GAIN db 8 6 4 2 2 k k GAIN SUPPLIES GAIN SUPPLIES RL = k M M PHASE OR SUPPLIES M Figure. Open-Loop Gain and Phase Margin vs. Frequency G + +8 +6 +4 +2 PHASE MARGIN Degrees 3 7 SHORT CIRCUIT CURRENT ma 7 SINK CURRENT SOURCE CURRENT OPEN-LOOP GAIN V/mV 6 4 3 2 3 6 4 2 2 4 6 8 2 4 TEMPERATURE C Figure 8. Short Circuit Current vs. Temperature k k LOAD RESISTANCE Figure. Open-Loop Gain vs. Load Resistance PHASE MARGIN Degrees 8 6 4 GAIN BANDWIDTH PHASE MARGIN 8 6 4 UNITY GAIN BANDWIDTH MHz PSR db 8 7 6 4 3 NEGATIVE SUPPLY POSITIVE SUPPLY 2 2 2 6 4 2 2 4 6 8 2 4 TEMPERATURE C Figure 9. Unity Gain Bandwidth and Phase Margin vs. Temperature k k k M M M Figure 2. Power Supply Rejection vs. Frequency

4 4 V IN = V p-p GAIN = +2 CMR db 2 8 HARMONIC DISTORTION db 6 7 8 2ND HARMONIC 3RD HARMONIC 6 k k k M M Figure 3. Common-Mode Rejection vs. Frequency k k k M M Figure 6. Harmonic Distortion vs. Frequency 3 OUTPUT VOLTAGE Volts p-p 2 R L = R L = INPUT VOLTAGE NOISE nv/ Hz 4 3 2 k M M M Figure 4. Large Signal Frequency Response 3 k k k M M Figure 7. Input Voltage Noise Spectral Density 8.% 38 OUTPUT SWING FROM TO V 6 4 2 2 4 6 8 %.% %.%.% SLEW RATE V/ s 36 34 32 2 4 6 8 2 4 6 SETTLING TIME ns Figure. Output Swing and Error vs. Settling Time 3 6 4 2 2 4 6 8 2 4 TEMPERATURE C Figure 8. Slew Rate vs. Temperature 6

4 3 2 V IN 78.dB V S FLATNESS MHz 2MHz 2MHz 4.dB V S C C FLATNESS 3 V IN C C 3pF 6MHz 4pF 4MHz 2 6pF 2MHz GAIN db 2 3 V S = V S = V S = GAIN db 2 3 V S = V S = V S = 4 4 k M M M Figure 9. Closed-Loop Gain vs. Frequency k M M M FREQUENCY HZ Figure 22. Closed-Loop Gain vs. Frequency, Gain = DIFFERENTIAL PHASE Degrees.3 DIFF GAIN..3.7.2 DIFF PHASE.. SUPPLY VOLTAGE Volts Figure 2. Differential Gain and Phase vs. Supply Voltage DIFFERENTIAL GAIN Percent GAIN db..8.6.4.2 V S =.2 V S =.4.6 V S = +.8. k M M M Figure 23. Gain Flatness Matching vs. Supply, G = + 3 4 CROSSTALK db 6 7 8 R L = R L = V IN 3 8 2 F R L R L 7 6 4 F V S k k M M Figure 2. Crosstalk vs. Frequency M R L = FOR =, FOR = USE GROUND PLANE PINOUT SHOWN IS FOR MINIDIP PACKAGE Figure 24. Crosstalk Test Circuit 7

3.3 F. F PULSE (LS) OR FUNCTION (SS) GENERATOR V IN R IN. F TEKTRONIX P62 FET PROBE TEKTRONIX 7A24 PREAMP R L V S 3.3 F Figure 2. Noninverting Amplifier Configuration ns 2mV ns % % 2mV Figure 26. Noninverting Large Signal Pulse Response, R L = kω Figure 28. Noninverting Small Signal Pulse Response, R L = kω ns 2mV ns % % 2mV Figure 27. Noninverting Large Signal Pulse Response, R L = Ω Figure 29. Noninverting Small Signal Pulse Response, R L = Ω 8

3.3 F R IN PULSE (LS) V IN OR FUNCTION (SS) GENERATOR. F TEKTRONIX P62 FET PROBE TEKTRONIX 7A24 PREAMP. F R L V S 3.3 F Figure 3. Inverting Amplifier Configuration ns 2mV ns % % 2mV Figure 3. Inverting Large Signal Pulse Response, R L = kω Figure 33. Inverting Small Signal Pulse Response, R L = kω ns 2mV ns % % 2mV Figure 32. Inverting Large Signal Pulse Response, R L = Ω Figure 34. Inverting Small Signal Pulse Response, R L = Ω 9

THEORY OF OPERATION The is a low cost, wide band, high performance dual operational amplifier which can drive heavy capacitive and resistive loads. It also achieves a constant slew rate, bandwidth and settling time over its entire specified temperature range. The (Figure 3) consists of a degenerated NPN differential pair driving matched PNPs in a folded-cascode gain stage. The output buffer stage employs emitter followers in a class AB amplifier which delivers the necessary current to the load while maintaining low levels of distortion. IN +IN C F NULL NULL8 Figure 3. Simplified Schematic +V S OUTPUT The capacitor, CF, in the output stage mitigates the effect of capacitive loads. With low capacitive loads, the gain from the compensation node to the output is very close to unity. In this case, CF is bootstrapped and does not contribute to the overall compensation capacitance of the device. As the capacitive load is increased, a pole is formed with the output impedance of the output stage. This reduces the gain, and therefore, CF is incompletely bootstrapped. Effectively, some fraction of CF contributes to the overall compensation capacitance, reducing the unity gain bandwidth. As the load capacitance is further increased, the bandwidth continues to fall, maintaining the stability of the amplifier. INPUT CONSIDERATIONS An input protection resistor (RIN in Figure 2) is required in circuits where the input to the will be subjected to transient or continuous overload voltages exceeding the ±6 V maximum differential limit. This resistor provides protection for the input transistors by limiting their maximum base current. V S For high performance circuits, it is recommended that a balancing resistor be used to reduce the offset errors caused by bias current flowing through the input and feedback resistors. The balancing resistor equals the parallel combination of RIN and RF and thus provides a matched impedance at each input terminal. The offset voltage error will then be reduced by more than an order of magnitude. APPLYING THE The is a breakthrough dual amp that delivers precision and speed at low cost with low power consumption. The offers excellent static and dynamic matching characteristics, combined with the ability to drive heavy resistive and capacitive loads. As with all high frequency circuits, care should be taken to maintain overall device performance as well as their matching. The following items are presented as general design considerations. Circuit Board Layout Input and output runs should be laid out so as to physically isolate them from remaining runs. In addition, the feedback resistor of each amplifier should be placed away from the feedback resistor of the other amplifier, since this greatly reduces inter-amp coupling. Choosing Feedback and Gain Resistors In order to prevent the stray capacitance present at each amplifier s summing junction from limiting its performance, the feedback resistors should be kω. Since the summing junction capacitance may cause peaking, a small capacitor ( pf pf) maybe paralleled with RF to neutralize this effect. Finally, sockets should be avoided, because of their tendency to increase interlead capacitance. Power Supply Considerations To ensure the proper operation of the, connect the positive supply before the negative supply. Also, proper power supply decoupling is critical to preserve the integrity of high frequency signals. In carefully laid out designs, decoupling capacitors should be placed in close proximity to the supply pins, while their lead lengths should be kept to a minimum. These measures greatly reduce undesired inductive effects on the amplifier s response. Though two. μf capacitors will typically be effective in decoupling the supplies, several capacitors of different values can be paralleled to cover a wider frequency range. -- Rev. C

SINGLE SUPPLY OPERATION An exciting feature of the is its ability to perform well in a single supply configuration (see Figure 37). The is ideally suited for applications that require low power dissipation and high output current and those which need to drive large capacitive loads, such as high speed buffering and instrumentation. Referring to Figure 36, careful consideration should be given to the proper selection of component values. The choices for this particular circuit are: (R + R3) R2 combine with C to form a low frequency corner of approximately 3 Hz. R3 and C2 reduce the effect of the power supply changes on the output by low-pass filtering with a corner at 2πR 3 C 2. The values for R L and C L were chosen to demonstrate the s exceptional output drive capability. In this configuration, the output is centered around 2. V. In order to eliminate the static dc current associated with this level, C3 was inserted in series with R L. mv R3 3.3 F C2 R 9k. F V IN C F R2 k R L C3 C OUT C L 2pF Figure 36. Single Supply Amplifier Configuration % mv ns Figure 37. Single Supply Pulse Response, G = +, R L = Ω, C L = 2 pf PARALLEL AMPS PROVIDE ma TO LOAD By taking advantage of the superior matching characteristics of the, enhanced performance can easily be achieved by employing the circuit in Figure 38. Here, two identical cells are paralleled to obtain even higher load driving capability than that of a single amplifier ( ma min guaranteed). R and R2 are included to limit current flow between amplifier outputs that would arise in the presence of any residual mismatch. V IN F R R2 R L V S F Figure 38. Parallel Amp Configuration

SINGLE-ENDED TO DIFFERENTIAL LINE DRIVER Outstanding CMRR (> 8 db @ MHz), high bandwidth, wide supply voltage range, and the ability to drive heavy loads, make the an ideal choice for many line driving applications. In this application, the AD83 high speed video difference amp serves as the differential line receiver on the end of a back terminated, ft., twisted-pair transmission line (see Figure 4). The overall system is configured in a gain of + and has a 3 db bandwidth of 4 MHz. Figure 39 is the pulse response with a 2 V p-p, MHz signal input. 2V 2ns % 2V Figure 39. Pulse Response. F. F I N 2.2 F FEET TWISTED PAIR Z = 72.k 36 36 BNC pf.k AD83.k.k 36 pf 36. F. F 2.2 F Figure 4. Differential Line Driver LOW DISTORTION LINE DRIVER The can quickly be turned into a powerful, low distortion line driver (see Figure 4). In this arrangement the can comfortably drive a 7 Ω back-terminated cable, with a MHz, 2 V p-p input; all of this while achieving the harmonic distortion performance outlined in the following table. Configuration 2nd Harmonic. F. No Load 78. dbm R C 7. 2. Ω R L Only 63.8 dbm 3. Ω R L 7. Ω R C 7.4 dbm In this application one half of the operates at a gain of 2. and supplies the current to the load, while the other provides the overall system gain of 2. This is important for two reasons: the first is to keep the bandwidth of both amplifiers the same, and the second is to preserve the s ability to operate from low supply voltages. R C varies with the load and must be chosen to satisfy the following equation: 7 F 7 Figure 4. Low Distortion Amplifier R L 7 R C = MR L where M is defined by [(M+ ) G S = G D ] and G D = Driver s Gain, G S = System Gain. 2

HIGH PERFORMANCE ADC BUFFER Figure 42 is a schematic of a 2-bit high speed analog-to-digital converter. The dual op amp takes a single ended input and drives the AD872 A/D converter differentially, thus reducing 2nd harmonic distortion. Figure 43 is a FFT of a MHz input, sampled at MHz with a THD of 78 db. The can be used to amplify low level signals so that the entire range of the converter is used. The ability of the to perform on a ± volt supply or even with a single volts combined with its rapid settling time and ability to deliver high current to complicated loads make it a very good flash A/D converter buffer as well as a very useful general purpose building block. V IN mv p-p MAX COAX CABLE 2. V INA AD872 2-BIT MSPS ADC V INB COMMON F 2 F 2 V S V S Figure 42. A Differential Input Buffer for High Bandwidth ADCs Figure 43. FFT, Buffered A/D Converter 3

OUTLINE DIMENSIONS.4 (.6).36 (9.27).3 (9.2).2 (.33) MAX. (3.8).3 (3.3). (2.92).22 (.6).8 (.46).4 (.36) 8. (2.4) BSC.28 (7.).2 (6.3) 4.24 (6.). (.38) MIN SEATING PLANE. (.3) MIN.6 (.2) MAX. (.38) GAUGE PLANE.32 (8.26).3 (7.87).3 (7.62).43 (.92) MAX.9 (4.9).3 (3.3). (2.92).4 (.36). (.2).8 (.2).7 (.78).6 (.2).4 (.4) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 44. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 766-A. (.968) 4.8 (.8) 4. (.74) 3.8 (.497) 8 4 6.2 (.244).8 (.2284).2 (.98). (.4) COPLANARITY. SEATING PLANE.27 (.) BSC.7 (.688).3 (.32). (.2).3 (.22).2 (.98).7 (.67). (.96).2 (.99).27 (.).4 (.7) COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 4. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option AN 4 C to +8 C 8-Lead PDIP N-8 ANZ 4 C to +8 C 8-Lead PDIP N-8 AR 4 C to +8 C 8-Lead SOIC_N R-8 AR-REEL 4 C to +8 C 8-Lead SOIC_N R-8 AR-REEL7 4 C to +8 C 8-Lead SOIC_N R-8 ARZ 4 C to +8 C 8-Lead SOIC_N R-8 ARZ-REEL 4 C to +8 C 8-Lead SOIC_N R-8 ARZ-REEL7 4 C to +8 C 8-Lead SOIC_N R-8 Z = RoHS Compliant Part. 8 4 247-A -4- Rev. C

REVISION HISTORY Changed Power Supply Bypassing Section to Power Supply Considerations Section... Changes to Power Supply Considerations Section... Updated Outline Dimensions... 4 Changes to Ordering Guide... 4 2 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D89--4/(C) Rev. C --