April 27, 2006 Altera APEX EP20K600CB652C8ES Programmable Logic Device Structural Analysis Table of Contents List of Figures...Page 1 Introduction...Page 4 Device Summary...Page 5 Device Identification Package and Assembly Analysis Major Microstructural Features Transistor Microstructural Analysis Microstructural Material Analysis Memory Cell Analysis Report Evaluation For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. Rev. 1.0
Altera APEX EP20K600CB652C8ES PLD Structural Analysis Page 1 List of Figures Device Identification 1-1 & 1-2 Package Markings 1-3 Package X-Ray 1-4 Die Photograph 1-5 &1-6 Die Markings 1-7 Die Corners 1-8 Bond Pad Layout 1-9 Etch Uniformity Patterns and Fuses Package and Assembly Analysis 2-1 3-D Views of Package 2-2 Details of Solder Balls 2-3 Details of Trace Patterning 2-4 Section of Package 2-5 Section of Package Structures 2-6 Section Details of Package Structures 2-7 Section of Solder Balls 2-8 Section of Stitch Wirebonds 2-9 SEM of Die and Leadframe Wirebonds Major Microstructural Analysis 3-1 & 3-2 FESEM Micrograph of General Structure 3-3 FESEM Micrograph of Stacked Via Structures 3-4 FESEM Micrograph of Bonding Pad Structure 3-5 FESEM Micrograph of Edge Seal 3-6 FESEM Micrograph of Metal 6 3-7 FESEM Micrograph of Metal 6-to-Metal 5 Vias 3-8 FESEM Micrograph of Metal 5 3-9 FESEM Micrograph of Metal 5-to-Metal 4 Vias 3-10 FESEM Micrograph of Metal 4
Altera APEX EP20K600CB652C8ES PLD Structural Analysis Page 2 3-11 FESEM Micrograph of Metal 4-to-Metal 3 Vias 3-12 FESEM Micrograph of Metal 3 3-13 FESEM Micrograph of Metal 3-to-Metal 2 Vias 3-14 FESEM Micrograph of Metal 2 3-15 FESEM Micrograph of Metal 2-to-Metal 1 Vias 3-16 FESEM Micrograph of Metal 1 3-17 FESEM Micrograph of Metal 1 Contacts 3-18 FESEM Micrograph of Metal 1-to-Diffusion Contacts 3-19 FESEM Micrograph of Poly Features 3-20 FESEM Micrograph of P-channel Transistors 3-21 FESEM Micrograph of N-channel Transistors 3-22 FESEM Micrograph of N-channel Transistor and Sidewall Spacers 3-23 FESEM Micrograph of STI/Gate Oxide Transition and Well Structure Transistor Microstructural Analysis 4-1 Optical and SEM section views of well structure and CMOS gates 4-2 SEM section views of N-channel transistors 4-3 SEM section views of P-channel transistors 4-4 SEM section views illustrating salicide structures 4-5 TEM section views illustrating overall device structure 4-6 TEM section views illustrating M1 contact structure and gate structure 4-7 TEM view of a typical poly gate 4-8 TEM detail view of a poly gate Microstructural Material Analysis 5-1a SIMS depth profile through dielectric layers 5-1b Spreading resistance profile through an N-well 5-2b Spreading resistance profile through a P-well 5-3b Spreading resistance profile through portion of substrate indicating no epi layer 5-4b Spreading resistance profile through field oxide region indicating apparent field implant 5-1c EDS spectrum of copper metallization
Altera APEX EP20K600CB652C8ES PLD Structural Analysis Page 3 5-2c EDS spectrum of metal liner (tantalum) 5-3c EDS spectrum of tungsten plugs 5-4c EDS spectrum of plug liner (titanium) 5-5c EDS spectrum of cobalt silicide on gate and S/D Memory Cell Analysis 6-1 Optical views of a memory block from the ESB (Embedded System Block) 6-2 Topological SEM views of memory cells from the ESB 6-3 Topological SEM views of memory cells from the ESB 6-4 Perspective SEM views of memory cells from the ESB 6-5 Topological SEM views of a memory cell from the ESB 6-6 Topological SEM view and schematic of a memory cell from the ESB 6-7 Optical views of memory cells from the MultiCore Architecture 6-8 Topological SEM views of memory cells from the MultiCore Architecture 6-9 Topological SEM views of memory cells from the MultiCore Architecture 6-10 Perspective SEM views of memory cells from the MultiCore Architecture 6-11 Topological SEM views of a memory cell from the MultiCore Architecture 6-12 Topological SEM view and schematic of a memory cell from the MultiCore Architecture
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