TWO AND ONE STAGES OTA

TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +39-38-50505; fax. +39-038-505677 474 EE Department Texas A&M University 1

FUNDAMENTAL OF OPERATIONAL AMPLIFIER The ideal operational amplifier is a voltage controlled voltage source with infinite gain, infinite input impedance and zero output impedance. + _ A(v - v ) + In all applications the op-amp is used in feedback configuration. 474 EE Department Texas A&M University

The feedback configuration: Z V 1 Z 1 Z 3 _ V V 0 + Z 4 V 0 V -------------------- Z Z 4 1 + Z Z = -------------------- V Z 1 ------ Z 3 + 4 Z 1 Z 1 If the gain of the op-amp is not infinite, an error of the order of 1/A results. This error must be smaller or comparable to the impedance matching. 474 EE Department Texas A&M University 3

If impedances are implemented with capacitors and switches, it result that, after a transient, the load of the op-amp is made of pure capacitors. Their voltage can be obtained with stages having high output resistance (transconductance operational amplifier). C _ - Q δ(t) + g v m i r 0 C0 v 0 ( 0 + Q ) = ------ v i ( 0 + 1 ) = Q ------ C 0 C 0 1 + --- C V i ( t ) = V 0 ( t ) Q ---- C 474 EE Department Texas A&M University 4

g m v 0 ( ) Q ---- C v 0 ( ) = --------------- v 0 ( ) r 0 = Q g m r 0 ---- ----------------------- C 1+ g m r 0 The output resistance must be high in order to have v 0 ( ) Q --- C Q + C g v m i r 0 C0 v 0 ( t ) = v o ( 0 + ) + [ v 0 ( ) v 0 ( 0 + )][ 1 e t τ ] v (t) 0 C τ ------- g m t 474 EE Department Texas A&M University 5

PERFORMANCE CHARATCTERISTICS Actual op-amps deviate from ideal behavior. The differences are described by the performance characteristics. DC differential gain: is the open loop voltage gain measured at DC with a small differential input signal. Typically A d = 80-100 db v in vout + 474 EE Department Texas A&M University 6

Common mode gain: is the open loop voltage gain with a small signal applied to both the input terminals. A cm = 0-40 db. v out v in + Common mode rejection ratio: is defined as the ratio between the differential gain and the common mode gain. Typically CMRR = 40-80 db 474 EE Department Texas A&M University 7

Power supply rejection ratio: if a small signal is applied in series with the positive or negative power supply, it is transferred to the output with a given gain A ps + (or A ps -). The ratios between differential gain and power supply gains furnish the two PSRRs. + o v =A v ps ps v ps Typically: PSRR = 90 db (DC) PSRR = 60 db (1KHZ) PSRR = 30 db (100 KHZ) 474 EE Department Texas A&M University 8

Input offset voltage: in real circuits if the two input terminals are set at the same voltage the output saturates close to V DD or to V SS. Offset compensates the effect. Typically V os = 5-15 mv v os + v out Input common mode range: it is the maximum range of the common mode input voltage which do not produce a significant variation of the differential gain. 474 EE Department Texas A&M University 9

Output voltage swing: is the swing of the output node without generating a defined amount of harmonic distortion. Equivalent input noise: The noise performances can be described in terms of an equivalent voltage source at the input of the op-amp. Typically V n = 40-50 nv/ Hz at 1 khz; in a wide band (1MHz) it results 10-50 µv RMS v n v [db] n + v out log(f) 474 EE Department Texas A&M University 10

Unity-gain bandwidth (f t ): is the frequency at which the open loop gain is zero. It is also the -3 db bandwidth for unity-gain closed loop conditions. Typically f t = 0 MHz Slew rate: + v out it is the maximum slope of the output voltage for a steply signal applied at the input. Usually measured with the op-amp in the buffer configuration. The positive slew rate can be different from the negative slew rate, depending on the specific design. Typically 5-0 V/µsec. For micropower operations they drops to much lower levels. [db] A 0 f T log(f) + v out v out slope t 474 EE Department Texas A&M University 11

Settling time: if the phase margin is not good enough the response to an input step can be affected by some ringing. The settling time is the time required to settle the output within a given range (usually ± 0.1%) of the final value. Power dissipation: it depends on the request of speed and bandwidth of the circuit. Typically, for 5 V supply, is around 1 mw. For lower supply the power consumption doesn t scale proportionally 474 EE Department Texas A&M University 1

Technology Supply voltage DC gain gain-bandwidth Slew rate Settling time 1V, Cl=4pf CMRR PSRR, DC PSRR, 1 khz PSRR, 100 khz Offset Input common range Output swing Input referred noise Power dissipation 0.8 µm CMOS 3.3 V 80 db 0 MHz 5 V/µsec 400 n sec 40 db 90 db 60 db 30 db 6 mv V.5 V 100 nv/ Hz at 1 khz 1 mw Area 100 x 100 µm 474 EE Department Texas A&M University 13

Differ. Gain Differ. S. End. nd gain Stage Output Stage Basic Op-Amp Internal Functions Key requirement: Need absolute stability in unity gain closed loop conditions when driving maximum load. Use minimum number of gain stages. 474 EE Department Texas A&M University 14

Two stages op-amp (transconductance) MB M7 M6 I Ref M1 M C c Out M3 M4 M5 Key design issue: Open loop DC gain DC offset PSRR 474 EE Department Texas A&M University 15

Open loop DC gain: g m1 g K ----- W W ----- m5 L 1 L 5 A v = A 1 A = ------------------------------ ------------------------------ -------------------------------- = g ds + g ds4 g ds5 + g ds6 I 7 I 6 K ----- W W ----- L 1 L 5 ------------------------------------- W W I Ref ----- ----- L 7 L 6 DC offset: The input offset is composed of two terms: Systematic offset Random offset 474 EE Department Texas A&M University 16

Systematic offset: It is assumed that the device are perfectly matched. The systematic offset can be reduced to zero with a careful design. For zero input differential signal the scheme is equivalent to: MB 1/ M7 M6 I Ref M1 M3 M5 Out The transistors M6 and M7 must operate is saturation. Hence: ( W L) 3 -------------------- = ( W L) 5 1 -- ( W L) 7 -------------------- ( W L) 6 474 EE Department Texas A&M University 17

Random offset: Due to the geometrical mismatching and process dependent inaccuracies. v os1 -A 1 v os -A v os v os = v os1 ---------- v os1 A 1 Dominated by the offset of the input stage Higher than bipolar counterpart 474 EE Department Texas A&M University 18

For zero input signal, the output is: R R 1 + - I I V = I 1 R I R = I -- R V is neutralized with an input offset voltage such that: gm1r 0 v 0s 1 I = V v 0s = -- --------- ------- R g m1 R 0 474 EE Department Texas A&M University 19

Bipolar: Mosfet: Assuming: it results: I ------- g m = I ------- 6mV g m V GS V Th ---------------------------- 150 300mV R ---------- = 0.01 R 0 v os, bip = 0.6mV v os MOS, = 1.5 3mV 474 EE Department Texas A&M University 0

Power supply rejection: + v n V DD MB M7 M6 I Ref M1 M C c Out - v n 3 M3 M4 4 M5 V DD A signal on the positive bias line determines a modulation in the reference current, which, in turn, gives an equal modulation of the currents in M 5 and M 6 if the condition of the zero systematic offset is fulfilled. 474 EE Department Texas A&M University 1

A signal on the negative bias line is divided by the network made by M 7, M 1, M 3. The signal on node 4 (by symmetry equal to the one on 3) is given by: v 4 = v - v - ------------------------------------------------------ 1+ g m1 g m3 r ds1 r ds7 v gs5 = v - v 4 v 0 v v gs5 A - A = = -------------------------------------------- g m1 g m3 r ds1 r ds7 The DC PSRR is usually larger than the DC gain. At high frequency the PSRR is determined only in the second stage The impedance of the compensation capacitances C c decreases, resulting an effective shorting of gate to drain of M 5. 474 EE Department Texas A&M University

V DD n r ds6 v - n M5 It results: v out ---------- + v n = 1 g m5 ----------------------------------- 1 g m5 + r ds6 v out ---------- - v n = r ds6 ----------------------------------- 1 1 g m5 + r ds6 The negative supply PSRR is approximately 0 db at the unity gain frequency of the op-amp. 474 EE Department Texas A&M University 3

Coupling through the virtual ground Gives an high frequency contribution to the PSRR when the op-amp is used as integrator. V DD C + C I Due to the capacitive coupling between power supply lines and the input led. C - + v out + - v 0 = [ αv n βv n ] V SS Put input transistors in well attached to source. The body effect, which changes V Th, hence V GS, is eliminated. Careful layout: no crossover, shielding. 474 EE Department Texas A&M University 4

FREQUENCY RESPONSE AND COMPENSATION A two gain stages scheme with poles in the same frequency range needs compensation. A single pole system is always stable. Strategy: approach single pole performance by splitting the two poles apart. P1 C c P I1 I 474 EE Department Texas A&M University 5

Miller capacitance moves p 1 at lower frequency. Shunt feedback moves p ar higher frequency Small signal equivalent circuit for two stages operational amplifier. C v c v 1 0 g v m1 in R 1 C 1 g v m 1 R C v 1 ( g 1 + sc 1 ) + ( v 1 v 0 ) sc c + g m1 v in = 0 v 0 ( g + sc ) + ( v 0 v 1 ) sc c + g m v 1 = 0 sc 1 c ---------- V 0 g m -------- = g V m1 R 1 g m R ----------------------------------------------------------------------------------------------------------------------------------------- in 1+ sr 1 R g m C c + S R 1 R [ C 1 C + ( C 1 + C ) C c 474 EE Department Texas A&M University 6

The circuit displays two poles and a zero in the right half plane. 1 p 1 --------------------------------- p g m R R 1 C -------------------------------------------------------- g m C c c C 1 C + ( C 1 + C )C c z = + g m --------- since in practice C c > C 1 ; C c C and g m1 > 1/R 1 ; g m > 1/R it results: C c 1 g m p 1 «-------------- p R 1 C ---------» 1 C 1 -------------- R C Assuming p 1 as dominant, the unity gain angular frequency w T is: 1 g ω T = p 1 A 0 = --------------------------------- g g m R R 1 C m1 g m R 1 R = m1 --------- c C c 474 EE Department Texas A&M University 7

The locations of the second pole p and of the zero with respect to w T are derived by considering: p ------- ω T = g m C c --------- ------ g m1 C for stability > to 4; z ------- ω T = g m --------- g m1 474 EE Department Texas A&M University 8

if C c > C and g m > g m1 A [db] log(f) with left half-plane zero Φ log(f) -90-180 -70 The right half-plane worsen the phase margin. In bipolar technology g m >> g m1 because the current in the second stage is normally higher than the one in the first stage. 474 EE Department Texas A&M University 9

In CMOS technology because is proportional to the square root of I; moreover, the transconductance of the input pair must be high in order to reduce their thermal noise contribution. In real situations the obtainable phase margin does not guarantee the stability. Eliminating right half-plane zero: Source follower Zero nulling resistor The zero is due to a signal feedforward to a point that is 180 out of phase I 474 EE Department Texas A&M University 30

Solution: eliminate feedforward with a source follower 1 I I Disadvantages: Area Power dissipation Actually creates a doublet in the feedback path. Potentially not stable. Alternative, a substrate emitter follower may be used. (The bipolar transistor is smaller and has higher g m ) 474 EE Department Texas A&M University 31

Zero nulling resistor: Zero s position is pushed away with a resistance in series with C c 1 R z C c It results: V 0 A 0 [ 1+ s( R z 1 g m )C c ] -------- ---------------------------------------------------------------------- V in s 1 + ----- s 1 + ----- p 1 p 474 EE Department Texas A&M University 3

The pole locations are closed to the original The zero is moved depending on R z z = 1 ------------------------------------- 1 C c --------- R z g m If R z = 1/g m the zero is moved at the infinite If R z = 1/g m the zero is located in the left half-plane Implementation: V DD 1 1 g m = ------ + ------ R n R p V 1 V 0 V SS 474 EE Department Texas A&M University 33

In non saturation: 1 ------ = k' W R n ----- n L n [ V DD V 1 V Th, n ] 1 ------ = k' W R p ----- p L p [ V 1 V ss V Th, p ] Choose ----- and ----- such that: and: W L n W L p k' W n ----- L n = k' W p ----- L p g m = k n W ----- L n [ V DD V SS V Th, n V Th, p ] Problem: Supply sensitivity. Since the swing of the node 1 is A less than the output swing, only one transistor with supply independent bias can be used. 474 EE Department Texas A&M University 34

SLEW RATE M3 M4 M5 M1 M C c IB1 IB C L (C L includes the feedback capacitor) For large input signal: M 1, M 4 are off so the current I B1 charges C c through M. Assuming M 5 able to drive the current request by C c, C L and I B V SR + + = ---------- = t max I B1 ------- C c 474 EE Department Texas A&M University 35

M, M 5 are off so the current I B1 mirrored by M 4 discharges C c ; C L is discharged by I B V SR - - = --------- = t max I B --------------------- C c + C L In order to have SR+ = SR- it must be: I B1 ------- C c = I B --------------------- C c + C L Since ω T = g m1 --------- C c, it results I B1 SR = --------- ω T = ( V GS1 V Th ) ω T g m1 For ω T = π 5 10 6, (V GS - V Th ) = 600 mv, SR 10 V/µsec. 474 EE Department Texas A&M University 36

SINGLE STAGE SCHEMES High gain is get with a cascode scheme. Telescopic cascode Mirrored cascode Folded cascode 474 EE Department Texas A&M University 37

Telescopic cascode: J DC gain (g m r ds ) J J L L Low power consumption Only one high impedance node: compensated with a capacitance load (if necessary) Low output swing Reference of the input close to the negative supply L Two bus lines (V B1, V B ) L 5 Transistors in series V B1 M7 M8 M5 M6 M3 M4 + _ M1 M V B M9 474 EE Department Texas A&M University 38

Mirrored cascode: J Optimum input common mode M10 M11 M1 M13 J J range Only 4 transistors in series Improved output swing V B1 M3 + _ M1 M M4 Out L L Speed of the mirror Higher power consumption V B M5 M7 M9 M6 M8 V outmax = V B1max + V GS4 V sat V B1max = V DD V sat V GS4 V outmax = V DD V sat V outmax = V GS7 + V sat 474 EE Department Texas A&M University 39

Conventional Folded cascode: M10 M11 V B3 _ M1 M + M3 M4 V B1 M5 M6 Out V B M9 M7 M8 474 EE Department Texas A&M University 40

Modified Folded cascode: M10 M11 V B3 _ M1 M + M3 M4 V B1 M5 MA M6 Out V B M9 M7 M8 MB Modified in order to improve the going down output swing 474 EE Department Texas A&M University 41

TWO STAGES AMPLIFIER VS SINGLE STAGE AMPLIFIER Two stages: J J J L L Voltage gain less affected by resistive loading Maximum signal swing Less bussing of bias lines Requires additional capacitor for frequency compensation More power consumption 474 EE Department Texas A&M University 4

Single stage: J J J No need for additional compensation capacitor Lower power consumption Better CMRR L L Lower signal swing More bussing of bias lines 474 EE Department Texas A&M University 43

CLASS AB AMPLIFIER Class AB: a circuit which can have an output current which is larger than its DC quiescent current. Two stages amplifier with class AB second stage M 6 and M 7 act as a level shifter M 8 and M 9 act as a class AB push-pull amplifier M3 M1 M4 M M6 M8 M9 g A m8 + g m9 = ------------------------------ + g ds8 g ds9 VB M5 M7 474 EE Department Texas A&M University 44

The quiescent current in the output stage is bias voltage and technological variation dependent. neglecting the body effect: V DD = V GS8 + V GS6 + V GS9 V DD ------ L k' ----- L + I n W 6 + ------- 6 k' ----- I + p W 8 = V Th, p V Th, n + ------ L k' ----- n W I 9 I = L V DD V Th, p V Th, n ------ k' ----- n W --------------------------------------------------------------------------------------------------- ------- L k' ----- L + ------ p W 8 k' ----- n W 9 I 6 6 Typically with V DD = 5V the numerator is around 1.6 V; if it is assumed V DD = (5 ± 0.5)V and DV Th = ± 00 mv, it results that the numerator can change from 0.7 V to.5 V; hence, I min = 0.3 I nom ; I max =.5 I nom 474 EE Department Texas A&M University 45

Single stage class AB amplifier (only inverting) The input pair M 1 and M operate source followers and it drives the common gate stages M 3 and M 4 M5 M6 I B V B = V Th, n + V Th, p + V ov, n + V ov, p M7 V B for V in = 0 M M3 V B I 1 = I = I Bias M1 M4 V B for V in > 0 I 1 and I M10 I out = K 89, I 1 K 56, I K 8,9 and K 5,6 mirror factors (assumed equal) M8 M9 V B I B 474 EE Department Texas A&M University 46

= + = V Th, n + V Th p + V B + V in V GS V GS4, ------ W k' ----- L n + k' ------- ----- W L p 4 I It results: = + = V Th, n + V Th p + V B V in V GS1 V GS3, k' ------ ----- W L n I out = K 89, ( I 1 I ) = αk 89, V B V in 3 + ------- W k' ----- L p 1 I 1 I out until I 1 or I goes to zero, for a larger V in, I out increases quadratically with V in V in 474 EE Department Texas A&M University 47

Small signal gain: A v = G m r out G m is the transconductance of the cross coupled input stage In M g m (v in - v A ) A A M4 -gm4 v A g m ( V in V A ) = g m4 V A V A = g m V in --------------------------- + g m g m4 I out g = g m4 V m g m4 A = --------------------------- V + in = G m V in g m g m4 474 EE Department Texas A&M University 48

FULLY DIFFERENTIAL SCHEMES The use of fully differential paths through analog signal processor gives benefits on: PSRR Dynamic range Clock feedthrough cancellation Consider an integrator and its fully differential version C C in R - in+ R + - out - + out in - R - + + out C 474 EE Department Texas A&M University 49

J J Noise from the power supply and clock feedthrough are common mode signal. The output swing is (V max+ - V max- = V max ) doubled. Since the noise is unchanged, the dynamic range improves by 6 db. L L L L Single ended to differential and double ended to single ended converters are necessary Larger area More bussing of bias lines Common mode feedback is necessary SE/DE Different. Processor DE/SE 474 EE Department Texas A&M University 50

The blocks SE/DE and DE/SE increase the complexity and introduce noise. Differential approach is convenient if the differential processor contains more than 4 stages. C C in R - in+ R + - - out + out in- R - + + out C The feedback around the op-amp control the difference of the input terminal voltages and not their mean value. In turn, there is no control on the output common mode voltage. 474 EE Department Texas A&M University 51

M10 M11 V B3 _ M1 M + Out- M3 M4 V B1 Out+ M5 M6 V B M9 M7 M8 V B4 V B5 + + CMFB V B or V B3 or V B5 474 EE Department Texas A&M University 5

Continuous time Sampled data Continuous time feedback: COMMON MODE FEEDBACK V B M3 I out V+ V M1 M - 474 EE Department Texas A&M University 53

V B is such that M 1 and M are in the linear region; (W/L) 1 = (W/L) M 1 and M are like the parallel of two voltage dependent resistance 1 I 1 = -- k' W ----- L 1 [ V ( + V Th )V DS V DS ] 1 I = -- k' W ----- L 1 [ V ( - V Th )V DS V DS ] 1 I out = I 1 + I = -- k' W ----- L 3 [ V B V DS V Th ] With a differential signal I out = cost With a common mode signal: for positive, I out increase for negative, I out decrease 474 EE Department Texas A&M University 54

FULLY DIFFERENTIAL FOLDED CASCODE WITH CMFB V B1 M9 M10 + _ M1 M V B Out - M3 M4 Out + V B3 V B3 V B5 M5 M7 M6 M8 V CM M11 M1 474 EE Department Texas A&M University 55

V B1 M9 M10 + _ M1 M Out _ V B M3 M4 Out + V B3 V B4 V B5 M5 M7 M6 M8 M11 M1 474 EE Department Texas A&M University 56

Problems: Dynamic range Linearity Compensation of the non linearities of the n-channel and p-channel CMFB cell. V+ I I out V- 474 EE Department Texas A&M University 57

Simple data feedback: The common mode feedback operates on slowly variable signal. It can be implemented at discrete time interval. The sampled data feedback is essential for low bias voltage and low power. J J J Lineartity (mean value with capacitors) Low power consumption No limitation to the dynamic range I Ref 1 C 1 1 C V+ V- C' I Out L L Clock phases necessary Clock feedthrough effect V CM 1 474 EE Department Texas A&M University 58

MICROPOWER OP-AMPS Required in battery operated system (pocket calculators, pace makers, hearing aids, electronic telephone,...) Consumption < 1 µa Use of MOS transistors in weak inversion (subthreshold) Low current has, as consequence, low slew rate. C 1 1 B M5 M3 M4 M6 M1 M M7 1 B/C M8 474 EE Department Texas A&M University 59

AMPLIFIER WITH ADAPTIVE BIAS M3 M4 M5 M6 D(I -I ) 1 D(I -I 1 ) M1 M M7 M8 1 D 1 D I B Basic idea: Generate I 1 - I and increase the current in the differential stage by D I 1 - I. 474 EE Department Texas A&M University 60

Since I 1 - I = α [I 0 +D I 1 - I ]: I 1 I = αi 0 ----------------- 1 Dα For transistors in weak inversion α = v i tanh-------------- nv T The increase of the current in the differential stages becomes significant around: Typical performances DC gain 95 db f t 130 khz SR 0.1 V/µ sec I 0 0.5 µa I tot.5 µa v i D tanh-------------- = 1 nv T 474 EE Department Texas A&M University 61

CLASS AB SINGLE STAGE WITH DYNAMIC BIASING M7 M8 Bias3 Bias1 Out+ In+ M M3 In- Out- M1 M4 Bias4 Bias M5 M6 In order to have a maximum output swing the bias voltages BIAS 1 - BIAS must be kept as close as possible to the bias voltages 474 EE Department Texas A&M University 6

During the slewing the current source of the output cascodes can be pushed in the linear region, hence loosing the advantage of the AB operation. The problem is solved with the dynamic biasing M7 M8 M M3 M1 M4 Out- Bias M5 M6 474 EE Department Texas A&M University 63

NOISE The noise of an operational amplifier is described with an input referred voltage source V n. The spectrum of V n is made of a white term and 1/f term. V n is due to the contributions, referred to the input, of the noise generators associated to all the transistors of the circuit (assumed uncorrelated). 474 EE Department Texas A&M University 64

consider the input stage of a two stages op-amp. M3 v n3 v n4 M4 v n1 M1 M v n M5 The output noise voltage is given by: V n, out = 1 [( V n1 + V n)gm1+ ( V n3 + V n4) gm3 ] ------------------------------ + g ds g ds4 474 EE Department Texas A&M University 65

Where it is assume g m1 = g m ; g m3 = g m4 (it is assumed that the noise source of M5 does not contribute) moreover since usually W 1 =W ; L 1 = L ; W 3 =W 4 ; L 3 =L 4 ; V n1 = V n; V n3 = V n4; if we refer V n,out to the input, we get: V nout V -------------- = V n, out n, in = ---------------- ( g ds + g ds4 ) = V n1 A 1 g m1 + --------- g m3 g m1 V n3 The contribution of the active loads is reduced by the square of the ratio g m3 /g m1 It is worth to remember that g m = W µc ox -----I L K F 8 V n -- ------- kt -------------------- 1 = + 3g m µc -------- f WL ox 474 EE Department Texas A&M University 66

The attenuation by the factor (g m3 /g m1 ) gives, for the white term: V n, in, ω g m3 = V n1 1 + --------- g m1 = V n1 1 + µ 3 I 3 W L3 --------------------------- µ 1 I 1 W L1 and for the 1/f term: Where K F1 and K F are the flicker noise coefficient of the type of transistor of which M 1 and M 3 are made. The white contribution of the active load is reduced by choosing (W/L) input >> (W/L) load The 1/f noise contribution of the active load is reduced by choosing L input < L load K = ----------------------------------- µ 1 C 1 F3 I 3 L 1 + ---------------------- oxw 1 L 1 K F1 I 1 L 3 K V F1 n, in, 1 f If the above conditions are satisfied the input noise is dominated by the input pair. 474 EE Department Texas A&M University 67

Cascode scheme: The noise is contributed by the input pair and the current sources of the cascode load v n4 M4 M3 Out M V n, in = V + g m4 n1 --------- V n4 g m1 M1 v n1 I1 474 EE Department Texas A&M University 68

Folded Cascode scheme: M M1 v n1 M3 Out M4 I1 M5 v n5 The noise contributed by the same source as in the cascode and by the current source M V n, in = V + g m n1 --------- V g m5 n --------- + V n5 g m1 g m1 474 EE Department Texas A&M University 69

Two stages amplifier: (feedforward + zero nulling compensation) C c R z Out v n1 + g v m1 i1 r 1 v n C1 + g v m i r C The noise is modelled with two input referred noise sources: one at the input of the first stage and the other at the input of the second stage. 474 EE Department Texas A&M University 70

vout [db] p 1 p v n1 log(f) v out v n [db] p 1 p log(f) 1/ A v1 In the low frequency range the noise is dominated by V n1. In the high frequency range the noise is dominated by V n. 474 EE Department Texas A&M University 71

Frequency response: The input referred noise generator is transmitted to the output as a conventional input signal The feedback network around the op-amp must be taken into account. One stage amplifier: Out The cutoff frequency is: v n + g v m i r 0 C0 p 1 = -g m /C 0 v out [db] p 1 v n log(f) 474 EE Department Texas A&M University 7

Power of the noise: We consider only the white term. One stage amplifier: V n0 V n df = --------------------------- = α 8 0 1+ s p 3 --kt 1 0 1 --------- g ------------------------------------------------ df α 8 m1 1+ ( πfc 0 g m1 ) 3 --kt 1 dx = ------------- πc 0 -------------- 0 1+ x = 4 --α ------ kt 3 C 0 Two stages amplifier: we consider only the white term contributed by the noise source of the second stage. V n = 8 α' -- --------- kt V 3 n0 g m = V 0 n df --------------------------- 1+ s p p = g m ------------------- C 1 + C 4 V n0 = kt --α' ------------------------ 3 ( C 1 + C ) 474 EE Department Texas A&M University 73

Rules: LAYOUT Use poly connection only for signal, never for current because the offset RI 15 mv. Minimize the line length, especially for lines connecting high impedance nodes (if they are not the dominant node). Use matched structure. If necessary common centroid arrangement. Respect symmetries (even respect power devices). Only straight-line transistors. Separate (or shield) the input from the output line, to avoid feedback. Shielding of high impedance nodes to avoid noise injection from the power supply and the substrate. Regular shape and use a layout oriented design. 474 EE Department Texas A&M University 74

Stacked layout: C sb = C db = C jb Wd ( + x j ) Structure A: d w Source L Drain 1 C sb = --C db = W C jb ---- ( d+ x j ) w Drain Structure B: w/ Drain Source w/3 Drain W C sb = C db = C jb -------- ( d+ x 3 j ) Source Source Drain Drain Source A B 474 EE Department Texas A&M University 75

Capacitances are further reduced if the diffusion area is shared between different transistors Key point: use of equal width transistors (or part of transistors) Transistors with arbitrary width are not allowed Placement and routing: If we divide a transistor in an odd number of parallel transistors the resulting stack has the source on one side and the drain on the other side If we divide a transistor in an even number of parts the resulting stack has source or drain on the two sides. Drain Source Drain Source Drain Drain Source Drain Source 474 EE Department Texas A&M University 76

Example: 1 150 00 00 150 3 4 5 1 1 3 1 3 1 4 1 4 1 5 1 5 474 EE Department Texas A&M University 77

Routing into stacks: use of comb connections or serpentine connections. 474 EE Department Texas A&M University 78

Fully differential folded cascode. Example Features, symmetry, common centroid input pair, minimum mine length. VB1 M9 M10 9 3 3 9 10 4 4 10 + _ M1 M _ Out VB M3 4 4 M4 Out + 1 1 1 1 V B3 V B4 M5 M13 M6 11 13 13 13 13 13 13 1 V B5 M7 M11 1 6 1 M1 M8 7 5 5 7 8 6 6 8 474 EE Department Texas A&M University 79

VDD VB1 V B V + V _ VB4 VB5 VB3 VSS 474 EE Department Texas A&M University 80