MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Power Module> TYPE TYPE INTEGRATED POWER FUNCTIONS 600/5A low-loss 5 th generation IGBT inverter bridge for three phase DC-to-AC power conversion. Open emitter type. INTEGRATED DRIE, PROTECTION AND SYSTEM CONTROL FUNCTIONS r upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (U) protection. r lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (U), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a U fault (Lower-side supply). Input interface : 3,5 line CMOS/TTL compatible. (High Active) UL Approved : Yellow Card No. E80276 APPLICATION AC100~200 inverter drive for small power motor control. Fig. 1 PACKAGE OUTLINES Dimensions in mm TERMINAL CODE 3 (0~5 ) 28 27 26 25 29 30 1.778 26 (=46.228) 1.778 ±0.15 24 23 22 21 20 19 35 34 37 36 33 32 31 18 16 1513 1210 987 654 321 17 14 11 (φ2 DEPTH 2) Type name, Lot No. 6.7 7.62 7.62 7.62 2.54 2.54 (41) 42 ±0.15 49 C B 0.8 A B 5 HEAT SINK SIDE φ3.3 15.25 9 (22.1) (17.6) (17.6) 17.4 17.4 (6.5) 4.5 (3.5) (1.5) D 35 1.2 1.25 2.5 HEAT SINK SIDE 1.75 (φ3.8) φ3.3 B-B 3.556 1.2 NO SOLDER PLATING ON BOTH LEAD SIDE TERMINAL 0.8 (0.05) (0.7) (0.05) 0.8 DETAIL C (36 TERMINAL) 3.556 (2.056) All outer lead terminals are with Pb-free solder plating. (1) (1.5) (ex. PCB LAYOUT) Note1) DETAIL A (1.5) (1) (0.278) () (R0.75) PCB PATTERN SLIT 1 UFS 2 (UPG) 3 UFB 4 P1 5 (COM) 6 UP 7 FS 8 (PG) 9 FB 10 P1 11 (COM) 12 P 13 WFS 14 (WPG) 15 WFB 16 P1 17 (COM) 18 WP 19 (UNG) 20 NO 21 UN 22 N 23 WN 24 FO 25 CFO 26 CIN 27 NC 28 N1 29 (WNG) 30 (NG) 31 P 32 U 33 34 W 35 NU 36 N 37 NW DETAIL D Note 1 : In order to get enough creepage distance between the terminals, please take some countermeasure such as a slit on PCB.
MAXIMUM RATINGS (Tj = 25 C, unless otherwise noted) INERTER PART Symbol Ratings CC CC(surge) CES ±IC ±ICP PC Tj Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Applied between P-NU, N, NW Applied between P-NU, N, NW Tf = 25 C Tf = 25 C, less than 1ms Tf = 25 C, per 1 chip (Note 1) 450 500 600 5 10 16.7 20~+125 Note 1 : The maximum junction temperature rating of the power chips integrated within the is 150 C (@ Tf 100 C) however, to ensure safe operation of the, the average junction temperature should be limited to Tj(ave) 125 C (@ Tf 100 C). A A W C CONTROL (PROTECTION) PART Symbol Ratings D DB IN FO IFO SC Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Applied between P1-NC, N1-NC Applied between UFB-UFS, FB-FS, WFB-WFS Applied between UP, P, WP, UN, N, WN-NC Applied between FO-NC Sink current at FO terminal Applied between CIN-NC 20 20 ~D+ ~D+ 1 ~D+ ma TOTAL SYSTEM Symbol Ratings Self protection supply voltage limit D = 13.5~16.5, Inverter part CC(PROT) Tj = 125 C, non-repetitive, less than 2 (short circuit protection capability) Tf Module case operation temperature (Note 2) C Tstg iso Storage temperature Isolation voltage 60Hz, Sinusoidal, 1 minute, All connected pins to heat-sink plate 400 20~+100 40~+125 2500 C rms Note 2 : Tf measurement point Al Board Specification : Dimensions : 100 100 10mm, Finishing : 12s, Warp : 50~100µm Control Terminals 18mm 16mm FWDi Chip Al Board Groove IGBT Chip Temperature measurement point (inside the AI board) N W U Power Terminals P Temperature measurement point (inside the AI board) Silicon-grease should be applied evenly with a thickness of 100~200µm
THERMAL RESISTANCE Symbol Rth(j-f)Q Rth(j-f)F Junction to case thermal resistance (Note 3) Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) Note 3: Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of and heat-sink. Min. Limits Typ. Max. 6.0 6.5 C/W C/W ELECTRICAL CHARACTERISTICS (Tj = 25 C, unless otherwise noted) INERTER PART CE(sat) EC ton trr Symbol tc(on) toff tc(off) ICES Collector-emitter saturation voltage FWD forward voltage Switching times Collector-emitter cut-off current D = DB = 15 IC = 5A, Tj = 25 C IN = 5 IC = 5A, Tj = 125 C Tj = 25 C, IC = 5A, IN = 0 CC = 300, D = DB = 15 IC = 5A, Tj = 125 C, IN = 0 5 Inductive load (upper-lower arm) CE = CES Tj = 25 C Tj = 125 C Limits Min. Typ. Max. 0.60 1.60 1.70 1.50 1.20 0.30 0.40 1.30 0 2.10 2.20 2.00 1.80 0.60 2.00 0.80 1 10 ma CONTROL (PROTECTION) PART Symbol ID FOH FOL SC(ref) IIN UDBt UDBr UDt UDr tfo th(on) th(off) Circuit current Fault output voltage Short circuit trip level Input current Control supply under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage D = DB = 15 IN = 5 D = DB = 15 IN = 0 Total of P1-NC, N1-NC UFB-UFS, FB-FS, WFB-WFS Total of P1-NC, N1-NC UFB-UFS, FB-FS, WFB-WFS SC = 0, FO circuit pull-up to 5 with 10kΩ SC = 1, IFO = 1mA Tf = 20~100 C, D = 15 (Note 4) IN = 5 Trip level Tj 125 C Reset level Trip level Reset level CFO = 22nF (Note 5) Applied between UP, P, WP-NC, UN, N, WN-NC Limits Min. Typ. Max. 5.00 0.40 7.00 5 4.9 0.95 0.45 2 1.0 1.5 2.0 10.0 12.0 1 12.5 10.3 12.5 10.8 13.0 1.0 1.8 2.1 2.3 2.6 0.8 1.4 2.1 Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is less than 2.0 times of the current rating. 5:Fault signal is asserted corresponding to a short circuit or lower side control supply under-voltage failure. The fault output pulse width tfo depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 10-6 tfo [F]. ma ma ms
MECHANICAL CHARACTERISTICS AND RATINGS Mounting torque Weight Heat-sink flatness Mounting screw : M3 Recommended : 0.78 N m (Note 6) Min. 9 50 Limits Typ. 20 Max. 0.98 100 N m g µm Note 6: Measurement point of heat-sink flatness + Measurement location 3mm Heat-sink side + Heat-sink side RECOMMENDED OPERATION CONDITIONS CC D DB D, DB tdead fpwm IO Symbol PWIN(on) PWIN(off) NC Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Allowable r.m.s. current Allowable minimum input pulse width NC variation Applied between P-NU, N, NW Applied between P1-NC, N1-NC Applied between UFB-UFS, FB-FS, WFB-WFS r each input signal, Tf 100 C Tf 100 C, Tj 125 C CC = 300, D = DB = 15, P.F = 0.8, sinusoidal output Tf 100 C, Tj 125 C (Note 7) fpwm = 5kHz 200 CC 350, 13.5 D 16.5, 13.0 DB 18.5, 20 C Tf 100 C, N-line wiring inductance less than 10nH (Note 9) between NC-NU, N, NW (including surge) fpwm = 15kHz (Note 8) Below rated current Between rated current and 1.7 times of rated current Between 1.7 times and 2.0 times of rated current Min. 0 13.5 13.0 1 1.5 Note 7 : The allowable r.m.s. current value depends on the actual application conditions. 8:The input pulse width less than PWIN(on) might make no response. 9:IPM might not work properly or make response for the input signal with OFF pulse width less than PWIN(off). Please refer to Fig.5. Recommended value Typ. 0.3 5.0 300 15.0 15.0 Max. 400 16.5 18.5 1 20 3.5 3.2 5.0 / khz Arms
Fig. 2 THE INTERNAL CIRCUIT UFB UFS P1 HIC1 CC B IGBT1 Di1 P UP IN HO COM S U FB FS P1 HIC2 CC B IGBT2 Di2 P IN HO COM S WFB WFS P1 HIC3 CC B IGBT3 Di3 P IN HO COM S W LIC IGBT4 Di4 UOUT N1 CC NU IGBT5 Di5 OUT N UN N UN N WOUT IGBT6 Di6 WN WN NO NW NC GND CIN CFO NO CIN CFO
Fig. 3 TIMING CHART OF THE PROTECTIE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter) a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a6. Input L : IGBT OFF. a7. Input H : IGBT ON. a8. IGBT OFF in spite of input H. Lower-arms control input a6 a7 Protection circuit state SET Internal IGBT gate a2 a3 Output current Ic a1 SC a4 a8 Sense voltage of the shunt resistor SC reference voltage Error output a5 CR circuit time constant DELAY [B] Under-oltage Protection (Lower-arm, UD) b1. Control supply voltage rises : After the voltage level reaches UDr, the circuits start to operate when next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UDt). b4. IGBT OFF in spite of control input condition. b5. FO operation starts. b6. Under voltage reset (UDr). b7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state SET Control supply voltage D UDr b1 UDt b3 b6 b2 b4 b7 Output current Ic Error output b5
[C] Under-oltage Protection (Upper-arm, UDB) c1. Control supply voltage rises : After the voltage reaches UDBr, the circuits start to operate when next input is applied. c2. Normal operation : IGBT ON and carrying current. c3. Under voltage trip (UDBt). c4. IGBT OFF in spite of control input condition, but there is no FO signal output. c5. Under voltage reset (UDBr). c6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state SET UDBr Control supply voltage DB c1 UDBt c3 c5 c2 c4 c6 Output current Ic Error output High-level (no fault output) Fig. 4 RECOMMENDED CPU I/O INTERFACE CIRCUIT 5 line 10kΩ UP,P,WP,UN,N,WN MCU NC(Logic) Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the wiring impedance of the printed circuit board. The input section integrates a 2.5kΩ (min) pull-down resistor. Therefore, when using an external filtering resistor, pay attention to the turn-on threshold voltage. Fig. 5 WIRING CONNECTION OF SHUNT RESISTOR Wiring inductance should be less than 10nH. Equivalent to the inductance of a copper pattern with length=17mm, width=3mm, and thickness=100µm NC NO NU N NW Shunt resistor Please make the GND wiring connection of shunt resistor to the NO, NC terminal as close as possible.
Fig. 6 TYPICAL APPLICATION CIRCUIT EXAMPLE C1:Tight tolerance temp-compensated electrolytic type C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering C3 C2 C1 UFB UFS P1 UP HIC1 CC B IN HO P C2 C1 FB FS COM S U C3 P1 P HIC2 CC B IN HO CONTROLLER C3 C2 C1 WFB WFS P1 WP COM S HIC3 CC B IN HO COM S LIC UOUT W M C3 N1 CC NU 5 line OUT N UN UN N WN NC N WN GND WOUT NO CIN CFO Too long wiring here might cause short-circuit. NW C CFO CIN NO 15 line C4(CFO) A If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction. Shunt resistors Long GND wiring here might generate noise to input and cause IGBT malfunction. OR Logic + - + - + - ref ref ref B R1 C5 B R1 C5 B R1 C5 N1 Comparator External protection circuit Note 1 : To prevent the input signals oscillation, the wiring of each input should be as short as possible. (Less than 2cm) 2:By virtue of integrating an application specific type HIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. 3:FO output is open drain type. This signal line should be pulled up to the positive side of the 5 power supply with approximately 10kΩ resistor. 4:FO output pulse width is determined by the external capacitor between CFO and NC terminals (CFO). (Example : CFO = 22 nf tfo = 1.8 ms (typ.)) 5:The logic of input signal is high-active. The input signal section integrates a 2.5kΩ (min) pull-down resistor. Therefore, when using external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. 6:To prevent malfunction of protection, the wiring of A, B, C should be as short as possible. 7:Please set the C5R1 time constant in the range 1.5~2. 8:Each capacitor should be located as nearby the pins of the as possible. 9:To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 pins should be as short as possible. Approximately a 0.1~0.22µF snubber capacitor between the P-N1 pins is recommended. 10 : To prevent ICs from surge destruction, it is recommended to insert a Zener diode (24, 1W) between each control supply terminals. 11 : The reference voltage ref of comparator should be set up the same rating of short circuit trip level (sc(ref): min.0.45 to max.2). 12 : OR logic output level should be set up the same rating of short circuit trip level (sc(ref): min.0.45 to max.2).