MULTIPHASE voltage-controlled oscillators (VCOs) are

474 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 3, MARCH 2007 A 15/30-GHz Dual-Band Multiphase Voltage-Controlled Oscillator in 0.18-m CMOS Hsieh-Hung Hsieh, Student Member, IEEE, Ying-Chih Hsu, and Liang-Hung Lu, Member, IEEE Abstract A multiphase oscillator suitable for 15/30-GHz dual-band applications is presented. In the circuit implementation, the 15-GHz half-quadrature voltage-controlled oscillator (VCO) is realized by a rotary traveling-wave oscillator, while frequency doublers are adopted to generate the quadrature output signals at the 30-GHz frequency band. The proposed circuit is fabricated in a standard 0.18- m CMOS process with a chip area of 1.1 1.0 mm 2. Operated at a 2-V supply voltage, the VCO core consumes a dc power of 52 mw. With a frequency tuning range of 250 MHz, the 15-GHz half-quadrature VCO exhibits an output power of 8 dbm and a phase noise of 112 dbc/hz at 1-MHz offset frequency. The measured power level and phase noise of the 30-GHz quadrature outputs are 16 dbm and 104 dbc/hz, respectively. Index Terms Coplanar striplines (CPSs), frequency doublers, half-quadrature output phases, rotary traveling-wave oscillators. I. INTRODUCTION MULTIPHASE voltage-controlled oscillators (VCOs) are widely used in both wired and wireless communication systems. In the pursuit of increasing carrier frequencies and higher data rates to satisfy the emerging application standards, the implementation of high-frequency signal sources with multiple phases is of crucial importance. Due to the superior device characteristics, III V compound semiconductors were preferred in the realization of high-frequency oscillators [1], [2]. With recent advances in the deep-submicrometer fabrication technology, transistors with and beyond 100 GHz [3], [4] are available in a standard CMOS process. High-frequency CMOS VCOs have been proposed to operate at frequencies in tens of gigahertz. However, most of the reported circuits provide single-ended or differential oscillation signals [5] [10]. It is still a challenging task to implement quadrature-phase CMOS VCOs operating at millimeter-wave frequencies [11] [13]. In this paper, a fully integrated dual-band multiphase VCO is presented. Using a 0.18- m CMOS process, a prototype circuit is implemented to operate at the 15/30-GHz frequency bands. The proposed circuit architecture is described in Section II. Theoretical analysis and circuit design of the 15-GHz half-quadrature VCO and the 30-GHz quadrature VCO are presented in Manuscript received July 19, 2006; revised November 8, 2006. This work was supported in part by the National Science Council under Grant 94-2220- E-002-026 and Grant 94-2220-E-002-009. The authors are with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan, R.O.C. (e-mail: lhlu@cc.ee.ntu.edu.tw). Digital Object Identifier 10.1109/TMTT.2006.890518 Fig. 1. Proposed dual-band multiphase VCO architecture. Sections III and IV, respectively. The experimental results of the fabricated circuit are shown in Section V. II. VCO ARCHITECTURE In a conventional VCO topology, quadrature output phases are realized by two parallel-coupled LC-tank oscillators [14], [15]. Due to the simplicity in the circuit design, it is widely used for applications at multigigahertz frequencies. As the operating frequency increases beyond 10 GHz, the parasitics from the coupling transistors contribute additional capacitive loading to the LC tank. Consequently, a small inductance is required to maintain a high resonant frequency of the tank, which might cause significant offset in the oscillation frequency due to small deviations in the inductance value. Moreover, a large varactor is not preferred in high-frequency designs to compensate for the process variation. Therefore, it is not practical to implement a high-frequency multiphase VCO with the active coupling technique. In order to overcome the limitations on the multiphase VCO designs, a dual-band circuit architecture is presented. Fig. 1 shows the conceptual illustration of the proposed architecture, which is composed of a half-quadrature VCO at the fundamental frequency and four doublers to generate the quadrature phases at the second harmonic. Since the fundamental VCO is oscillating at half of the maximum operating frequency, the stringent restrictions on the circuit implementation are effectively alleviated, resulting in better performance in terms of the phase 0018-9480/$25.00 2007 IEEE

HSIEH et al.: 15/30-GHz DUAL-BAND MULTIPHASE VCO IN 0.18- m CMOS 475 Fig. 2. Schematic of the 15-GHz half-quadrature CMOS VCO based on a rotary traveling-wave oscillator. noise, tuning range, and output power. As for the quadrature outputs at the second harmonic, the additional noise contribution from the doublers can be minimized by careful circuit design such that a phase noise lower than what an oscillator at twice of the fundamental frequency would give can be achieved, especially for VCOs operating at frequencies close to the transistor cutoff. Therefore, the proposed architecture is employed to realize the 15/30-GHz dual-band multiphase VCO in a standard CMOS process. III. 15-GHz HALF-QUADRATURE VCO A. Circuit Topology To achieve the required half-quadrature output phases with low close-in phase noise, a rotary traveling-wave topology [16] is employed for the 15-GHz fundamental oscillator. Fig. 2 shows the complete schematic of the fully integrated VCO with all on-chip components. In this design, the oscillation frequency is determined by the resonator, which is composed of a coplanar stripline (CPS) structure and the capacitances from the transistors and the varactors. A cross-connection is included in the CPS to form a closed loop for the required reverse feedback. Since no termination is needed, limitations on bandwidth and impedance mismatch can be alleviated. In order to ensure the odd-mode operation of the CPS and to compensate for the loss from the resonator, four identical complementary cross-coupled inverters are utilized in a symmetric manner. Compared with all-nmos circuit implementations, the complementary architecture provides a higher transconductance at the same bias current. In addition, a more symmetric oscillation waveform can be obtained, resulting in a reduction in the up-conversion of noise for better phase-noise performance [17]. For an enhanced tuning range of the VCO circuit, pmos devices are used as the varactors in the resonator. Finally, the half-quadrature outputs of the fundamental oscillator are buffered by open-drain stages to drive the 50- load of the test instruments. B. Theoretical Analysis 1) Modeling: The CPS is a uniplanar transmission line, which has been widely used in microwave and millimeter-wave applications [18], [19]. With two adjacent metal lines running in parallel on the same substrate surface, the CPS possesses the advantages of low insertion loss, small dispersion, less discontinuity parasitics, and low sensitivity to the substrate thickness [18]. Since the resonator of the fundamental oscillator is realized by a CPS structure in a closed-loop form, a circuit model is introduced for the detailed analysis of the VCO. Fig. 3(a) illustrates the equivalent circuit of the unloaded CPS [20], where the parameters and are per-unit-length quantities. Note that represents the self-inductance of the individual metal lines and is the capacitance between these two lines. The CPS attenuation is modeled by and, accounting for the conductor and

476 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 3, MARCH 2007 approximation is used in (5) and (6) for simplification, resulting in (7) (8) Based on the unloaded CPS model, a distributed equivalent circuit of the rotary traveling-wave VCO including the lumped loading elements is constructed as shown in Fig. 3(b). Note that and represent the overall shunt capacitance and conductance per-unit-length, respectively, defining between the two metal lines. From the geometry of the proposed oscillator, and can be expressed as [22] (9) (10) Fig. 3. Distributed circuit model of: (a) the unloaded CPS and (b) the proposed rotary traveling-wave VCO. dielectric losses, respectively. Since the two metal lines are in close proximity, the mutual inductance is represented by the coupling coefficient. Based on the equivalent circuit, a small-signal analysis is performed to characterize the propagation parameters of the CPS for both even- and odd-mode operations. The even-mode operation corresponds to a common-mode signal. By equalizing the potential in both signal paths, the characteristic impedance and the propagation constant for even-mode operation can be derived as where and. Assuming that and, the low-loss approximation in [21] applies and (1) and (2) can be expressed as As for the odd-mode operation, it is analyzed by providing a differential signal in the CPS. The characteristic impedance and propagation constant are given by where (1) (2) (3) (4) (5) (6) and. Similar to the even-mode operation, the low-loss where is the length of the CPS segment between two consecutive cross-coupled inverters. Note that and are the parasitics from the cross-coupled inverters, while and account for the shunt capacitance and conductance from the varactors, respectively. Due to the use of the cross-coupled inverters, the signal propagating in the CPS of the oscillator is in the differential mode. Therefore, propagation parameters in the similar forms of (7) and (8) are derived for the rotary traveling-wave oscillator, and the resulting characteristic impedance and propagation constant are given by (11) (12) where and. The derivations in (11) and (12) are thus used for analysis and design of the 15-GHz halfquadrature VCO. 2) Start-Up Condition and Oscillation Frequency: The equivalent circuit of the rotary traveling-wave oscillator is shown in Fig. 4(a). By treating the circuit as a closed-loop feedback system, the startup conditions to initiate the VCO oscillation are given by (13) (14) where is the loop gain and is the oscillation frequency. In order to evaluate the startup conditions, is derived by breaking the loop between the points and. Fig. 4(b) illustrates the equivalent open-loop circuit model of the rotary traveling-wave oscillator. Note that the transconductance contributed from the cross-coupled inverters are modeled by ideal current sources to simplify the analysis while terminations with a characteristic impedance of

HSIEH et al.: 15/30-GHz DUAL-BAND MULTIPHASE VCO IN 0.18- m CMOS 477 Fig. 4. Equivalent: (a) closed- and (b) open-loop circuit model of the proposed rotary traveling-wave VCO. are included in the CPSs to sustain the propagation mode in the closed-loop case. As the wave propagates through the CPSs, amplified components are superimposed at the points where the cross-coupled inverters locate. For an odd-mode operation, the waves of the two lines have identical amplitude with a phase difference of 180. As a result, the voltage at the first inverter node can be expressed as (15) where is the transconductance provided by the inverter stage and represents the effective load impedance at the inverter output. Similarly, the voltages at the loading nodes of the following inverter stages can be expressed as (16) where and, and the voltage amplitude at point is given by (17) Finally, the loop gain of the rotary traveling-wave oscillator is defined as the ratio of and as (18) From (18), the startup conditions in (13) and (14) can be expressed as (19) (20) where is an arbitrary odd integer. Furthermore, the required transconductance and the fundamental oscillation frequency are determined by (21) (22) From (21), it is noted that the startup condition can be alleviated by increasing the characteristic impedance of the CPS. However, the line attenuation may increase with, as indicated in (12), due to the increasing value of at

478 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 3, MARCH 2007 Fig. 6. Schematic of the complementary cross-coupled inverters with a pmos tail current. TABLE I CIRCUIT PARAMETERS OF THE CROSS-COUPLED INVERTERS Fig. 5. Simulated results of: (a) the characteristics impedance and (b) the quality factor for the unloaded CPS at 15 GHz with various w and s. higher frequencies. A tradeoff has to be made in determining the CPS parameters and the transistor sizes for an optimum VCO design, especially for high-frequency applications. In the design of the rotary traveling-wave oscillator, varactors are included in the cross-coupled inverters to provide the required frequency tuning. By varying the equivalent capacitance of the varactors from to with the controlled voltage, the tuning range of the VCO can be estimated by C. Circuit Design (23) The design of the rotary traveling-wave oscillator starts with the geometry of the CPS structure. To minimize the conductor and the substrate losses, top metal layer with a thickness of 2 m provided by the CMOS technology is utilized for the implementation of the CPS. The most important design parameters for the CPS are the linewidth and the line spacing, which predetermine the values of and. Based on the full-wave electromagnetic (EM) simulation, the extracted values of the CPS parameters for various and at 15 GHz are shown in Fig. 5. In consideration of the -factor and the layout dimensions, a CPS structure with m, m is employed for the design. Once the width and the spacing of the CPS are determined, the required length can be estimated by (22). In this particular design, is chosen to be 250 m to achieve an oscillation frequency of 15 GHz. As for the inverter stages, the complementary cross-coupled pairs with a pmos tail current, as shown in Fig. 6, are adopted to compensate the losses of the resonator. The transistor sizes and bias currents are selected according to (21) to provide sufficient transconductance while maintaining minimum parasitic capacitance and reasonable power consumption. Table I summarizes the device parameters in this design. Due to the use of the complementary inverter stages, the overall capacitance in (23) is dominated by, leading to a reduced VCO tuning range at the fundamental frequency. With the design values utilized for the active and the passive components, the circuit parameters of the loaded CPS are extracted and summarized in Table II. From (21) (23), the calculated value for to satisfy the startup condition is 150 ma/v, while the estimated oscillation frequency ranges from 15.6 to 15.9 GHz. Compared with the circuit-level simulation, it is noted that the theoretical analysis provides a first-order prediction for the design of the rotary traveling-wave oscillators with sufficient accuracy.

HSIEH et al.: 15/30-GHz DUAL-BAND MULTIPHASE VCO IN 0.18- m CMOS 479 TABLE II EXTRACTED CIRCUIT PARAMETERS OF THE LOADED CPS Fig. 8. Small-signal equivalent circuit of the push push doubler. Fig. 7. Schematic of the quadrature VCO using push push doublers. and differential fundamental signals are applied to the input terminals of the push push stage, the drain currents of the transistors are given by IV. 30-GHz QUADRATURE VCO A. Circuit Topology With the half-quadrature output phases provided at the fundamental frequency, the 30-GHz quadrature VCO is realized by four push push stages as the frequency doublers. Complete circuit schematic of the frequency doublers are shown in Fig. 7. The generation of the harmonics is based on the nonlinear variation in the transconductance of the push push stages. To maximize the conversion gain, the transistors are in the commonsource configuration, while spiral inductors are employed for the purposes of output matching at the second harmonic frequency. The 15-GHz fundamental signals are directly coupled to the inputs of the push push stages without dc blocks or level shifters. In addition, open-drain buffers are used at the 30-GHz quadrature outputs to drive the 50- input impedance of the testing instruments. B. Theoretical Analysis 1) Conversion Gain and Phase Noise: In order to evaluate the output power at the second harmonic, the conversion gain of the frequency doublers is derived. Fig. 8 shows the schematic and the equivalent circuit of the frequency doubler. Considering that the drain current of a MOSFET is expressed by its Taylor series as (24) From (25) and (26), the ac current at the doubler output is (25) (26) (27) Note that the fundamental components are eliminated at the output node due to the push push operation, while the currents are constructively added at the second harmonic frequency. If the inductance value is chosen to resonate with the parasitic capacitance at 2, the conversion gain of the frequency doubler can be approximated by (28) By taking the velocity saturation into account, the drain current of a MOSFET in the saturation region is given by [23] (29) where is the threshold voltage, is the gate oxide capacitance per area, is the saturation velocity, is the mobility, is the mobility degradation factor, and and are the channel

480 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 3, MARCH 2007 Fig. 9. Simulated conversion gain of the doublers as a function of the gate bias voltage with various transistor aspect ratios width/length (W/L) (m/m). width and length, respectively. The coefficient series is derived as of the Taylor (30) Finally, the conversion gain of the frequency doubler can be obtained by plugging (30) into (27) as follows: Fig. 10. VCO. Microphotograph of the fabricated 15/30-GHz dual-band multiphase (31) Expression (31) provides a guideline for the design of the frequency doublers in terms of the conversion gain. In order to achieve a high conversion gain for enhanced output power at the second harmonic, MOSFETs with a large channel width and a minimum gate length are desirable, while a low overdrive voltage is required to maximize the nonlinearity of the devices. In addition to the conversion gain, the excess phase noise at the second harmonic output is also investigated. Provided a conversion gain of 0 db for the frequency doubler, the output phase noise is theoretically increased by 6 db in an ideal case [24]. However, due to the losses of the matching networks and the noise sources from the transistors, the noise power density at a specific offset frequency is generally higher than the theoretical prediction in a practical design. Furthermore, the output power level of the frequency doubler should be taken into account, as well in the evaluation of the phase noise at the second harmonic frequency. 2) Phase and Amplitude Errors in the Fundamental Inputs: In the derivations of the conversion gain, it is assumed that the fundamental signals are equal in amplitude with a phase difference of 180. However, the phase and amplitude errors due to device mismatch and layout asymmetry are inevitable in practical circuit implementations. The influence on the doubler performance is evaluated by introducing a phase error and an amplitude error in the differential signals at the fundamental frequency as Fig. 11. Measured and simulated tuning characteristics of: (a) the fundamental and (b) second harmonic outputs. From (32) and (33), the drain currents of the transistors are (32) (33) (34)

HSIEH et al.: 15/30-GHz DUAL-BAND MULTIPHASE VCO IN 0.18- m CMOS 481 Fig. 12. Measured: (a) output spectrum and (b) close-in phase noise of the 15-GHz half-quadrature VCO. Fig. 13. Measured: (a) output spectrum and (b) close-in phase noise of the 30-GHz quadrature VCO. (35) The ac current at the doubler output is obtained by summing (34) and (35) (36) where and. It is noted that the output current consists of components at the fundamental and the second harmonic frequencies due to the phase and amplitude error. Therefore, the fundamental rejection ratio can be evaluated by (36). Provided that the phase error is relatively small, it is clear that the fundamental rejection ratio is inversely proportional to the phase error (37) As indicated in (37), the fundamental rejection ratio decreases by 6 db as the phase error doubles. Thus, careful design and symmetric layout are required to ensure sufficient suppression of the fundamental component at the second harmonic output. C. Circuit Design Four push push stages are utilized as the frequency doublers to generate the quadrature output at 30 GHz from the 15-GHz half-quadrature signals. The simulated conversion gain of the doublers as a function of the gate bias voltage is illustrated in Fig. 9. In this particular design, transistors with m and m are employed. To maximize the conversion gain, 0.32-nH spiral inductors are used to resonate with the parasitic capacitance of the output node at 30 GHz. Based on the circuit simulation, the frequency doublers with the open-drain buffers exhibit a reasonable conversion gain for the second harmonic component providing an output power level of 15 dbm. V. EXPERIMENTAL RESULTS The proposed dual-band multiphase VCO is implemented in a standard 0.18- m CMOS process. Fig. 10 shows a die photograph of the fabricated circuit with a chip area of 1.1 1.0 mm. In order to minimize the phase error among the multiphase outputs, a symmetrical layout is used for the design. On-wafer probing was performed to characterize the performance of the VCO at the 15- and 30-GHz frequency bands, while the losses from the measurement setup were calibrated and deembedded in the experimental results. The output spectrum and phase noise were measured by a 50-GHz spectrum analyzers. Operated at a supply voltage of 2.0 V, the VCO core consumes a dc power of 52 mw. As the controlled-voltage sweeps from 0 to 2 V, the tuning characteristics, including the oscillation frequency and the output power, of the fundamental and second harmonic outputs are shown in Fig. 11(a) and (b), respectively. With a frequency tuning range of 250 MHz, the

482 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 3, MARCH 2007 TABLE III PERFORMANCE SUMMARY OF THE HIGH-FREQUENCY MULTIPHASE VCOS 15-GHz half-quadrature VCO exhibits an output power ranging from 8to 9 dbm. The measured output power of the doublers at 30 GHz is 16 dbm. Fig. 12 shows the measured output spectrum and close-in phase noise of the 15-GHz fundamental oscillator, indicating a phase noise of 112 dbc/hz at 1-MHz offset frequency. The measured wideband spectrum and the close-in phase noise at the second harmonic output are shown in Fig. 13(a) and (b), respectively. With careful circuit design of the frequency doublers, the 30-GHz output signal exhibits a deembedded fundamental rejection of 19.79 db and a phase noise of 104 dbc/hz with an offset frequency of 1 MHz. The performance of the proposed circuit along with results from the state-of-the-art multiphase VCOs are summarized in Table III for comparison. VI. CONCLUSION This paper has presented a dual-band multiphase VCO using 0.18- m CMOS technology. By employing a rotary travelingwave oscillator and four push push doublers, the fabricated circuit provides half-quadrature output phases at 15 GHz and quadrature oscillating signals at 30 GHz. Since the resonator of the VCO core is designed at half of the maximum operating frequency, stringent design constrains are alleviated. As a result, a manageable design and superior performance can be achieved by the proposed VCO topology. ACKNOWLEDGMENT The authors would like to thank National Chip Implementation Center (CIC), Hsinchu, Taiwan, R.O.C., for chip fabrication, and National Nano Device Laboratories (NDL), Hsinchu, Taiwan, R.O.C., and Y.-C. Huang, National Taiwan University, Taipei, Taiwan, R.O.C., for measurement support. REFERENCES [1] Z. Lao, J. Jensen, K. Guinn, and M. Sokolich, 80-GHz differential VCO in InP SHBTs, IEEE Microw. Wireless Compon. Lett., vol. 14, no. 9, pp. 407 409, Sep. 2004. [2] K. W. Kobayashi, A 108-GHz InP HBT monolithic push push VCO with low phase noise and wide tuning bandwidth, IEEE J. Solid-State Circuits, vol. 34, no. 9, pp. 1225 1232, Sep. 1999. [3] L. F. Tiemeijer et al., A record high 150 GHz f max realized at 0.18 m gate length in an industrial RF-CMOS technology, in Int. Electron Devices Meeting Tech. Dig., Dec. 2001, pp. 10.4.1 10.4.4. [4] H. M. J. Boots, G. Doornbos, and A. Heringa, Scaling of characteristic frequencies in RF CMOS, IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2102 2108, Dec. 2004. [5] C. Cao and K. K. O, A 140-GHz fundamental mode voltage-controlled oscillator in 90-nm CMOS technology, IEEE Microw. Wireless Compon. Lett., vol. 16, no. 10, pp. 555 557, Oct. 2006. [6], Millimeter-wave voltage-controlled oscillators in 0.13-m CMOS technology, IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1297 1304, Jun. 2006. [7] J. Lee, J.-Y. Ding, and T.-Y. Cheng, A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-m CMOS technology, in IEEE VLSI Circuits Tech. Symp. Dig., Jun. 2005, pp. 136 139. [8] H. Shigematsu et al., Millimeter-wave CMOS circuit design, IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 472 477, Feb. 2005. [9] A. P. van der Wel et al., A robust 43-GHz VCO in CMOS for OC-768 SONET applications, IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1159 1163, Jul. 2004. [10] L. M. Franca-Neto, R. E. Bishop, and B. A. Bloechel, 64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method, in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2004, pp. 444 445. [11] A. W. L. Ng and H. C. Luong, A 1 V 17 GHz 5 mw quadrature CMOS VCO based on transformer coupling, in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2006, pp. 711 712. [12] F. Ellinger and H. Jackel, 38 43 GHz quadrature VCO on 90 nm VLSI CMOS with feedback frequency tuning, in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2005, pp. 1701 1703. [13] A. Natarajan, A. Komijani, and A. Hajimiri, A fully integrated 24-GHz phased-array transmitter in CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2502 2514, Dec. 2005. [14] A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, A 900-MHz CMOS LC-oscillator with quadrature outputs, in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 1996, pp. 392 393. [15] H. C. Choi, S. B. Shin, and S.-G. Lee, A low-phase noise LC-QVCO in CMOS technology, IEEE Microw. Wireless Compon. Lett., vol. 14, no. 11, pp. 540 542, Nov. 2004. [16] J. Wood, T. C. Edwards, and S. Lipa, Rotary traveling-wave oscillator arrays: A new clock technology, IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1654 1665, Nov. 2001. [17] A. Hajimiri and T. H. Lee, Design issues in CMOS differential LC oscillators, IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717 724, May 1999. [18] Y.-H. Suh and K. Chang, Coplanar stripline resonators modeling and applications to filter, IEEE Trans. Microw. Theory Tech., vol. 50, no. 5, pp. 1289 1296, May 2002. [19] H. Krishnaswamy and H. Hashemi, A 26 GHz coplanar striplinebased current sharing CMOS oscillator, in IEEE Radio Freq. Integr. Circuits Symp., Jun. 2005, pp. 127 130. [20] G. Le Grand de Mercey, A 18 GHz rotary traveling wave VCO in CMOS with I/Q outputs, in IEEE Eur. Solid-State Circuits Conf., Sep. 2003, pp. 489 492. [21] D. M. Pozar, Microwave Engineering, 3rd ed. New York: Wiley, 2005.

HSIEH et al.: 15/30-GHz DUAL-BAND MULTIPHASE VCO IN 0.18- m CMOS 483 [22] H. Wu and A. Hajimiri, Silicon-based distributed voltage-controlled oscillators, IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 493 502, Mar. 2001. [23] C. Yu, J. S. Yuan, and H. Yang, MOSFET linearity performance degradation subject to drain and gate voltage stress, IEEE Trans. Device Mater. Rel., vol. 4, no. 4, pp. 681 689, Dec. 2004. [24] D. B. Leeson, A simple model of feedback oscillator noise spectrum, Proc. IEEE, vol. 54, no. 2, pp. 329 330, Feb. 1966. [25] D. Baek, J. Kim, D. Kang, and S. Hong, Low phase noise Ku band frequency multiplied and divided MMIC VCOs using InGaP/GaAs HBT technology, in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2003, pp. 2193 2196. [26] S. Ko et al., K- and Q-bands CMOS frequency sources with X-band quadrature VCO, IEEE Trans. Microw. Theory Tech., vol. 53, no. 9, pp. 2789 2800, Sep. 2005. [27] S. Hackl et al., A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology, IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 135 137, Jan. 2003. Hsieh-Hung Hsieh (S 05) was born in Taipei, Taiwan, R.O.C., in 1981. He received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2004, and is currently working toward the Ph.D. degree in electronic engineering at National Taiwan University. His research interests include the development of low-voltage and low-power RF integrated circuits, multiband wireless systems, RF testing, and monolithic microwave integrated circuit (MMIC) designs. Ying-Chih Hsu was born in Taichung, Taiwan, R.O.C., in 1981. He received the B.S. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 2003, and the M.S. degree in electronics engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2005. His research interests include RF integrated circuits and monolithic microwave integrated circuit (MMIC) designs. Liang-Hung Lu (M 02) was born in Taipei, Taiwan, R.O.C., in 1968. He received the B.S. and M.S. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1991 and 1993, respectively, and the Ph.D. degree in electrical engineering from The University of Michigan at Ann Arbor, in 2001. During his graduate study, he was involved in SiGe HBT technology and monolithic microwave integrated circuit (MMIC) designs. From 2001 to 2002, he was with IBM, where he was involved with low-power and RF integrated circuits for silicon-on-insulator (SOI) technology. In August 2002, he joined the faculty of the Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., where he is currently an Associate Professor. His research interests include CMOS/BiCMOS RF and mixed-signal integrated-circuit designs.