IN RECENT years, wireless communication systems have

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1 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY Design and Analysis for a Miniature CMOS SPDT Switch Using Body-Floating Technique to Improve Power Performance Mei-Chao Yeh, Student Member, IEEE, Zuo-Min Tsai, Student Member, IEEE, Ren-Chieh Liu, Member, IEEE, Kun-You Lin, Member, IEEE, Ying-Tang Chang, and Huei Wang, Fellow, IEEE Abstract A low insertion-loss single-pole double-throw switch in a standard m complementary metal oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the 1dB, the bodyfloating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured 1dB of 21.3 dbm, an insertion loss of 0.7 db, and an isolation of 35 db at 2.4 GHz, while at 5.8 GHz, the switch attains a measured 1dB of 20 dbm, an insertion loss of 1.1 db, and an isolation of 27 db. The effective chip size is only 0.03 mm 2. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches. Index Terms Body-floating technique, complementary metal oxide semiconductor (CMOS) switches, nonlinear model, single-pole double-throw (SPDT). I. INTRODUCTION IN RECENT years, wireless communication systems have undergone explosive growth in complementary metal oxide semiconductor (CMOS) technology. CMOS technology has been able to meet the more stringent cost constraints inherent in these more diverse mainstream applications. The advantages of silicon CMOS technology for RF and microwave control functions over GaAs are its low-cost structure and its integration potential with RF and silicon MOS-based mixed-signal circuitry. A high-quality microwave switch is a key building block of a RF front end for time-division duplexing (TDD) communication systems. Key figures-of-merit of a transmit/receive (T/R) Manuscript received May 31, 2005; revised August 31, The work was supported in part by the Sunplus Technology Company Ltd. and the National Science Council of Taiwan, R.O.C. under Grant NSC E PAE, Grant NSC E , Grant NSC E , and Grant NSC E M.-C. Yeh was with the Graduate Institute of Communication Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C. She is now with the Realtek Semiconductor Corporation, Hsinchu City, Taiwan 300, R.O.C. ( yehmei@realtek.com.tw). Z.-M. Tsai and H. Wang are with the Graduate Institute of Communication Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C. ( hueiwang@ew.ee.ntu.edu.tw). R.-C. Liu is with the Realtek Technology Company, Hsinchu City, Taiwan 300, R.O.C. ( rcliu@ntu.edu.tw). K.-Y. Lin and Y.-T. Chang are with the Sunplus Technology Company Ltd., Hsinchu City, Taiwan 300, R.O.C. ( ytchang@sunplus.com). Digital Object Identifier /TMTT Fig. 1. Dynamic load line of the: (a) on- and (b) off-state passive FET. switch include insertion loss, isolation, and power-handling capability measured by the power 1-dB compression point. Recent publications show a trend of implementing T/R switches using the CMOS process [1] [4]. Switches using high and low substrate resistances in a m CMOS process have demonstrated good insertion loss [5], but required a large area of substrate contact to implement a low substrate resistance switch. To achieve such performance, an LC-tuned substrate bias was used [6]. However, the bias network improving the large-signal handling capability increased the chip size significantly. In the meanwhile, the LC-tuned substrate bias network limited the switch in a narrow frequency range. For 2.4- and 5.2-GHz applications, two different switches were designed and the LC-tuned substrate bias networks were needed to be /$ IEEE

2 32 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006 Fig. 2. (a) Circuit schematic of a series transistor. (b) The equivalent model in the on state. The simplified equivalent circuit models: (c) without and (d) with body-floating technique. devised, respectively. An impedance-matching technique was used to improve the of the switch [7], but the matching network also resulted in a large die size. Switch realized by depletion-layer-extended transistors (DETs) obtained high power handling [8]. Nevertheless, the DETs were formed with additional mask steps compared with the standard CMOS process. In order to avoid latching up, the pmos and n-well must also be placed sufficiently far away from the DETs and, thus, results in a large chip size. An accurate nonlinear CMOS model is needed to predict the power performance. A CMOS RF model for gigahertz communication integrated circuits (ICs) was proposed [9], but it described the power characteristics mainly in the active region of the transistor. A large-signal field-effect transistor (FET) model of a passive high electron-mobility transistor (HEMT) for the switch circuit was presented [10], and the power performance of the series-shunt switch can be predicted accurately in the heterojunction field-effect transistor (HJFET) monolithic-microwave integrated-circuit (MMIC) process. In this paper, the body-floating technique is used to improve the power performance of the switch. To implement this technique in a CMOS switch, the body of the device is connected to ground with a 5-k resistor. This simple implementation can increase the power-handling capability in a wide-band frequency range with a small chip size [11]. An RF single-pole doublethrow (SPDT) switch in a standard m CMOS process is presented. In order to investigate the power limitation of the transistors, a nonlinear CMOS model is developed to predict the power performance of the SPDT switch. This SPDT switch exhibits 0.7-dB insertion loss, 35-dB isolation, and 21.3-dBm input at 2.4 GHz and 1.1-dB insertion loss, 27-dB isolation, and 20-dBm input at 5.8 GHz. Compared with the previously published CMOS switches [1] [8], this chip accomplished low insertion loss, high isolation, good power performance, and smallest chip size simultaneously. II. BODY-FLOATING TECHNIQUE In order to increase the power performance of the switch, the reasons for power limitation of CMOS devices are first investigated. Fig. 1(a) and (b) shows the dynamic load lines of a shunt passive FET in the on and off states, respectively. The equivalent-circuit model of an on-state transistor is a small resistor, which has the dynamic load line along the I V curve, as shown in Fig. 1(a). The larger swing range of the dynamic load line follows the large input power. The input impedance is changed when the dynamic load line approaches the maximum current, and limits the power-handling capability. For the off-state transistor, it is represented as a small capacitor series with a small resistor. For small input power, the drain-to-source current is almost zero when the transistor turns off. The dynamic load line is shown in Fig. 1(b). When the input power increases, the dynamic load line approaches the breakdown voltage and, thus, the input impedance is changed and power performance is degraded. In order to improve the power performance of the CMOS switch, the body-floating technique is used. Fig. 2(a) shows the circuit schematic of a series transistor, and the equivalent-circuit model in the on state is presented in Fig. 2(b). For a conventional switch, the body of the transistor is connected to the source, and the equivalent-circuit model is shown as Fig. 2(c). When the input power increases, the drain-to-source voltage is so negative as to turn on the diode between drain and body, and the input impedance of the transistor is lower. Using the body-floating technique, the body of the transistor is connected to ground with a 5-k resistor, and the equivalent-circuit model is illustrated in Fig. 2(d). Since the resistance connected to ground is very high compared to, the input impedance of the transistor still remains the same as. Fig. 3(a) shows the circuit schematic of a shunt transistor, and the equivalent-circuit model in the off state is shown in Fig. 3(b). Without the body-floating technique, the high input power will turn on the diode between body and drain, and the current from ground to drain increases quickly. The high current will change the input impedance of the transistor, and degrade the power performance, as shown in Fig. 3(c). Fig. 3(d) demonstrates the equivalent-circuit model of the off-state transistor with the body floating. When the input power is high, the diode between drain and body still turns on. Since the resistance between body and ground is very high, the current from ground to drain increases smoothly. Fig. 4 presents the measured dc IV curves of a 60- m transistor with and without using the body-floating technique. As can be observed, the negative drain current occurs much later in the off state when the body-floating technique is applied. That means the input impedance of the transistor with the body-floating technique is barely influenced with the high input power, and the power-handling capability is improved. On the other hand, the power performance is limited by the maximum

3 YEH et al.: DESIGN AND ANALYSIS FOR MINIATURE CMOS SPDT SWITCH 33 Fig. 3. (a) Circuit schematic of a shunt transistor. (b) The equivalent model in the off state. The simplified equivalent circuit models: (c) without and (d) with body-floating technique. Fig. 4. DC IV curves of a 60-m transistor with and without using body-floating technique. Fig. 5. Simple structure of DNW. current when the device is in the on state. In the case of a 60- m device, the differences between the dc IV curves are not obvious in the positive drain-to-source voltage region. Therefore, when the power performance of the switch is limited by the shunt transistor, which is in the off state, the body-floating technique can increase the power-handling capability of the switch effectively. This will be explained using the load-line analysis in Section III. The SPDT switch is fabricated in a m CMOS process. To implement the body-floating technique, the body is connected to ground with a 5-k resistor, as shown in Fig. 5. A deep n-well (DNW) is offered as default in the m mixed-signal process for better substrate isolation with an additional PN junction [12]. In this study, the DNW is used to completely separate the body of the transistor with a p-substrate using the body-floating technique. Due to the DNW, there are no parasitic bipolar junction transistors (BJTs) and, thus, the switch can get rid of latching up. III. SPDT SWITCH DESIGN By using the body-floating technique, the performances of the CMOS switch can be improved. Fig. 6 is the schematic of the series-shunt CMOS RF SPDT switch, which comprises two series and two shunt transistors. The series transistors M1 and M2 perform the main switching function, and the shunt transistors M3 and M4 increase the isolation of the switch. It is observed that the ratio of the size for the series to shunt transistor significantly Fig. 6. Series-shunt switch schematic diagram. influences the performances of the switch, especially for the insertion loss. Fig. 7(a) presents the simulated relations between the insertion loss (in decibels) and the gatewidth of series and shunt transistors, while the relations between isolation (in decibels) and the sizes are shown in Fig. 7(b). As can be observed, the sizes of the series and shunt transistors must be selected properly. In order to achieve a low insertion loss, there are two options: one is to use a large size for the series transistor and a small size for the shunt one, and the other is simply the opposite, i.e., to select a small size for the series device and a large size for the shunt one. Since the insertion losses of the two cases are similar, isolation and power-handling capability will be taken into consideration. Fig. 8 illustrates the dc IV curves of a 60- and a 180- m transistor. As can be observed, in the on state, the larger device has the higher maximum current and, thus,

4 34 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006 Fig. 7. Relationships between the sizes of the transistors and: (a) insertion loss and (b) isolation of the SPDT switch. Fig. 9. DC IV curves and dynamic load lines of a: (a) 180-m series on-state and (b) 60-m shunt off-state transistor. power is 19 dbm, the dynamic load line of the 180- m series on-state transistor is still within the linear region of the dc IV curve [see Fig. 9(a)], while the dynamic load line of the 60- m shunt off-state transistor has been clamped by the nonlinear portion of the dc IV curve [see Fig. 9(b)]. This explains that the shunt transistor limits the power performance of the switch. Fig. 8. DC IV curves of a 60- and a 180-m transistor. the power-handling capability is better. On the other hand, in the off state, the smaller device has less negative current, which leads to a better power-handling capability. For the concern of power-handling capability, large devices are used for series transistors, while a small size is used for the shunt ones. Since there are tradeoffs in device size selection for the insertion loss, isolation, and power-handling capability, large devices of 180- m gatewidth are selected for series transistors M1 and M2, while the sizes of shunt transistors M3 and M4 are both 60 m in the design. The gate bias resistors,,, and are 5k to improve the dc-bias isolation. The simulated dynamic load lines are illustrated in Fig. 9. The dynamic load lines are plotted along the dc IV curves for a 180- m series on-state and a 60- m shunt off-state transistor, respectively. When the input IV. NONLINEAR RESISTIVE CMOS MODEL The resistive CMOS model is nonlinear model operating at zero drain-to-source voltage and suitable for the passive CMOS switches. The maximum power for the switching operation would be expressed by the CMOS parameters such as the saturation drain current at V and the drain breakdown voltage in the pinched-off state. In the large-signal operation, the drain voltage swings to the negative region. Therefore, the characteristics of the negative drain voltage region must be included in the nonlinear model for the switch applications. A large-signal CMOS model for the switch circuit is presented in Fig. 10. In the model, the FET can be expressed as the parallel combination of a capacitor series with a small resistor and a current source. The current equations of the current source describe saturation current, knee voltage, and breakdown voltage. The model is based on the Angelov model [13]. To study the two-port model easily, a simple hyperbolic tangent current model is employed. Four main current source equations are used to describe the on- and off-state transistors. In the on state with V, the drain current is described as (1) (4)

5 YEH et al.: DESIGN AND ANALYSIS FOR MINIATURE CMOS SPDT SWITCH 35 Fig. 10. Nonlinear model of the FET. TABLE I PARAMETER VALUES FOR LARGE-SIGNAL MODEL Fig. 11. device. DC IV curves comparison of measurement and model for a 60-m Fig. 12. Measured phase of S of a shunt 60-m device for the different bias conditions in on state. (3) (4) (5) (6) (7) and, in the off state, with V, the drain current is as shown in (5) (7). Two series of parameters of a 180- and 60- m transistors are extracted. The values of the parameters of the CMOS nonlinear model are listed in Table I. In order to simplify the nonlinear model, some coefficients such as,, etc. are omitted. It is observed the simplified nonlinear model still can describe the power performance of the device accurately as follows: (1) (2) When the input power varies, the gate-to-source voltage of the transistor changes simultaneously. The dc IV curves of different from 1.4 to 2 V in the on state and 2.2 to 1.4 V in the off state are described in the nonlinear model. Fig. 11 demonstrates the dc IV curves of a 60- m transistor. The lines with markers are the calculated results of the nonlinear model, while the solid lines present the measurements. The measured and calculated results are in good agreement. The capacitance for is the combination of the parasitic capacitances between drain, gate, source, and body. In the on state, the input impedance is dominated by, and is almost the same in different bias conditions. Fig. 12 shows the measured phase of of a shunt 60- m transistor with different values of and. As can be observed, when the gate voltage and the drain-to-source voltage change, the phases of of the device are similar. In the off state, changes when the drain-to-source voltage swings. However, in the low-frequency

6 36 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006 Fig. 13. Measured phase of S of a shunt 60-m device for different bias condition in off state. Fig. 15. Die photograph of 0.18-m CMOS switch. The effective circuit area without pads is only 0.03 mm. Fig. 16. Simulated and measured insertion loss and isolation of the 0.18-m CMOS switch. It achieves a 1.1-dB insertion loss and 27-dB isolation at 5.8 GHz. Fig. 14. S of measurement and simulation by nonlinear model for a shunt 60-m transistor. In the on state, V is 1.8 V, while V is 01.8 V in the off state. range, the difference is not obvious. Fig. 13 demonstrates the measured phase of of a shunt 60- m transistor with different drain-to-source voltages at 5.8 GHz. The variations of phases between different bias conditions are less than 3 with gate voltage fixed at 1.8 V. In order to simplify the nonlinear model, the capacitor of the model is assumed not to vary with the dc bias of the transistor. In the TSMC m CMOS process, the values of are 0.15 and 0.05 pf for 180- and 60- m devices, respectively, with an of 5. Fig. 14 shows the of measurement and simulation with the nonlinear model for a shunt 60- m transistor in the on and off states from dc to 50 GHz. The simulated results by the nonlinear model agree with the measurements very well. V. MEASUREMENT RESULTS This CMOS SPDT switch is implemented using commercial standard m MS/RF CMOS technology, which provides one poly layer for the gate of the MOS and six metal layers for inter-connection [14], [15]. The substrate conductivity is approximately 10 S/m. With optimized CMOS technology and DNW, this technology provides and of higher than 60 and 55 GHz, respectively. The die micrograph of the series-shunt SPDT switch using a m CMOS process is shown in Fig. 15. The chip size is mm and the effective circuit area without pads is only mm. The circuit was tested via on-wafer probing. As shown in Fig. 16, the series-shunt switch achieves an insertion loss of 0.7 db and an isolation of 35 db at 2.4 GHz. It also achieves an insertion loss of 1.1 db and an isolation of 27 db at 5.8 GHz. Fig. 17 shows the simulated and measured I/O return losses of the switch versus frequency. The I/O return losses are both better than 10 db below 6 GHz. Fig. 18 presents the measured insertion losses versus input power of the switches with/without body-floating technique at 2.4 and 5.8 GHz. When the dc bias of the Tx and Rx nodes shown in Fig. 6 is 0 V, and is 1.8 and 1.8 V, respectively, the switch using a m device achieves a of 21.3 dbm at 2.4 GHz

7 YEH et al.: DESIGN AND ANALYSIS FOR MINIATURE CMOS SPDT SWITCH 37 Fig. 17. switch. Simulated and measured I/O return losses of the 0.18-m CMOS Fig. 19. Simulated and measured P versus P of the SPDT switch at: (a) 2.4 and (b) 5.8 GHz. The simulation is performed by using the nonlinear model introduced in Section IV. TABLE II MEASURED PERFORMANCE SUMMARY OF THE SPDT SWITCH Fig. 18. Insertion loss versus P of the 0.18-m CMOS switch at: (a) 2.4 and (b) 5.8 GHz. Using the body-floating technique, the P of the switch is improved 2 db. and a of 20 dbm at 5.8 GHz. Using devices of the same sizes, another SPDT switch without the body-floating technique achieves a of 19 dbm at 2.4 GHz and a of 18 dbm at 5.8 GHz. The of the switch is improved 2 db by using the body-floating technique. Fig. 19 shows the simulated and measured versus of the SPDT CMOS switch with the body-floating technique. The simulated input of the switch is 21 dbm with the nonlinear model described in Section IV at 2.4 GHz, while the simulated input is 24.5 dbm with the BSIM3 models [12]. At 5.8 GHz, by using the nonlinear model described in Section IV, the simulated input of the switch is 21 dbm, compared with the 25-dBm simulated input with the BSIM3 models, the nonlinear model can predict the power performance more accurately. High power performances of the switches in [6] and [8] are achieved by using the large transistors and asymmetric topologies at the cost of the higher insertion loss and lower isolation in the receive path. This switch with the body-floating technique attains low insertion loss, high

8 38 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 1, JANUARY 2006 TABLE III RECENTLY REPORTED PERFORMANCES OF 5 6-GHz CMOS SWITCHES isolation, and good power performance in the transmit and receive paths simultaneously. Table II summaries the measured performances of the SPDT switch at 2.4 and 5.8 GHz. VI. CONCLUSIONS The body-floating technique has been used to increase the power-handling capability of the CMOS switch. In order to investigate the power performance of the switch, a nonlinear CMOS model for describing the power-handling capability has been developed. Based on the nonlinear model, the transistor size can be properly selected for high-power performance. An SPDT switch using a m CMOS process was designed, fabricated, and measured. The series-shunt switch achieves an insertion loss of 0.7 db, an isolation of 35 db, and a of 21.3 dbm at 2.4 GHz. This switch also exhibits 1.1-dB insertion loss, 27-dB isolation, and 20-dBm input at 5.8 GHz. Table III presents the recently reported performances of 5 6-GHz CMOS switches. The switch with the body-floating technique accomplishes low insertion loss, high isolation, good power performance, and smallest chip size simultaneously. Moreover, the newly developed nonlinear model can predict the power performance of the switch more accurately than the BSIM3 model. ACKNOWLEDGMENT The authors would like to thank Dr. H.-Y. Chang and C.-S. Lin, both with the National Taiwan University, Taipei, Taiwan, R.O.C., for their valuable suggestions. REFERENCES [1] F.-J. Huang and K. O, A 0.5-m CMOS T/R switch for 900-MHz wireless applications, IEEE J. Solid-State Circuits, vol. 36, no. 5, pp , May [2] A. Ajjikuttira, C. Lrung, E.-S. Khoo, M. Choke, and R. Singh, A fullyintegrated CMOS RFIC Bluetooth application, in IEEE Int. Solid-State Circuits Conf. Dig., San Franciso, CA, Feb. 2001, pp [3] K. K. O, X. Li, F.-J. Huang, and W. Foley, CMOS components for b wireless LAN applications, in IEEE RFIC Symp., Seattle, WA, Jun. 2002, pp [4] M. Madihian, L. Desclos, and T. Drenski, CMOS RF IC s for 900 MHz 2.4 GHz band wireless communication networks, in IEEE RFIC Symp., Anaheim, CA, Jun. 1999, pp [5] Z. Li, H. Yoon, F.-J. Huang, and K. K. O, 5.8-GHz CMOS T/R switches with high and low substrate resistances in a 0.18-m CMOS process, IEEE Microw. Wireless Compon. Lett., vol. 13, no. 1, pp. 1 3, Jan [6] N. A. Talwalkar, C. P. Yue, H. Gan, and S. S. Wong, Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications, IEEE J. Solid-State Circuits, vol. 39, no. 6, pp , Jun [7] F.-J. Huang and K. K. O, Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p-silicon substrates, IEEE J. Solid-State Circuits, vol. 39, no. 1, pp , Jan [8] T. Ohnakado, S. Yamakawa, T. Murakami, A. Furukawa, E. T. H. Ueda, N. Suematsu, and T. Oomori, 21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs), IEEE J. Solid-State Circuits, vol. 39, no. 1, pp , Jan [9] J.-J. Ou, X. Jin, I. Ma, C. Hu, and P. R. Gray, CMOS RF modeling for GHz communication IC s, in VLSI Circuits Symp. Dig., Honolulu, HI, Jun. 1998, pp [10] H. Mizutani, M. Funabashi, M. Kuzuhara, and Y. Takayama, Compact DC 60-GHz HJFET MMIC switches using ohmic electrode-sharing technology, IEEE Trans. Microw. Theory Tech., vol. 46, no. 11, pp , Nov [11] M.-C. Yeh, R.-C. Liu, Z.-M. Tsai, and H. Wang, A miniature low-insertion-loss, high-power CMOS SPDT switch using floating-body technique for 2.4- and 5.8-GHz applications, in IEEE RFIC Symp., Long Beach, CA, Jun. 2005, pp [12] 0.18 m mixed signal 1P6M+ MIM salicide 1.8 V/3.3 V design guideline, TSMC, Hsinchu City, Taiwan, R.O.C., [13] I. Angelov, H. Zirath, and N. Rorsman, A new empirical model for HEMT and MESFET devices, IEEE Trans. Microw. Theory Tech., vol. 40, no. 12, pp , Dec [14] H. M. Hsu, J. Y. Chang, J. G. Su, C. C. Tsai, S. C. Wong, C. W. Chen, K. R. Peng, S. P. Ma, C. H. Chen, T. H. Yeh, C. H. Lin, Y. C. Sun, and C. Y. Chang, A 0.18-m foundry RF CMOS technology with 70-GHz ft for single chip system solutions, in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, May 2001, pp [15] C. H. Diaz et al., A 0.18-m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications, in IEEE VLSI Tech. Symp., Kyoto, Japan, Jun. 1999, pp

9 YEH et al.: DESIGN AND ANALYSIS FOR MINIATURE CMOS SPDT SWITCH 39 Mei-Chao Yeh (S 03) was born in Kaohsiung, Taiwan, R.O.C., on January 10, She received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2003, and the M.S. degree from the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in She is currently an Engineer with the Realtek Semiconductor Corporation, Hsinchu City, Taiwan, R.O.C. Her research interests are in the areas of RF and millimeter-wave ICs in CMOS technologies. Kun-You Lin (S 00 M 04) was born in Taipei, Taiwan, R.O.C., in He received the B.S. degree in communication engineering from National Chiao Tung University, Hsinchu City, Taiwan, R.O.C., in 1998, and the Ph.D. degree in communication engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in From August 2003 to March 2005, he was a Post-Doctoral Research Fellow with the Graduate Institute of Communication Engineering, National Taiwan University. He is currently an Advanced Engineer with the Sunplus Technology Company Ltd., Hsinchu City, Taiwan, R.O.C. His research interests include the design and analysis of microwave/rf circuits. Dr. Lin is a member of Phi Tau Phi. Zuo-Min Tsai (S 01) was born in Mailo, Taiwan, R.O.C., in He received the B.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, R.O.C., 2001, and is currently working toward the Ph.D. degree at National Taiwan University. His research interests are the theory of microwave circuits. Ren-Chieh Liu (S 01 M 05) was born in ChangHua, Taiwan, R.O.C., on September 2, He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, R.O.C., in 1997, 2000 and 2004, respectively. He is currently an Engineer with the Realtek Semiconductor Corporation, Hsinchu City, Taiwan, R.O.C. His research interests include CMOS RF ICs, microwave monolithic ICs, and communication system circuits. Ying-Tang Chang was born in Taipei, Taiwan, R.O.C., in He received the B.S. degree in communication engineering from National Chiao Tung University, Hsinchu City, Taiwan, R.O.C., in 1999, and the M.S. degree in communication engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in Since October 2001, he has been with the Sunplus Technology Company Ltd., Hsinchu City, Taiwan, R.O.C., where he is an Advanced Engineer engaging in CMOS/BiCMOS RFIC design. Huei Wang (S 83 M 87 SM 95 F 06) was born in Tainan, Taiwan, R.O.C., on March 9, He received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1980, and the M.S. and Ph.D. degrees in electrical engineering from Michigan State University, East Lansing, MI, in 1984 and 1987, respectively. During his graduate study, he was engaged in research on theoretical and numerical analysis of electromagnetic radiation and scattering problems. He was also involved in the development of microwave remote detecting/sensing systems. In 1987, he joined the Electronic Systems and Technology Division, TRW Inc. He has been an MTS and Staff Engineer responsible for MMIC modeling of computer-aided design (CAD) tools, and MMIC testing evaluation and design, and became the Senior Section Manager of the Millimeter-Wave Sensor Product Section, RF Product Center. In 1993, he visited the Institute of Electronics, National Chiao-Tung University, Hsinchu City, Taiwan, R.O.C., where he taught MMIC-related topics. In 1994, he returned to TRW Inc. In February 1998, he joined the faculty of the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., where he is currently a Professor. Dr. Wang is a member of Phi Kappa Phi and Tau Beta Pi. He was the recipient of the Distinguished Research Award presented by the National Science Council, R.O.C. ( ). He was also elected as the first Richard M. Hong Endowed Chair Professor of National Taiwan University in 2005.