FDG8850NZ Dual N-Channel PowerTrench MOSFET 30V,0.75A,0.4Ω Features Max r DS(on) = 0.4Ω at V GS = 4.5V, I D = 0.75A Max r DS(on) = 0.5Ω at V GS = 2.7V, I D = 7A Very low level gate drive requirements allowing operation in 3V circuits(v GS(th) <.5V) Very small package outline SC70-6 RoHS Compliant April 2007 General Description This dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values. tm S2 D G2 S Q D S G D2 G D2 Q2 G2 S2 SC70-6 Pin MOSFET Maximum Ratings T A = 25 C unless otherwise noted Symbol Parameter Ratings Units V DS Drain to Source Voltage 30 V V GS Gate to Source Voltage ±2 V Drain Current -Continuous 0.75 I D -Pulsed 2.2 A Power Dissipation for Single Operation (Note a) 0.36 P D (Note b) 0.30 W T J, T STG Operating and Storage Junction Temperature Range 55 to +50 C Thermal Characteristics R θja Thermal Resistance, Junction to Ambient Single operation (Note a) 350 R θja Thermal Resistance, Junction to Ambient Single operation (Note b) 45 Package Marking and Ordering Information C/W Device Marking Device Reel Size Tape Width Quantity.50 FDG8850NZ 7 8mm 3000 units
Electrical Characteristics T J = 25 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV DSS Drain to Source Breakdown Voltage I D = 250μA, V GS = 0V 30 V ΔBV DSS Breakdown Voltage Temperature ΔT J Coefficient I D = 250μA, referenced to 25 C 25 mv/ C I DSS Zero Gate Voltage Drain Current V DS = 24V, V GS = 0V μa I GSS Gate to Source Leakage Current V GS = ±2V, V DS = 0V ±0 μa On Characteristics V GS(th) Gate to Source Threshold Voltage V GS = V DS, I D = 250μA 5.0.5 V ΔV GS(th) ΔT J r DS(on) Gate to Source Threshold Voltage Temperature Coefficient Static Drain to Source On Resistance I D = 250μA, referenced to 25 C 3.0 mv/ C V GS = 4.5V, I D = 0.75A V GS = 2.7V, I D = 7A V GS = 4.5V, I D = 0.75A,T J = 25 C g FS Forward Transconductance V DS = 5V, I D = 0.75A 3 S Dynamic Characteristics C iss Input Capacitance 90 20 pf C oss Output Capacitance V DS = 0V, V GS = 0V, f= MHZ 20 30 pf C rss Reverse Transfer Capacitance 5 25 pf Switching Characteristics (note 2) t d(on) Turn-On Delay Time 4 0 ns t r Rise Time V DD = 5V, I D = 0.5A, 0 ns t d(off) Turn-Off Delay Time V GS = 4.5V,R GEN = 6Ω 9 8 ns t f Fall Time 0 ns Q g Total Gate Charge.03.44 nc Q gs Gate to Source Charge V GS =4.5V, V DD = 5V, I D = 0.75A 0.29 nc Q gd Gate to Drain Miller Charge 0.7 nc 0.25 0.29 0.36 0.4 0.5 Ω Drain-Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain-Source Diode Forward Current 0.3 A V SD Source to Drain Diode Forward Voltage V GS = 0V, I S = 0.3A (Note 2) 0.76.2 V Notes:. R θja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θjc is guaranteed by design while R θja is determined by the user's board design. a. 350 C/W when mounted on a in 2 pad of 2 oz copper. b. 45 C/W when mounted on a minimum pad of 2 oz copper. Scale : on letter size paper. 2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%. 2
Typical Characteristics T J = 25 C unless otherwise noted ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 2.20.76.32 0.88 0.44 V GS = 4.5V 0.00 0.0 0.5.0.5 2.0 Figure..6.4.2.0 0.8 I D = 0.75A V GS = 4.5V V GS = 2.7V V GS = 2.0V V GS =.8V V GS =.5V V DS, DRAIN TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE.0 V GS = 4.5V 0.00 0.44 0.88.32.76 2.20 On-Region Characteristics Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage -50-25 0 25 50 75 00 25 50 T J, JUNCTION TEMPERATURE ( o C) Figure 3. Normalized On - Resistance vs Junction Temperature rds(on), DRAIN TO SOURCE ON-RESISTANCE (Ω) 2.6 2.2.8.4 0.8 0.4 Figure 4. V GS =.8V T J = 25 o C V GS = 2.0V V GS = 2.7V I D, DRAIN CURRENT(A) I D =0.38A V GS = 3.5V T J = 25 o C 0.2 2 3 4 5 V GS, GATE TO SOURCE VOLTAGE (V) On-Resistance vs Gate to Source Voltage I D, DRAIN CURRENT (A) 2.20.76.32 0.88 0.44 VDD = 5V T J = 50 o C T J = 25 o C T J = -55 o C 0.00 0.0 0.5.0.5 2.0 2.5 V GS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics IS, REVERSE DRAIN CURRENT (A) 2 0. 0.0 V GS = 0V T J = 50 o C T J = -55 o C T J = 25 o C E-3 0.2 0.4 0.8.0.2 V SD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3
Typical Characteristics T J = 25 C unless otherwise noted VGS, GATE TO SOURCE VOLTAGE(V) ID, DRAIN CURRENT (A) 5 4 3 2 ID = 0.22A 0 0.0 0.2 0.4 0.8.0.2.4 Q g, GATE CHARGE(nC) Figure 7. 4 0. V DD = 5V r DS(on) LIMITED V DD = 5V V DD = 0V 0. 0 V DS, DRAIN TO SOURCE VOLTAGE (V) Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 00μs ms 0ms SINGLE PULSE T J = MAX RATED 00ms R θja = 45 O C/W s 0.0 T A = 25 O C DC 0.005 0. 0 00 V DS, DRAIN to SOURCE VOLTAGE (V) Figure 9. Forward Bias Safe Operating Area CAPACITANCE (pf) P (PK), PEAK TRANSIENT POWER (W) 200 00 0 50 0 f = MHz V GS = 0V Figure 0. C iss C oss C rss SINGLE PULSE R θja = 45 O C/W T A = 25 O C 0. 0.000 0.00 0.0 0. 0 00 000 t, PULSE WIDTH (s) Single Pulse Maximum Power Dissipation 30 NORMALIZED THERMAL IMPEDANCE, Z θja 0. 0.0 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0. 0.05 0.02 0.0 SINGLE PULSE P DM t t 2 NOTES: DUTY FACTOR: D = t /t 2 PEAK T J = P DM x Z θja x R θja + T A R θja = 45 o C/W 0.000 0.00 0.0 0. 0 00 000 t, RECTANGULAR PULSE DURATION (s) Figure. Transient Thermal Response Curve 4
tm TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world ActiveArray Bottomless Build it Now CoolFET CROSSVOLT CTL Current Transfer Logic DOME E 2 CMOS EcoSPARK EnSigna FACT Quiet Series FACT FAST FASTr FPS FRFET GlobalOptoisolator GTO HiSeC i-lo ImpliedDisconnect IntelliMAX ISOPLANAR MICROCOUPLER MicroPak MICROWIRE Motion-SPM MSX MSXPro OCX OCXPro OPTOLOGIC OPTOPLANAR PACMAN PDP-SPM POP Power220 Power247 PowerEdge PowerSaver Power-SPM PowerTrench Programmable Active Droop QFET QS QT Optoelectronics Quiet Series RapidConfigure RapidConnect ScalarPump SMART START SPM STEALTH SuperFET SuperSOT -3 SuperSOT -6 SuperSOT -8 SyncFET TCM The Power Franchise TinyBoost TinyBuck TinyLogic TINYOPTO TinyPower TinyWire TruTranslation µserdes UHC UniFET VCX Wire tm DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor.The datasheet is printed for reference information only. Rev. I26
Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor: FDG8850NZ