Frequency Timing Generator for PENTIUM II/III Systems

Integrated Circuit Systems, Inc. ICS9250-2 Frequency Timing Generator for PENTIUM II/III Systems General Description The ICS9250-2 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRMs. This chip provides all the clocks required for such a system when used with a Direct Rambus Clock Generator (DRCG) chip such as the ICS922-0, 02, 03 and a PCI buffer 92-7. Spread Spectrum may be enabled by driving the SPRED# pin active. Spread spectrum typically reduces system EMI by 8dB to 0dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-2 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. The CPU/2 clocks are inputs to the DRCG. Key Specification: CPU Output Jitter: 50ps IOPIC Output Jitter: 250ps CPU/2, 3V66, PCI Output Jitter: 250ps CPU (0:3) CPU/2 Output Skew: <75ps PCI_F, PCI :7 Output Skew: <500ps 3V66 (0:3) Output Skew <250ps IOPIC (0:2) Output Skew <250ps CPU to 3V66 (0:3) Output Offset: 0.0 -.5ns (CPU leads) CPU to PCI Output Offset:.5-4.0ns (CPU leads) CPU to PIC Output Offset.5-4.0ns (CPU leads) Features Generates the following system clocks: - 4 CPU clocks ( 2.5V, 00/33) - 8 PCI clocks, including free-running (3.3V, 33) - 2 CPU/2 clocks (2.5V, 50/66) - 3 IOPIC clocks (2.5V, 6.67) - 4 Fixed frequency 66 clocks(3.3v, 66) - 2 REF clocks(3.3v, 4.38) - USB clock (3.3V, 48) Efficient power management through PD#, CPU_STOP# and PCI_STOP#. 0.5% typical down spread modulation on CPU, PCI, IOPIC, 3V66 and CPU/2 output clocks. Uses external 4.38 crystal. Pin Configuration Block Diagram 56-pin SSOP 9250-2 Rev B 2/23/00 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS9250-2 Pin Descriptions Pin number Pin name Type Description GNDREF PWR Gnd pin for REF clocks 2, 3 REF(0:) OUT 4.38 reference clock outputs at 3.3V 4 VDDREF PWR Power pin for REF clocks 5 X IN XTL_IN 4.38 crystal input 6 X2 OUT XTL_OUT Crystal output 7, 3, 9 GNDPCI PWR Gnd pin for PCICLKs 8 PCICLK_F OUT Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected by the PCI_STOP# input. 9,, 2, 4, 5, 7, 8 PCICLK[:7] OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks. 0, 6 VDDPCI PWR 3.3Volts power pin for PCICLKs 20, 24 GND66 PWR Gnd pin for 3V66 outputs 2, 22, 25, 26 3V66[0:3] OUT 66 outputs at 3.3V. These outputs are stopped when CPU_STOP# is driven active.. 23, 27 VDD66 PWR power pin for the 3V66 clocks. 28 SEL 33/00# IN This selects the frequency for the CPU and CPU/2 outputs. High = 33, Low=00 29 GND48 PWR Ground pin for the 48 output 30 48 OUT Fixed 48 clock output. 3.3V 3 VDD48 PWR Power pin for the 48 output. 32, 33 SEL[0:] IN Function select pins. See truth table for details. 34 SPRED# IN 35 PD# IN 36 CPU_STOP# IN 37 PCI_STOP# IN Enables spread spectrum when active(low). modulates all the CPU, PCI, IOPIC, 3V66 and CPU/2 clocks. Does not affect the REF and 48 clocks. 0.5% down spread modulation. This asynchronous input powers down the chip when drive active(low). The internal PLLs are disabled and all the output clocks are held at a Low state. This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at logic "0" when driven active(low). Does not affect the CPU/2 clocks. This asynchronous input halts the PCICLK[:7] at logic"0" when driven active(low). PCICLK_F is not affected by this input. 38 GNDCOR PWR Ground pin for the PLL core 39 VDDCOR PWR Power pin for the PLL core. 3.3V 43, 47 VDDLCPU PWR Power pin for the CPUCLKs. 2.5V 40, 44 GNDLCPU PWR Ground pin for the CPUCLKs 4, 42, 45, 46 CPUCLK[0:3] OUT Host bus clock output at 2.5V. 33 or 00 depending on the state of the SEL 33/00. 48 GNDLCPU/2 PWR Ground pin for the CPU/2 clocks. 49, 50 CPU/2[0:] OUT 2.5V clock outputs at /2 CPU frequency. 66 or50 depending on the state of the SEL 33/00# input pin. 5 VDDLCPU/2 PWR Power pin for the CPU/2 clocks. 2.5V 52 GNDLIOPIC PWR Ground pin for the IOPIC outputs. 53, 54, 55 IOPIC[0:2] OUT IOPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at 6.67. 56 VDDLIOPIC PWR Power pin for the IOPIC outputs. 2.5V. 2

ICS9250-2 Frequency Select: SEL SEL0 CPU 0 0 0 0 0 N/ CPU/2 N/ 3V66 N/ PCI N/ 0 N/ N/ N/ N/ N/ N/ N/ 0 33 66 66 33 4.38 6.67 33 66 66 33 48 4.38 6.67 Note:. TCLK is a test clock driven on the x input during test mode. ICS9250-2 Power Management Features: 48 N/ REF N/ IOPIC N/ 0 0 00 50 66 33 4.38 6.67 SEL 33/00- # 0 00 50 66 33 48 4.38 6.67 TCLK/- 0 0 TCLK/ 2 TCLK/ 4 TCLK/ 4 TCLK/ 8 TCLK CLK/6 2 Comments Tri-state Reserved 48 PLL disabled T Test mode () Reserved C PU_STOP# P D# PCI_STOP# CPUCLK CPU/ 2 IOPIC 3V66 PCI PCI_ F REF. 48 Osc VCOs X 0 X OFF OFF 0 0 0 0 Note:. means outputs held static as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 outputs. 4. ll 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled. 5. CPU/2, IOPIC, REF, 48 signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions except PD# = Power Groups: VDDREF, GNDREF = REF, X, X2 GNDPCI, VDDPCI = PCICLK VDD66, GND66 = 3V66 VDD48, GND48 = 48 VDDCOR, GNDCOR = PLL Core VDDLCPU/2, GNDLCPU/2 = CPU/2 VDDLIOPIC, GNDIOPIC = IOPIC 3

ICS9250-2 Power Management Requirements: Singal CPU_STOP PCI_STOP# PD# Singal State Latency No. of rising edges of PCICLK 0 (disabled) (enabled) 0 (disabled) (enabled) (normal operation) 3mS 0 (power down) 2max. Note:. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device. CPU_STOP# Timing Diagram CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU clock) and must be internally synchronized to the external output. ll other clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. LY one rising edge of PCICLK_F is allowed after the clock control logic switched for both the CPU and 3V66 outputs to become enabled/disabled. Notes:. ll timing is referenced to the internal CPUCLK. 2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 3. CPU_STOP# signal is an input singal that must be made synchronous to free running PCICLK_F 4. 3V66 clocks also stop/start before 5. PD# and PCI_STOP# are shown in a high state. 6. Diagrams shown with respect to 33. Similar operation when CPU is 00 4

ICS9250-2 PCI_STOP# Timing Diagram PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output. It is used to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and started such that a full high pulse width is guaranteed. LY one rising edge of PCICLK_F is allowed after the clock control logic switched for the PCI outputs to become enabled/disabled. Notes:. ll timing is referenced to CPUCLK. 2. PCI_STOP# signal is an input signal which must be made synchronous to PCICLK_F output. 3. Internal means inside the chip. 4. ll other clocks continue to run undisturbed. 5. PD# and CPU_STOP# are shown in a high state. 6. Diagrams shown with respect to 33. Similar operation when CPU is 00. 5

ICS9250-2 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 ms. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48 clocks are expected to be stopped in the state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the state may require more than one clock cycle to complete. Notes:. ll timing is referenced to the Internal CPUCLK (defined as inside the ICS9250 device). 2. s shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 33. Similar operation when CPU is 00. 6

ICS9250-2 bsolute Maximum Ratings Supply Voltage........................... 7.0 V Logic Inputs............................ GND 0.5 V to V DD +0.5 V mbient Operating Temperature............ 0 C to +70 C Storage Temperature...................... 65 C to +50 C Stresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T = 0-70º C; Supply Voltage V DD = 3.3 V +/-5%, V DDL = 2.5 V +/-5% (unless otherwise stated) PRMETER SYMBOL CDITIS MIN TYP MX UNITS Input High Voltage V IH 2 V DD +0.3 V Input Low Voltage V IL V SS -0.3 0.8 V Input High Current I IH V IN = V DD 0. 5 µ Input Low Current I IL V IN = 0 V; Inputs with no pull-up resistors -5 2.0 µ Input Low Current I IL2 V IN = 0 V; Inputs with pull-up resistors -200-00 µ Operating I DD3.3OP00 Select @ 00; Max discrete cap loads 68 80 Supply Current I DD3.3OP33 Select @ 33; Max discrete cap loads 80 m Power Down Supply Current I DD3.3PD C L = 0 pf; PWRDWN# = 0 62 200 u Input frequency F i V DD = 3.3 V 2 4.38 6 Input Capacitance C IN Logic Inputs 5 pf C INX X & X2 pins 27 36 45 pf Transition Time T Trans To st crossing of target Freq. 3 ms Settling Time T S From st crossing to % target Freq. ms Clk Stabilization T Stab From V DD = 3.3 V to % target Freq. 3 ms Guaranteed by design, not 00% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters T = 0-70º C; Supply Voltage V DD = 3.3 V +/-5%, V DDL = 2.5 V +/-5% (unless otherwise stated) PRMETER SYMBOL CDITIS MIN TYP MX UNITS Operating I DD2.5OP00 Select @ 00; Max discrete cap loads 9 25 Supply Current I DD2.5OP33 Select @ 33; Max discrete cap loads 22 40 Guaranteed by design, not 00% tested in production. m 7

ICS9250-2 Electrical Characteristics - CPUCLK T = 0-70º C; V DD = 3.3 V +/-5%, V DDL = 2.5 V +/-5%; C L = 20 pf (unless otherwise stated) PRMETER SYMBOL CDITIS MIN TYP MX UNITS Output High Voltage V OH2B I OH = -2.0 m 2 2.2 V Output Low Voltage V OL2B I OL = 2 m 0.3 0.4 V Output High Current I OH2B V OH =.7 V -35-9 m Output Low Current I OL2B V OL = 0.7 V 9 27 m Rise Time t r2b V OL = 0.4 V, V OH = 2.0 V 0.4.2.6 ns Fall Time t f2b V OH = 2.0 V, V OL = 0.4 V 0.4.25.6 ns Duty Cycle d t2b V T =.25 V 45 48 55 % Skew t sk2b V T =.25 V 80 75 ps Jitter, bsolute t jabs2b V T =.25 V -50 6 +50 ps Jitter, Cycle-to-cycle t jcyc-cyc2b V T =.25 V 00 50 ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - CPU/2 T = 0-70º C; V DD = 3.3 V +/-5%, V DDL = 2.5 V +/-5%; C L = 20 pf (unless otherwise stated) PRMETER SYMBOL CDITIS MIN TYP MX UNITS Output High Voltage V OH2B I OH = -2.0 m 2 2.3 V Output Low Voltage V OL2B I OL = 2 m 0.3 0.4 V Output High Current I OH2B V OH =.7 V -35-9 m Output Low Current I OL2B V OL = 0.7 V 9 27 m Rise Time t r2b V OL = 0.4 V, V OH = 2.0 V 0.4..6 ns Fall Time t f2b V OH = 2.0 V, V OL = 0.4 V 0.4.6 ns Duty Cycle d t2b V T =.25 V 45 48 55 % Skew t sk2b V T =.25 V 80 75 ps Jitter, bsolute t jabs2b V T =.25 V -250 70 +250 ps Jitter, Cycle-to-cycle t jcyc-cyc2b V T =.25 V 00 50 ps Guaranteed by design, not 00% tested in production. 8

ICS9250-2 Electrical Characteristics - 3V66 T = 0-70º C; V DD = 3.3 V +/-5%, V DDL = 2.5 V +/-5%; C L =30 pf PRMETER SYMBOL CDITIS MIN TYP MX UNITS Output High Voltage V OH I OH = - m 2.4 3. V Output Low Voltage V OL I OL = 9.4 m 0.25 0.4 V Output High Current I OH V OH = 2.0 V -60-22 m Output Low Current I OL V OL = 0.8 V 25 44 m Rise Time t r V OL = 0.4 V, V OH = 2.4 V 0.5.6 2 ns Fall Time t f V OH = 2.4 V, V OL = 0.4 V 0.5.3 2 ns Duty Cycle d t V T =.5 V 45 48 55 % Skew t sk V T =.5 V 20 250 ps Jitter, bsolute t jabs V T =.5 V -250 00 250 ps Jitter, Cycle-to-cycle t jcyc-cyc V T =.5 V 50 500 ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - PCICLK T = 0-70º C; V DD = 3.3 V +/-5%, V DDL = 2.5 V +/-5%; C L = 60 pf for PCI0 & PCI, CL = 30 pf for other PCIs PRMETER SYMBOL CDITIS MIN TYP MX UNITS Output High Voltage V OH I OH = - m 2.4 3. V Output Low Voltage V OL I OL = 9.4 m 0.2 0.4 V Output High Current I OH V OH = 2.0 V -60-22 m Output Low Current I OL V OL = 0.8 V 25 45 m Rise Time t r V OL = 0.4 V, V OH = 2.4 V 0.5.7 2 ns Fall Time t f V OH = 2.4 V, V OL = 0.4 V 0.5.6 2 ns Duty Cycle d t V T =.5 V 45 50 55 % Skew t sk V T =.5 V 360 500 ps Jitter, bsolute t jabs V T =.5 V -250 80 250 ps Jitter, Cycle-to-cycle t jcyc-cyc V T =.5 V 55 500 ps Guaranteed by design, not 00% tested in production. 9

ICS9250-2 Electrical Characteristics - 48, REF T = 0-70º C; V DD = 3.3 V +/-5%, V DDL = 2.5 V +/-5%; C L = 20 pf (unless otherwise stated) PRMETER SYMBOL CDITIS MIN TYP MX UNITS Output High Voltage VOH5 IOH = -2 m 2.6 2.9 V Output Low Voltage VOL5 IOL = 9 m 0.3 0.4 V Output High Current IOH5 VOH = 2.0 V -35-22 m Output Low Current IOL5 VOL = 0.8 V 7 23 m Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V, 48 2 4 ns Fall Time tf5 VOH = 2.4 V, VOL = 0.4 V, 48 2 4 ns Duty Cycle dt5 VT =.5 V, 48 45 50 55 % Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V, REF.5 2.2 4 ns Fall Time tf5 VOH = 2.4 V, VOL = 0.4 V, REF.5.9 4 ns Duty Cycle dt5 VT =.5 V, REF 45 52 55 % Jitter, Cycle-to-cycle t jcyc-cyc5 V T =.5 V, 48 200 500 ps Jitter, Cycle-to-cycle t jcyc-cyc5 V T =.5 V, REF 800 000 ps Guaranteed by design, not 00% tested in production. Electrical Characteristics - IOPIC T = 0-70º C; V DD = 3.3 V +/-5%, V DDL = 2.5 V +/-5%; C L = 20 pf (unless otherwise stated) PRMETER SYMBOL CDITIS MIN TYP MX UNITS Output High Voltage V OH4B I OH = -2 m 2 2.23 V Output Low Voltage V OL4B I OL = 2 m 0.3 0.4 V Output High Current I OH4B V OH =.7 V -36-6 m Output Low Current I OL4B V OL = 0.7 V 9 22 m Rise Time T r4b V OL = 0.4 V, V OH = 2.0 V 0.4.3.6 ns Fall Time T f4b V OH = 2.0 V, V OL = 0.4 V 0.4.25.6 ns Duty Cycle D t4b V T =.25 V 45 49 55 % Skew t skb V T =.25 V 20 250 ps Jitter, bsolute T jabs4b V T =.25 V -250 30 250 ps Jitter, Cycle-to-cycle t jcyc-cyc4b V T =.25 V 87 500 ps Guaranteed by design, not 00% tested in production. 0

ICS9250-2 General Layout Precautions: ) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: ) ll clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf RC termination should be used on all over 50 outputs. 3) Optional crystal load capacitors are recommended. Capacitor Values: C, C2 : Crystal load values determined by user C3 : 00pF ceramic ll unmarked capacitors are 0.0µF ceramic Connections to VDD:

ICS9250-2 Pin D/2.093 DI. PIN (Optional) Index rea H E/2 PRTING LINE L TOP VIEW BOTTOM VIEW DETIL -e- B 2 c SEE DETIL -E- -D- SETING PLNE.004 C END VIEW SIDE VIEW -C- SYMBOL COMM DIMENSIS VRITIS D N M IN. N OM. M X. M IN. N OM. MX.. 095. 02. 0 D. 720. 725. 730 56. 008. 02.06 2. 087. 090.094 B. 008 -.035 c. 005 -.00 D See Variations E. 29. 295.299 For current dimensional specifications, see JEDEC 95. e 0.025 BSC H. 395 -.420 h. 00. 03.06 L. 020 -.040 Dimensions in inches N See Variations 0-8 Ordering Information ICS9250yF-2-T Example: ICS XXXX y F - PPP - T 56 Pin 300 mil SSOP Package Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, V = Standard Device 2 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.