Politecnico di Torino - ICT School Analog and Telecommunication Electronics A3 BJT Amplifiers»Biasing» Output dynamic range» Small signal analysis» Voltage gain» Frequency response 12/03/2012-1 ATLCE - A3-2012 DDC
Lesson A3: BJT Amplifiers Biasing Output dynamic range Small signal analysis Voltage gain Frequency response Amplifier design Set operating point and use of small signal model Lab experiment 1: small signal measurements References: B1 xxxxxx; B2 Transistor circuits, sect. 1.1, 1.2 12/03/2012-2 ATLCE - A3-2012 DDC
Amplifiers or. What matters in an amplifier Gain Bandwidth Linearity (no distorsion) Noise (low) There is always some nonlinearity Reduce, counteract» Negative feedback, tuned circuits, Exploit to build» VGA/dynamic compressor»mixers» Oscillators 12/03/2012-3 ATLCE - A3-2012 DDC
Transistor models Small signal MOS, MOS-FET, BJT Same linear model (gm or hybrid) Large signal: same method, different models BJT: exponential large signal model (rather simple) MOS: lin/log/quad large signal model (complex!) analytic model for BJT heuristic models for MOS Similar effects Similar countermeasures 12/03/2012-4 ATLCE - A3-2012 DDC
Building the BJT amplifier Basic bias circuit R1 Rc V AL Ic depends on current gain C1 Wide changes in current gain Vi Collector feedback bias R1 Rc V AL R1 to Vc Less dependent on current gain Vi C1 Emitter feedback bias Ic depends on temperature (Vbe) C1 R1 Rc V AL Vi Re 12/03/2012-5 ATLCE - A3-2012 DDC
Final BJT amplifier CE circuit Final bias circuit R1 Rc V AL Stable Ic C1» Versus current gain (emitter feedback) Vi R2 Re2» Versus temperature (Vb >> Vbe) V AL Gain related with bias R1 Rc C1 Separate bias / gain Different AC / DC paths Same approach for CC, CB Vi R2 Re2 Re1 12/03/2012-6 ATLCE - A3-2012 DDC
BJT reference circuit Common Emitter circuit Add BW control R E1 R E2 12/03/2012-7 ATLCE - A3-2012 DDC
Amplifier features and analysis AC amplifier: BJT Common Emitter circuit Input and output AC coupling: C1, C4 Emitter feedback DC: stabilize the bias point AC control the gain Analysis or design: Bias point AC passband gain (linear model) Cutoff frequency Nonlinear model analysis 12/03/2012-8 ATLCE - A3-2012 DDC
Analysis of BJT circuit: step 1 CE amplifier with bipolar transistor (BJT) Find bias point: (I C, V CE ) The bias point must be in the active region: V CE > 0,2 V V CE 12/03/2012-9 ATLCE - A3-2012 DDC
Analysis of BJT circuit: step 2 CE amplifier with bipolar transistor (BJT) Find bias point: (I C, V CE ) The bias point must be in the active region: V CE > 0,2 V Compute small signal parametares: hie, hfe hie, hfe, gm... 12/03/2012-10 ATLCE - A3-2012 DDC
BJT (simplified) models Simplified model for bias point analysis (active area) B I B I B C Simplified model for small signal analysis, CE configuration. Parameters h fe i B or g m v BE B E g m v BE C h ie = V T * h fe /I C v BE g m = I C /V T E 12/03/2012-11 ATLCE - A3-2012 DDC
Bias point analysis DC bias point Small signal parameters depend on I C and (to a lesser extent) on V CE solve bias point first I C I E is fixed by Base-Emitter mesh V CE is related with Collector-Emitter mesh Step 1: compute I C Equation on BE mesh First approximation: I B = 0 (h FE ) Step 2: check V CE value; Equation on CE mesh if > 0,2 V active area 12/03/2012-12 ATLCE - A3-2012 DDC
BE net Ic depends from these devices Ic depends only from Base-Emitter mesh Vcc, R1, R2 are mapped to a unique mesh, with equivalent Thevenin parameters V BB, R B 12/03/2012-13 ATLCE - A3-2012 DDC
BE mesh BE equivalent circuit V BB 12/03/2012-14 ATLCE - A3-2012 DDC
CE net Vce depends from devices in the CE mesh Vce depends from Ic and devices at the Collector node Vce= Vcc-IcRc-IeRe Vce 12/03/2012-15 ATLCE - A3-2012 DDC
Design choices If h fe is large, I B = (V BB V BE )/R B Design variables (for a given Ic) V BB, R B /V B Large V BB Good stability vs ΔV BE (mainly due to temperature) Reduced output dynamic range (V CE ) Small R B Good stability vs Δβ (mainly due to parameters spreading) High power consumption (R B = R 1 //R 2 ) 12/03/2012-16 ATLCE - A3-2012 DDC
Example: bias point, SS parameters R1 R2 Re1 Re2 Rc 120 k 82 k 330 12 k 10 k Vcc 12 V hfe 100 C1 R1 R2 I1 Rc C3 Q1 Ie Re1 Vcc Vbb = Rb = Re2 C2 Ie = Vce = hie = gm = 12/03/2012-17 ATLCE - A3-2012 DDC
Example: bias point, SS parameters R1 R2 Re1 Re2 Rc 120 k 82 k 330 12 k 10 k Vcc 12 V hfe 100 C1 R1 R2 I1 Rc C3 Q1 Ie Re1 Vcc Vbb = 12 * 82 / 202 = 4,9 V Rb = 48,7 k Re2 C2 Ie = 4,3 / (12,33 + 48,7/100) = 0,335 ma Vce = 4,35 V hie = 7,76 k gm = 12,88 ma/v 12/03/2012-18 ATLCE - A3-2012 DDC
Lesson A3: BJT Amplifiers Transistor amplifiers Basic CE circuit Biasing Output dynamic range Small signal analysis Voltage gain Frequency response Design of amplifiers Specifications Set operating point Use of small signal model Lab experiment 1: small signal measurements 12/03/2012-19 ATLCE - A3-2012 DDC
BJT circuit: small signal analysis Parts related with in-band gain (C3 open, C1, C2, C4 shorted) Reminders In signal analysis Vcc = 0 R1, R2 are connected as parallel resistances to Vi 12/03/2012-20 ATLCE - A3-2012 DDC
Gain analysis equivalent circuit Compute the gain using the linear model I B h fe I B Vi R1//R2 h ie Vo Z C Z E v O = i C Z C ; i C = i B h fe ; v i = i B h ie + i B (1+h fe ) Z E 12/03/2012-21 ATLCE - A3-2012 DDC
Results with linear model Gain with linear model (h fe +1) If hfe >> 1 hie becomes negligible with respect to Z E (hfe+1) 12/03/2012-22 ATLCE - A3-2012 DDC
Example: gain with linear model 1 hie = 8,96k hfe = 100 g m = 12,9 ma/v Rc Re1 RL 12 k 330 10 k Vi R1//R2 Ib hie Re1 hfe Ib Rc Vo RL Total load on the Collector: Rc//RL Av = - (12k//10k)*100 / (8,96k + 330*100) = -13 12/03/2012-23 ATLCE - A3-2012 DDC
Example: gain with linear model 2 hie = 8,96k hfe = 100 g m = 12,9 ma/v Rc Re1 RL 12 k 330 10 k Vi Vbe R1//R2 hie Re1 g m Vbe Rc Vo RL Total load on the Collector: Rc//RL Av = 12/03/2012-24 ATLCE - A3-2012 DDC
Example: Ri and Ro hie = 8,96k hfe = 100 g m = 12,9 ma/v Rc Re1 RL 12 k 330 10 k Vi R1//R2 Ib hie Re1 hfe Ib Rc Vo RL Ri =? Ro =? 12/03/2012-25 ATLCE - A3-2012 DDC
Frequency response Wideband AC amplifier Emitter/source feedback» stabilize DC bias point and in-band AC gain A V Z C /Z E Lower band limit: interstage series coupling capacitance Z E frequency behaviour transformer coupling (if any) Higher band limit parallel capacitors towards ground» designed capacitors» wiring parasitic» active device parasitic 12/03/2012-26 ATLCE - A3-2012 DDC
Wideband AC amplifier V u /V i (db) Band pass f (Hz) 1 Low cutoff 10 100 frequency (C1, C2, Ce) High cutoff frequency (C3, Cp1, Cp2) 12/03/2012-27 ATLCE - A3-2012 DDC
High Frequency: L and C parasitics Output Capacitance (load) insert isolation stage (Common Collector/Drain) PCB parasitic L and C Use SMD devices Careful PCB design Active device parasitic (C BC ) multiplied by Miller effect use HF devices with low C BC (GaAs, SiGe,..) proper circuit configuration (Common Base, cascode) 12/03/2012-28 ATLCE - A3-2012 DDC
Parasitic capacitances C1 R1 Rc Cp1 Q1 C3 C4 Vcc Cp2 Ie Vi R2 Re1 Vo Re2 C2 RL Cp1: Base-Collector parasitic (Cbc) C3: designed to set high cutoff frequency 12/03/2012-29 ATLCE - A3-2012 DDC
Miller effect Parasitic Base-Collector capacitance (C BC ) is connected between to nodes with inverting gain A Corrent I cond flowing in C BC : I cond = jωc BC (V B V C ) = jωc BC (V B +AV B ) = jωc BC (A+1) V B (multiplied by Miller effect) Admittance multiplied by (gain +1) Actual equivalent capacitance at Base node: C actual = C BC * (A+1) This capacitance limits the high frequency response Need for Miller free circuit configurations 12/03/2012-30 ATLCE - A3-2012 DDC
Other circuit configurations: CC Common Collector / Common Drain high Zi low Zo No Miller effect (Av 1) Current gain Va Vcc Good for Load separation Increasing Zi Vi Re Q1 Vo Lowering Zo Av 1 12/03/2012-31 ATLCE - A3-2012 DDC
Other circuit configurations: CB Common Base / Common Gate low Zi, high Zu C BC connected to GND: No Miller effect Low Zi Low Zo Voltage gain Q2 Vcc Rc combined with CE in the cascode stage Vi Vo Av gm Rc 12/03/2012-32 ATLCE - A3-2012 DDC
Cascode amplifier Only basic circuit, no bias network Rc Vcc Vi Va Q1: CE stage, Low Zc low V gain Good current gain - Low ΔVce - Low Miller effect Common Base Va Q2 Q1 RL Vu Va Vu Q2: CB stage Good voltage gain - No Miller effect Vi Common Emitter 12/03/2012-33 ATLCE - A3-2012 DDC
Cascode amplifier Common Base stage (CB) C BC parasitic towards ground no Miller effect (C multiplier) provides voltage gain Common Emitter output to low-z load small voltage dynamic provides current gain minimum effect of C BC parasitic capacitance Overall result higher gain at high frequency 12/03/2012-34 ATLCE - A3-2012 DDC
Lesson A3: BJT Amplifiers Transistor amplifiers Basic CE circuit Biasing Output dynamic range Small signal analysis Voltage gain Frequency response Design of amplifiers Specifications Set operating point Use of small signal model Lab experiment 1: small signal measurements 12/03/2012-35 ATLCE - A3-2012 DDC
Lab 1 and lab 2 Design an amplifier from the provided specs A real design:» Multiple solutions» Some specs are implicit» Devices have poorly defined parameters Simulate, build, measure Homework: design, simulation In the lab: build, measure, debug Compare specs/simulation/measurements Linear model lab 1 Nonlinear model lab 2 12/03/2012-36 ATLCE - A3-2012 DDC
Amplifier design specs (2012) Single-Transistor Amplifier with: Voltage gain Vu/Vi = 14 (nominal) Bandwidth -3 db from 100 Hz to 50 khz (minimum) Output dynamic at least 4 Vpp on 12 kω load (or higher) Supply voltage 12 V (nominal) 2N2222A Transistor All features within +/-10%, at ambient temperature Gain and output dynamic at band centre References: Text: design procedure: Cap 1, 1.P1 Lab procedures: Cap 1, 1.L1 web guides: lab 1 12/03/2012-37 ATLCE - A3-2012 DDC
Design sequence Select the circuit: CE with Ze, bias network Vb/Re Choose a no-load dynamic, or Ve, or Rc Stabilty/power/dynamic tradeoff Compute Rc, or no-load dynamic, or Ve Compute Ic Design bias network to get Ic: R1, R2, Re1+Re2 Computer Re1 from gain specs Get C1, C2, C3, C4 from frequency behaviour specs. 12/03/2012-38 ATLCE - A3-2012 DDC
Checks and measurements Passive devices (R and C) available in normalized values Know what they are (E12, E24, ) Only E12 values available in the lab From computed to normalized values The transfer function is modified Component tolerances expand the Bode plot (a line) to a somewhat wide band Specs must lie within the strip Compare measurements with allowed variations of Bode plot 12/03/2012-39 ATLCE - A3-2012 DDC
Theory and practice V u /V i (db) Measured values (with errors) Design specification f (Hz) 1 10 100 1k Design band, taking into account device parameters tolerances 12/03/2012-40 ATLCE - A3-2012 DDC
Lesson A3: final questions Which different types of amplifiers can be found in a radio system? Draw three circuits which can be used to set the operating point of a BJT, discussing respective benefits and drawbacks. Write an approximate expression for Av of a CE amplifier. Which elements limit the bandwidth of amplifiers? Which are the best configurations for high bandwidth amplifiers? List the specifications for an amplifier (what you must know to selct an amplifier from a catalogue). Outline the design procedure for a single transistor amplifier. Describe the lab procedures to measure the frequency response of an amplifier. 12/03/2012-41 ATLCE - A3-2012 DDC