Politecnico di Torino - ICT School Analog and Telecommunication Electronics A3 BJT Amplifiers»Biasing» Output dynamic range» Small signal analysis» ltage gain» Frequency response AY 2015-16 Biasing Output dynamic range Small signal analysis ltage gain Frequency response Lesson A3: BJT Amplifiers Amplifier design Set operating point and use of small signal model Lab experiment 1: small signal measurements References: D. Del Corso: Transistor circuits, sect. 1.1, 1.2 Any texbook on Transistor Amplifiers 01/03/2016-1 ATLCE - A3-2016 DDC 01/03/2016-2 ATLCE - A3-2016 DDC What matters in an amplifier Gain Bandwidth Linearity (no distorsion) Noise (low) There is always some nonlinearity Reduce, counteract» Negative feedback, tuned circuits, Exploit to build» VGA/dynamic compressor»mixers» Oscillators Amplifiers or. Small signal MOS, MOS-FET, BJT Same linear model (gm or hybrid) Transistor models Large signal: same method, different models BJT: exponential large signal model (rather simple) MOS: lin/log/quad large signal model (complex!) analytic model for BJT heuristic models for MOS Similar effects Similar countermeasures 01/03/2016-3 ATLCE - A3-2016 DDC 01/03/2016-4 ATLCE - A3-2016 DDC Building the BJT amplifier Final BJT amplifier CE circuit Basic bias circuit Ic depends on current gain Wide changes in current gain Collector feedback bias to Vc Less dependent on current gain Final bias circuit Stable Ic» Versus current gain (emitter feedback)» Versus temperature (Vb >> Vbe) Gain related with bias Emitter feedback bias Ic depends on temperature (Vbe) Re Independent bias / gain Different AC / DC paths Same approach for CC, CB Ce 01/03/2016-5 ATLCE - A3-2016 DDC 01/03/2016-6 ATLCE - A3-2016 DDC 2016 DDC 1
BJT reference circuit Amplifier features and analysis Common Emitter circuit Bias (DC) AC amplifier: BJT Common Emitter circuit Input and output AC coupling:, C2 Add Gain control with feedback v O Z L Emitter feedback DC: stabilize the bias point ( + ) AC control the gain ( only) Bandwidth (BW) control»hf: C feedback and to GND»LF: coupling C R E1 R E2 Analysis or design: Select or identify the configuration Set or evaluate the Bias point AC passband gain (linear model) Cutoff frequency (frequency response) Nonlinear model analysis next section 01/03/2016-7 ATLCE - A3-2016 DDC 01/03/2016-8 ATLCE - A3-2016 DDC Analysis of BJT circuit: step 1 Analysis of BJT circuit: step 2 CE amplifier with bipolar transistor (BJT) Find bias point: (I C, V CE ) CE amplifier with bipolar transistor (BJT) Find bias point: (I C, V CE ) The bias point must be in the active region: V CE > 0,2 V I C The bias point must be in the active region: V CE > 0,2 V I C hie, hfe V CE Compute small signal parameteres for the bias point: V CE hie, hfe, gm... 01/03/2016-9 ATLCE - A3-2016 DDC 01/03/2016-10 ATLCE - A3-2016 DDC BJT (simplified) models Bias point analysis Simplified model for bias point analysis (to verify operation in active area) Simplified model for small signal analysis, CE configuration. Parameters h fe i B or g m v BE h ie = V T * h fe /I C g m = I C /V T B v BE B I B I B E g m v BE E C C DC bias point Small signal parameters depend on I C and (to a lesser extent) on V CE solve bias point first I C I E is fixed by Base-Emitter mesh V CE is related with Collector-Emitter mesh Step 1: compute I C Equation on BE mesh First approximation: I B = 0 (h FE ) Step 2: check V CE value; Equation on CE mesh if > 0,2 V active area 01/03/2016-11 ATLCE - A3-2016 DDC 01/03/2016-12 ATLCE - A3-2016 DDC 2016 DDC 2
BE net BE mesh Ic depends from these devices Ic depends only from Base-Emitter mesh,, are mapped to a unique mesh, with equivalent Thevenin parameters BE equivalent circuit (h FE = β) V BB V BB, R B 01/03/2016-13 ATLCE - A3-2016 DDC 01/03/2016-14 ATLCE - A3-2016 DDC CE net Design choices Vce depends from devices in the CE mesh Vce depends from Ic and devices at the Collector node Vce = -Ic-IeRe Vce If h fe is large, I B = (V BB V B )/R B V B = V E + V BE βi B R E + V BE Design variables (for a given Ic) V BB, R B /V B Large V BB Good stability vs ΔV BE (mainly due to temperature) Reduced output dynamic range (lower V CEmax ) V B V BE V E Small R B Good stability vs Δβ (mainly due to parameters spreading) High power consumption (R B = R 1 //R 2 ) 01/03/2016-15 ATLCE - A3-2016 DDC 01/03/2016-16 ATLCE - A3-2016 DDC Example A3-e1: bias, small sig. param. Results (example A3-e1) hfe 120 k 82 k 330 12 k 10 k 12 V 100 (50 300) I1 C3 Ie 120 k 82 k 330 12 k 10 k 12 V hfe 100 I1 C3 Ie Vbb = Rb = Ce Vbb = 12 * 82 / 202 = 4,9 V Rb = 48,7 k Ce Ie = Vce = hie = gm = Ie = 4,3 / (12,33 + 48,7/100) = 0,335 ma Vce = 4,35 V hie = 7,76 k gm = 12,88 ma/v 01/03/2016-17 ATLCE - A3-2016 DDC 01/03/2016-18 ATLCE - A3-2016 DDC 2016 DDC 3
Lesson A3: BJT Amplifiers BJT circuit: small signal analysis Transistor amplifiers Basic CE circuit Biasing Output dynamic range Small signal analysis ltage gain Frequency response Design of amplifiers Specifications Set operating point Use of small signal model Lab experiment 1: small signal measurements Parts related with in-band gain: From slide A3-7: C3 open,, C2, Ce shorted) Reminder: In signal analysis = 0, are connected as parallel resistances to 01/03/2016-19 ATLCE - A3-2016 DDC 01/03/2016-20 ATLCE - A3-2016 DDC Gain analysis equivalent circuit Results with linear model Compute the gain using the linear model i B v I i h fe i C B Gain with linear model (h fe +1) v I // h ie Z E Z C v O If hfe >> 1 hie becomes negligible with respect to Z E (hfe+1) If Ze = 0 Max gain v O = - i C Z C ; i C = i B h fe ; v i = i B h ie + i B (1+h fe ) Z E Av = - (Zc hfe)/hie = V T h fe /I C Depends on device parameters (h fe ) 01/03/2016-21 ATLCE - A3-2016 DDC 01/03/2016-22 ATLCE - A3-2016 DDC Example A3-e2 : gain with linear model Results (example A3-e2) hie = 8,96k hfe = 100 g m = 12,9 ma/v 10 k 330 12 k Vbe // Total load on the Collector: // hie g m Vbe hie = 8,96k hfe = 100 Ib hfe Ib g m = 12,9 ma/v hie 10 k // 330 12 k Total load on the Collector: // Av = - (12k//10k)*100 / (8,96k + 330*100) = -13 Av = - Evaluate gain change for hfe 50 500 - Compare with Re = 0 01/03/2016-23 ATLCE - A3-2016 DDC 01/03/2016-24 ATLCE - A3-2016 DDC 2016 DDC 4
Example A3-e3: Ri and Ro Frequency response hie = 8,96k hfe = 100 g m = 12,9 ma/v Ri =? Ro =? 12 k 330 10 k // Ib hie hfe Ib Wideband AC amplifier Emitter/source feedback» stabilize DC bias point and in-band AC gain A V Z C /Z E Lower band limit: interstage series coupling capacitance Z E frequency behaviour transformer coupling (if any) Higher band limit parallel capacitors towards ground» designed capacitors» wiring parasitic» active device parasitic 01/03/2016-25 ATLCE - A3-2016 DDC 01/03/2016-26 ATLCE - A3-2016 DDC Wideband AC amplifier High Frequency: L and C parasitics V u /V i (db) Band pass Minimum required (specs) 1 10 100 Low cutoff frequency (, C2, Ce) Actual (tolerances) f (Hz) High cutoff frequency (C3, Cp1, Cp2) Output Capacitance (load) insert isolation stage (Common Collector/Drain) PCB parasitic L and C Use SMD devices Careful PCB design Active device parasitic (C BC ) multiplied by Miller effect use HF devices with low C BC (GaAs, SiGe,..) proper circuit configuration (Common Base, cascode) 01/03/2016-27 ATLCE - A3-2016 DDC 01/03/2016-28 ATLCE - A3-2016 DDC Parasitic capacitances Miller effect Cp1 C3 C2 C4 Cp1: Base-Collector parasitic (Cbc) C3: designed to set high cutoff frequency Ie Cp2 Parasitic Base-Collector capacitance (C BC ) is connected between two nodes with inverting gain A Corrent I cond flowing in C BC : I cond = jωc BC (V B V C ) = jωc BC (V B +AV B ) = jωc BC (A+1) V B (multiplied by Miller effect) Admittance multiplied by (gain +1) Actual equivalent capacitance at Base node: C actual = C BC * (A+1) This capacitance limits the high frequency response Need for Miller free circuit configurations 01/03/2016-29 ATLCE - A3-2016 DDC 01/03/2016-30 ATLCE - A3-2016 DDC 2016 DDC 5
Other circuit configurations: CC Other circuit configurations: CB Common Collector / Common Drain high Zi low Zo No Miller effect (Av 1) Current gain Good for Load separation Increasing Zi Lowering Zo Va Re Common Base / Common Gate low Zi, high Zo C BC connected to GND no Miller effect ltage gain Av gm Current gain Ai 1 Q2 Av 1 Combined with CE in the cascode stage 01/03/2016-31 ATLCE - A3-2016 DDC 01/03/2016-32 ATLCE - A3-2016 DDC Cascode amplifier Cascode amplifier Only basic circuit, no bias network Va : CE stage, Low Zc low V gain Good current gain - Low ΔVce - Low Miller effect Va Vu Q2: CB stage Good voltage gain - No Miller effect Common Base: Ie ltage gain Va Q2 Common Emitter: Ic Current gain Common Base stage (CB) C BC parasitic towards ground no Miller effect (C multiplier) provides voltage gain Common Emitter output to low-z load small voltage dynamic provides current gain minimum effect of C BC parasitic capacitance Overall result higher gain at high frequency 01/03/2016-33 ATLCE - A3-2016 DDC 01/03/2016-34 ATLCE - A3-2016 DDC Transistor amplifiers Basic CE circuit Biasing Output dynamic range Small signal analysis ltage gain Frequency response Lesson A3: BJT Amplifiers Design of amplifiers Specifications Set operating point Use of small signal model Lab experiment 1: small signal measurements Design an amplifier from the provided specs A real design:» Multiple solutions» Some specs are implicit» Devices have poorly defined parameters Simulate, build, measure Homework: design, simulation In the lab: build, measure, debug Compare specs/simulation/measurements Linear model lab 1 Nonlinear model lab 2 Lab 1 and lab 2 01/03/2016-35 ATLCE - A3-2016 DDC 01/03/2016-36 ATLCE - A3-2016 DDC 2016 DDC 6
Amplifier design specs (2016) Single-Transistor Amplifier with: ltage gain Vu/ = 20 (nominal) Bandwidth -3 db from 80 Hz to 200 khz (minimum) Output dynamic at least 4 Vpp on 10 kω load (or higher) Supply voltage 12 V (nominal) 2N2222A Transistor (or almost equivalent) All features within +/-10%, at ambient temperature Gain and output dynamic at band centre References: Text: design procedure: Cap 1, 1.P1 Lab procedures: Cap 1, 1.L1 web guides: lab 1 Design sequence Select the circuit: CE with Ze, bias network Vb/Re Choose a no-load dynamic (), or Ve, or Stability/power/dynamic tradeoffs Compute, or no-load dynamic, or Ve Compute Ic Design bias network to get Ic:,, + Compute from gain specs Compute, C2, C3, C4 from frequency gain specs. Evaluate Pdmax (always, even if not requested!) 01/03/2016-37 ATLCE - A3-2016 DDC 01/03/2016-38 ATLCE - A3-2016 DDC Checks and measurements Theory and practice Passive devices (R and C) available only in normalized values Know what they are (E12, E24, ) Only E12 values available in the lab From computed to normalized values V u /V i (db) Measured values (with errors) Transfer function modified by normalization / tolerances Evaluate effects Component tolerances expand the Bode plot (a line) to a somewhat wide band Specs must lie within the strip Compare measurements with variations of Bode plot Design specification 1 10 100 1k Design band, taking into account device parameters tolerances f (Hz) 01/03/2016-39 ATLCE - A3-2016 DDC 01/03/2016-40 ATLCE - A3-2016 DDC Lesson A3: final questions Which different types of amplifiers can be found in a radio system? Draw three circuits which can be used to set the operating point of a BJT, discussing respective benefits and drawbacks. Write an approximate expression for Av of a CE amplifier. Which elements limit the bandwidth of amplifiers? Which are the best configurations for high bandwidth amplifiers? List the specifications for an amplifier (what you must know to select an amplifier from a catalogue). Outline the design procedure for a single transistor amplifier. Describe the lab procedures to measure the frequency response of an amplifier. 01/03/2016-41 ATLCE - A3-2016 DDC 2016 DDC 7