1 Rail to Rail Input Amplifier with constant G M and High Frequency Arun Ramamurthy, Amit M. Jain, Anuj Gupta Abstract A rail to rail input, 2.5V CMOS input amplifier is designed that amplifies uniformly at all common mode voltage levels. The design makes use of a rail to rail stage which performs transconductance (G M ) control of the transistors in the input amplifying stage. A summing circuit has also been designed and is used to collect the input from the G M controlled input amplifier and give a single voltage output. A high gain output stage is used to produce a high 68 db gain from the circuit. Care has been taken to avoid any extra pole in the circuit to keep the phase margin high. To get extra phase margin (65 degrees), capacitances have been added in a cascoded Miller design style to increase the value of the capacitance. Resistances have also been added in series to the capacitances to reduce the effect of the zero, pushing frequency at which it exists higher and thereby getting a unity gain frequency (MHz) performance from the circuit. The layout of the circuit has been designed in a compact area saving manner with total die area being.11mm 2. I. INTRODUCTION The advances in VLSI technology are forcing the supply voltages down at a rapid rate due to the constraints of transistor breakdown limits, but the threshold voltages are not scaling down in proportion. Due to this the rising concern in the analog designing world is decreasing signal headroom. Consequently, analog blocks with Rail to Rail inputs are becoming more important for mixedsignal audio and video systems designed in submicron CMOS. In order to obtain an input stage with rail to rail input range, an n and a p channel would have to be driven in parallel. A simple design of this manner would make the g m of such a combination depend on the common mode input voltage. This is the major challenge in this design as the transconductance of the input stage would vary strongly with the common mode input voltage and this would impede the optimal frequency compensation. Moreover, the quiescent current in the output transistors depends on the supply voltage variations. Our design can be primarily split into 3 stages. The first stage would be a rail to rail input stage, the second stage being a summing circuit and the third stage a gain boosting stage consisting of a common source amplifier with current source load. In this paper, we describe the design of a rail to rail 3V CMOS amplifier and the results obtained after simulations of the design using the icfb tool of Cadence. In section II., we describe the working and the functionality of the rail to rail input stage. We describe the most important concerns while designing the stage and how it is able to keep the g m constant. In section III. we describe the working of the summing circuit and in section IV., we show the importance and the effect of the gain boosting stage. We will explain the amount of gain that this stage is able to extract and the effect of the pole that it introduces. In section V. we discuss the frequency and the bandwidth compensation techniques used in this design. Section VI., has the results and the analysis of the results in detail. We discuss the shortcomings in the results and there probable causes. Section VII., contains the conclusion along with the scope for improvements including the a summary of future work on the project. II. CONSTANT G M RAIL TO RAIL INPUT STAGE This is perhaps the most crucial stage of the design as this stage determines the correct functionality of the design in the Rail to Rail configuration. The key issue here is that this stage should ideally have both a constant g m and a limiting current so that the unity gain bandwidth and the slew rate are both maintained over the full common mode input range. V V gsn I ref2 V gsn I ref1 V V gsn V gsn = V CM Figure 1. Common Mode Voltage A simple railtorail architecture can be easily constructed as a composite of the N and the P channel differential pairs. The N channel input pair, is able to reach the positive supply rail and the P channel input pair is able to reach the negative supply rail. The input stage needs a supply voltage of at least 2V gs 2, where Vgs is the source gate voltage of the
2 gates and Vdsat is the voltage across the current source. If the supply voltage is less than this the input stage ceases to work in the middle of the common mode input range. Also, the minimum and the maximum values respectively for V b1 and V b2 are: V b1 < 2p Vtn V b2 > n 2V gsn Vtp But this technique suffers from two drawbacks. First, at the extreme input ranges, only one input pairs is active and so the effective transconductance is halved. Second, the large signal output current is also halved. When used in a conventional twostage amplifier, this means that both the unity gain bandwidth and the slewrate would be a function of the commonmode input voltage. Stabilization of the total g m over the common mode range can be tackled by varying the tail current in the active differential pair, so that the g m doubles when the other is inactive. A simple way of doing this is by increasing the tail current bias on each side by a factor of four, and to add additional devices inside each differential pair which have a width three times the width of active devices. Thus in normal operation 75 percent of the current is diverted through the center path, leaving the tail devices with a nominal tail current of I. This implies a four fold current increase in the effective tail current, and so if square law operation is valid, g m will double, making good the deficit caused by the inactive pair. However, this tail current also adds to the large signal limiting value, and hence the slewing value doubles from 2I to 4I. However, we have used an alternative technique which is to sense that one of the pairs has lost sufficient gate bias to operate and to divert the unused tail current through a bypass transistor, biased at a minimum active level. When current flows through this path, it activates a current mirror of the opposite polarity which has a ratio of. Hence, an additional current of 3I is added to the active pair s tail, raising the operating current to 4I. Again, with square law operation, this doubles the g m in the active pair, restoring the g m to its midrange value. V 1 only the P channel input pair operates. The N channel current switch (M2) conducts while the P channel one is off. The N channel current switch takes away the current I ref1 and directs it to the current mirror, where it is multiplied by a factor of three and added to I ref2. Since I ref1 and I ref2 are equal the tail current of the P channel input equals 4I ref. If the intermediate common mode input voltage is applied, i.e. voltage between.8 and.8, both the Pchannel and the N channel input pairs operate. Now, both the current switches are off. The result is that the tail current of the Nchannel input pair and that of the Pchannel input pair are I ref. If high common mode input voltage is applied, i.e. between.7 and, only the Nchannel input pair operates. The P channel current switch operates (M1), while the Nchannel current switch is off. The Pchannel current switch takes away the current I ref2 and feeds it to the current mirror, where it is multiplied by a factor of 3 and added to the current I ref1. The result of the tail current of the Nchannel input pair equals 4I ref. It can be concluded that g m is almost constant for the entire common mode input range except for the two take over ranges where both the Nchannel and the Pchannel work partially. In this region the value of g m varies about 15%. III. THE SUMMING CIRCUIT There are quite a few considerations while designing a current summing circuit. Firstly, the summing circuit should not impose any headroom constraints on the input structure and thus force some of the input transistors into triode region. This could detrimentally decrease the performance of the opamp. Also, the summingcircuit should have high bandwidth so that it does not significantly degrade the common mode or differential mode bandwidth. The circuit used is the composite of current mirror and current source. If consistent performance is required for application close to the nchannel current mirror should be used whereas for better performance in the region close to the pchannel current source should be used. Input from N channels Vbias2 M1 M2 V Vbias1 Vout V b2 Figure 2. Input Rail to Rail Amplifier Input from P channels Iref The principle of g m can be best understood by dividing the common mode input range into 3 parts. If low common mode voltage is applied, i.e. between and.7 volt then, Figure 3. Summing Circuit One of the most important parts of the design is the biasing of the cascodes in the current summer, particularly on the
3 mirror side. This cascode must operate with the value of which is less than the operating value of V t, otherwise the saturation is not maintained. The gate bias of the mirror cascode must also be set to accommodate large variations in the large signal variations in the current. The discussion regarding the biases in the circuit is found in [3]. The drawn overall circuit includes the input stage, summing stage and the gain boosting stage. When this circuit was carefully sized and all the transistors were brought in saturation, the gain, phase and the bandwidth output looked like this: IV. GAIN BOOSTER STAGE The design constraint for the output stage is that it should provide large enough amplification with the output swing of about 1 V. Moreover not many stages of amplification should be added because of the fact that each additional node adds another pole in the phase response that worsens the phase margin of the design. We have chosen a common source amplifier with current source load as the last stage of the design because of the high gain it provides, simplicity in design and ease of biasing the circuit, unlike other high gain booster circuits like Regulated cascodes. The gain of a common source amplifier with a current source load is: A v = g m *(r n r p ). The gain can very easily be increased by sizing up the N or P transistors i.e. by making changes to the transistor so that the internal resistance changes. Also g m of the transistors can be increased by increasing the current to get higher gain. The sizing of the P transistor and hence the current in this configuration is generally limited by the output swing. For a medium output swing as required by the specifications, size of the P and N transistors are normally determined by the Common Mode input voltage level. The output after this stage is around 7dB. Figure 6. Frequency and Phase Response without frequency response As we can see in the figure the gain and the unity gain frequency meet the specifications but the phase response is negative. So, we use some compensations technique to improve the phase margin. As shown in Figure 7, we add capacitances using the Cascoded Miller technique. Vb1 68 db GAIN Frequency:125M Hz Phase: 23!! V V Vout V out Vb2 Iref V in Figure 7. Complete circuit with frequency Compensation Figure 4 Common Source with constant current load V. PHASE AND BANDWIDTH COMPENSATION The combined figure of the overall circuit so far is drawn: Vb1 Vb2 V Figure 5.Complete circuit without frequency compensation V Vout The Cascoded Miller capacitance is used to increase the capacitance at the output node, which produces the most dominant pole in our design. This decreases the frequency of the dominant pole and the resulting gain, phase and bandwidth plot is shown in Figure 8. This compensation technique shifts the output pole to a frequency of approximately w out = (C M /C gs,out ) * (g mo /C l ) Also an introduction of this capacitor would mean an addition of an extra zero in the circuit, and which can potentially lead to instability. This is taken care by adding another resistor in series with the capacitance, which helps in reducing the effect of the zero introduction. This is given by the formula: W z = 1 / (g m 1 r z )*C m
4 68 db GAIN Frequency :55MHz!! Gain in db Phase: 115 2..5 1. 1.5 2. 2.5 Voltage Vcm V Figure 1. Gain Variations with Vcm Figure 8. Frequency Response with the addition of capacitance The addition of resistance pushes the zero frequency away from the jw axis. This results in the suppression of the zero and the shifting of the zero results in the drop in the rate of decrease of the gain thereby increasing bandwidth in our case. The values of the capacitance and the resistance are then changed in such a way so as to get ideal results as per the required specifications. The simulation result of the final schematic is shown in figure 9. 68 db GAIN Frequency:~ MHz Phase 15 Variation of Gain with Common Mode Input Voltage: We see here that the gain is nearest to the specification at 2.5 V at 7dB and falls to about db with decreasing common mode input voltage. The reason for this consistent drop from 68dB to db is because of the fact that the currents from the N channel transistors are amplified by the N channel transistors in the summing circuit whereas the currents from the P channel transistors are not. This could be avoided by using symmetrical current mirrors both on the N and P side of the summing circuit and using two separate transistors for summing. This essentially requires 5 stacked transistors between and and biasing of these transistors is not trivial. Also in this case the circuit is hyper sensitive to biasing voltages. Variation of Frequency with Common Mode Input Voltage: There is a slight variation in the unity gain frequency with the change in the common mode voltage being applied. The reason for variation in unity gain frequency is the variation of gain which leads to a magnified change in the Cascode Miller Capacitance. We see here that the Unity gain frequency varies between MHz and 115 MHz as shown in figure 11. Figure 9 Frequency Responses with Capacitive and Resistive Feedback We can see that the net gain of the circuit is 68 db, bandwidth is MHz and the phase margin is 75. This circuit is seen to provide us with reasonable results as far as meeting the specifications for the design is concerned. VI. RESULTS AND ANALYSIS According to the specifications, the gain, frequency and phase margins have been simulated for the entire common mode voltage swing from V 2.5V. These results have been discussed here. Frequency MHz 2 1 1 1 12 2..5 1. 1.5 2. 2.5 Voltage Vcm Figure11. Frequency variations with Common Mode Voltage
5 Variation of Phase Margin with Common Mode Input Voltage: The values of phase margin for different common mode input voltages are as shown in Figure 12. The main reason for this change can again be identified as the change in cascoded Miller Capacitance due to gain variations. The phase margin is seen to vary from 58 degrees to 75 degrees. sensitive to the biasing voltage and any change in these voltage significantly affect the overall gain of the opamp. The same degradation in the output is also seen when the there exists a variation in the supply voltage. Similar, degradation in the frequency and phase margin is observed when operated at high temperature. 75 7 65 Phase Margin in Degrees 2..5 1. 1.5 2. 2.5 Voltage Vcm V Figure 12. Variation in Phase margin with Different Temperatures Variation of Gain with varying Temperature: Variation of gain with Temperature is as shown in the Figure 13. Clearly the gain degrades very consistently with the increase in the temperature. The optimal range of operation is from 27 degrees to around 5 degrees C. The operation of opamp beyond this range seriously degrades the performance. The major reason being the fact that the biasing of the current switches in input rail to rail transistor and the summing circuit is done using stacked diode connected P and N transistors across the supply. With the change in temperature the mobility of holes and electrons change and so do the biasing voltages. Gain in db 55 5 45 35 3 25 2 245 25 255 2 265 Supply Voltage mv Figure 14 Variation of Gain with change in supply voltage at 2.5V common mode voltage Variation of Gain with Supply Voltage Variations: As seen in the figure 14 the opmap is very sensitive to the supply voltage variations. The gain of the circuit degrades away from the nominal supply voltage of 2.5V. The use of stacked diode transistors across the supply is the reason for this degradation. Output Voltage Swing: The output swing from 5mV to 2.2V is observed for the worst case. The best case for the output swing is from 2mV to 2.45V. Typical output swing is shown below in figure 15. 1 12 Gain in db 2 2 3 5 7 9 Temperature in Centigrade Figure 13 Variation of gain with change in Temperature at 2.5 V Common Mode Voltage Many transistors in this rail to rail input opamp circuit are Figure15. Plot of the Output Voltage Swing Current State of the Art and our comparison to: In some of the current state of the art circuits, the rail to rail voltage amplifiers have been designed for low voltages of ~.9 V. For such devices complementary input differential
6 amplifiers are made use of. But a majority of these devices have very low frequency response of the order of ~34 MHz. Also, the load being driven is much larger in a few circuits and is upto 2 pf. The gain achieved by most current state of the art circuits is around ~7dB and our results stand quite close to the state of the art in this respect. Most circuits have a phase margin of around 55 65 and we have been able to achieve good results in this aspect. Some circuits are also able to achieve rail to rail output swing. We get an output swing of ~2.2V which is pretty close to rail to rail. VII. LAYOUT IX. CONCLUSION A uniform gain rail to rail input amplifier with a gain of around 65dB and a unity gain frequency of around MHz is designed. We are very close to the current state of the art circuits on parameters like frequency response, phase margin and gain. Though, some of the circuits have been able to achieve rail to rail operation at much lower supply voltage. It was observed that our circuit is quite sensitive to voltage supply and temperature variations. Thus, better and less sensitive biasing circuits with minimal effect on frequency response are desired. ACKNOWLEDGMENT We would like to thank Prof. Michael Flynn and our GSI Brian Duverneay for their immense help and guidance at every step of the project. APPENDIX SCHEMATIC: ~/ group7/railtorail/arun_ckt3 LAYOUT: ~/ group7/railtorail/railtorail_layout Figure16. Layout The area of the design after layout is found to be.11 mm 2. The Layout is DRC and LVS clean and is shown above in Figure 16. After parasitic extraction slight variation in gain was seen. Analysis VIII. SUMMARY OF RESULTS Specification Desired Achieved Specifications Max. Min. SCHEMATIC FOR LVS: ~/ group7/railtorail/circuit_layout REFERENCES [1] R. Hogervost, J.P. Tero, G.H. Ruud, Eschauzier, and J.H. Huijsing A compact Power Efficient 3V CMOS Rail to Rail Input/Output Operational Amplifier for VLSI Cell Libraries, IEEE Journal of Solid State Circuits, Vol. 29, No.6 DECEMBER1994. [2] J. N. Babanezhad, A rail to rail inputcmos Opamp,, IEEE Journal of Solid State Circuits, Vol. 23, No.12 DECEMBER1988. [3] W. R. White, A High Bandwidth Constant and SlewRate RailtoRail CMOS Input Circuit and its Application,, IEEE Journal of Solid State Circuits, Vol. 39, No.5 DECEMBER1997. [4] B. Razhavi, Design of Analog CMOS Digital Circuits McGraw Hill Gain 7dB 68dB 61dB Phase 65 75 58 Output Swing 1V 2V Area.11 mm 2 Power 7.5mW Temperature 27Cto 85C 68dB db Voltage Variation / 1% 68dB 44dB Load 2pf 2pf Frequency MHz 115MHz MHz