Akustica AKU2000 MEMS Microphone MEMS Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
MEMS Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 MEMS Architecture 3.1 Package and Die 3.2 Diaphragm 3.3 Vents 4 Process Analysis 4.1 General Device Structure 4.2 Bond Pads 4.3 Dielectrics 4.4 Metallization 4.5 Vias and Contacts 4.6 Transistors and Poly 4.7 PNP Transistors 4.8 Resistors and Capacitors 4.9 Isolation 4.10 Wells and Substrate 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions 6 Statement of Measurement Uncertainty and Scope Variation 7 References Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Top Package View 2.1.2 Bottom Package View 2.1.3 Package X-Ray 2.1.4 Side View X-Ray 2.1.5 Die Photograph 2.1.6 Die Markings 1 2.1.7 Die Markings 2 2.1.8 Annotated Metal 1 Die Photograph 2.1.9 Die Photograph Annotated with Cross Sections 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Die Corner 3 2.2.4 Die Corner 4 2.2.5 Bond Pads 2.2.6 Standard Logic 3 MEMS Architecture 3.1.1 Package Cross Section 3.1.2 Microphone Port 3.1.3 PWB Cavity 3.1.4 Die Backside 3.2.1 Microphone Diaphragm in Tilt View 3.2.2 Edge of Metal 1 Diaphragm in Tilt View 3.2.3 Serpentine Metal 1 Diaphragm 3.2.4 Left Diaphragm Edge 3.2.5 Right Diaphragm Edge and Cavity 3.2.6 Right Edge of Diaphragm 3.2.7 Diaphragm Edge in Tilt View 3.2.8 Metal 1 Diaphragm 3.3.1 Top View Vents 3.3.2 Tilt View Vents 3.3.3 Vents and Cavity 3.3.4 Vents
Overview 1-2 4 Process Analysis 4.1.1 General View of AKU2000 4.1.2 Die Edge 4.1.3 Die Seal 4.2.1 Bond Pad 4.2.2 Left Bond Pad Edge 4.2.3 Right Bond Pad Edge 4.3.1 Passivation 4.3.2 IMD 2 4.3.3 IMD 1 4.3.4 PMD and Gate 4.3.5 PMD 4.4.1 Metal 3 4.4.2 Minimum Pitch Metal 2 4.4.3 Minimum Pitch Metal 1 4.5.1 Stacked Vias 4.5.2 Via 2 4.5.3 Minimum Pitch Via 1s 4.5.4 Minimum Pitch Contacts to Diffusion 4.6.1 NMOS Transistor 4.6.2 PMOS Transistor 4.6.3 Transistor with Glass Etch 4.6.4 Edge of Gate 4.7.1 PNP Band Gap Reference 4.7.2 Band Gap PNP Transistor 4.7.3 SCM Band Gap Transistor 4.7.4 Field Plated Lateral PNP Transistor 4.7.5 Lateral PNP in Cross Section 4.7.6 SCM Lateral PNP Transistor 4.8.1 Plan View Resistors and Capacitors 4.8.2 Double Poly Capacitors 4.8.3 Interpoly Dielectric 4.8.4 Poly Resistors 4.9.1 Minimum Width Isolation 4.9.2 Poly Over Isolation 4.10.1 SCM Peripheral N-Well 4.10.2 SRP Peripheral P-Well and Substrate 4.10.3 SRP Peripheral N-Well
Overview 1-3 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 Package, Die and Bond Pad Sizes 4 Process Analysis 4.3.1 Dielectric Thicknesses 4.4.1 Metallization Vertical Dimensions 4.4.2 Metallization Horizontal Dimensions 4.5.1 Via and Contact Dimensions 4.6.1 Peripheral Transistor Horizontal Dimensions 4.6.2 Peripheral Transistor and Polycide Vertical Dimensions 4.10.1 Die Thickness and Well Depths 5 Critical Dimensions 5.1.1 Package, Die and Bond Pads 5.1.2 Minimum Pitch Metals 5.1.3 Minimum Pitch Contacts and Vias 5.1.4 Peripheral Transistor Horizontal Dimensions 5.2.1 Vertical Dimensions Dielectrics 5.2.2 Vertical Dimensions Metals 5.2.3 Transistor Vertical Dimensions 5.2.4 Die and Wells Vertical Dimensions
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