DesignCon 2009 Prediction and Measurement of Supply Noise Induced Jitter in High-Speed I/O Interfaces Hai Lan, Rambus Inc. e-mail: hlan@rambus.com Ralf Schmitt, Rambus Inc. Chuck Yuan, Rambus Inc.
Abstract This paper presents a systematic approach for analyzing supply noise induced timing jitter in high-speed I/O interfaces. The proposed method combines frequency-dependent supply noise jitter sensitivity profile with supply noise spectral content to predict the jitter generated by the supply noise. Distributed power grid model and device-level current profiles are used to obtain time- and frequency-domain supply noise. Jitter sensitivity is extracted by sweeping the frequency of single tone disturbance added to ideal supply. Supply noise and jitter sensitivity are also measured by auto-correlation-based on-chip noise monitor circuit. The predicted supply noise induced jitter is shown to correlate well with the measurement data for a high speed I/O interface operating at 6.4Gbps. Authors Biography Hai Lan is a Senior Member of Technical Staff at Rambus Inc., where he has been working on on-chip power integrity and jitter analysis for multi-gigabit interfaces. He received his Ph.D. in Electrical Engineering from Stanford University, M.S. in Electrical and Computer Engineering from Oregon State University, and B.S. in Electronic Engineering from Tsinghua University in 2006, 2001, and 1999, respectively. His professional interests include design, modeling, and simulation for mixed-signal integrated circuits, substrate noise coupling, power and signal integrity, and high-speed interconnects. Ralf Schmitt received his Ph.D. in Electrical Engineering from the Technical University of Berlin, Germany. Since 2002, he is with Rambus Inc, Los Altos, California, where he is an engineering manager responsible for power integrity on chip, package, and system level. His professional interests include on-chip signal integrity, power integrity, timing analysis, clock distribution, and high-speed digital circuit design. Xingchao (Chuck) Yuan received his M.S. and Ph.D. degrees in Electrical Engineering from Syracuse University, in 1983 and 1987, respectively, Syracuse, New York. Since 1998, he is with Rambus Inc, Los Altos, California, where he is an engineering manager responsible for designing, modeling, and implementing Rambus multi-gigahertz signaling technologies using conventional interconnect technologies. He has over eighty publications in technical journals and conferences. His professional interests include computational electromagnetic methods and high speed signaling technologies for multigigabit applications.
I. Introduction Today s high speed I/O interfaces operating at multi-gigabit data rates [1] are posing more and more challenges to meet the design specifications under the comprehensive constraints, including lower supply voltage headroom, higher sub-threshold leakage, tighter timing budget, and tougher signal integrity, etc. Among all these increasingly difficult challenges, achieving very low jitter to meet the timing budget is one of the most critical tasks in optimizing multi-gigabit I/O interface design. It is a common understanding that the dynamic range of supply noise needs to be confined because it directly affects the available voltage headroom for proper device operation and therefore causes circuit performance degradation or even leads to system malfunction. More importantly, power supply noise is one of the major sources of timing jitter. It directly contributes to the jitter of the system internal timing sources, e.g., PLL and DLL circuits. Moreover, it affects the timing of other circuits, e.g., clock distribution and output driver circuits. In the past, there have been many efforts, focusing on optimizing the worst-case supply noise dynamic range to meet the supply noise budget. However, supply noise dynamic range alone is insufficient to fully characterize its impact on jitter. In [2], we presented our on-chip noise measurement technique, where the supply noise dynamics were reported to establish the understanding of the dependence of supply noise characteristics on supply domain nature, data activity, and power distribution network (PDN). We recently reported the jitter profile analysis in [3], where the results showed that the jitter sensitivity is circuit-dependent and the jitter generated by supply noise is dominated by jitter contributions at medium frequencies, way below the data rate or the frequency of internal clock signals. Based on the foundation laid out in our past work, this paper will focus on combining the supply noise characteristics and jitter sensitivity to predict and correlate the supply noise impact on system jitter. A systematic approach of analyzing power supply noise induced jitter is proposed in this paper. The overall jitter impact generated by supply noise is determined by two factors, the characteristics of supply noise itself and how the system responds to the noise present on its supplies. Therefore, it is necessary to analyze the frequency spectrum of supply noise and the frequency-dependent jitter sensitivity of supply noise for circuits and systems. This paper will discuss both the simulation methodology to predict supply noise spectrum and jitter sensitivity and the measurement technique to characterize them. Combining these two aspects of the analysis results, it will be shown that the supply noise induced jitter can be predicted and correlates well with measured data in a high speed I/O interface operating at data rate at 6.4Gbps. In particular, the simulation methods for predicting supply noise and jitter sensitivity are discussed first. An on-chip simulation methodology with transistor-level accuracy is developed to predict full-chip dynamic supply noise. Device-level current profiles are extracted by inserting the measurement probes into full transistor or Co-sim simulation environment. The extracted current profiles are then back-annotated and connected properly to power grid RC models extracted from GDSII. Depending on different supply, power distribution network, and activity, characteristics of transient supply noise and its frequency spectrum is simulated. The jitter sensitivity is extracted by running circuit simulations. Single tone sinusoidal signal is used as an intentional disturbance to the circuits ideal supply. Time interval error (TIE) in time domain is obtained from the
simulated clock or toggled data waveform. It is then analyzed in frequency domain. The jitter component present at the frequency corresponding to the disturbance signal tone is used to determine the jitter sensitivity at that frequency. By sweeping the frequency, the jitter sensitivity profile is obtained. We then discuss our on-chip supply noise measurement techniques reported earlier in [2]. There have been further enhancements on the characterization of the supply noise power spectral density and jitter extraction. They are discussed to allow better interpreting and thus correlating measured data with simulation data. Finally, by combining the supply noise spectrum together with the noise sensitivity profiles, we predict the supply noise induced jitter for the interface. Understanding the noise spectrum and the noise sensitivity profiles allows us to direct the circuit and power distribution design to reduce supply noise induced jitter in these interfaces. This paper is organized as follows. First, an overview of the supply noise induced jitter followed by a brief description of the test system under this study is given in Section II. The frequency spectrum-based approach of characterizing supply noise induced-jitter is introduced in Section III, including the discussion of the underline assumptions and the proposed methodology. Section IV addresses the simulation aspects of the proposed approach, including pre- and post-layout supply noise simulation methods as well as how to simulate jitter sensitivity profile in both conventional and faster ways. The measurement methodologies is discussed in Section V, where how to extract supply noise and jitter sensitivity using on-chip noise monitor and noise generator is presented following a review of the circuit implementation of the measurement module. Section VI presents the ultimate results of supply noise induced jitter predication as well as the correlation between the measurement and simulation. Finally, conclusion will be drawn in Section VII. II. Overview II.1 Supply Noise Impact on Jitter In high speed I/O interfaces, power supply noise is a major noise source to link jitter. As the data rate continues to increase, smaller total jitter budget has to be met to achieve sufficient system timing margin. Ideally, this can be achieved by scaling the supply noise budget inversely proportional to the interface data rate. Assuming a nearly constant sensitivity of the circuits to supply noise, this scaling assures that supply noise induced jitter consumes a constant fraction of the bit time (UI) at any data rate. However, in current technology nodes, simply scaling the supply noise budget is not practical. As a result, more detailed, comprehensive characterization of the supply noise-induced jitter has become crucial. The supply noise causes timing variations in the circuit controlling the internal timing of the interface. Understanding the supply noise-induced jitter proves to be influential and beneficial to decide better clocking architecture, choose less sensitive circuit topology and fine tuning their parameters, and even more importantly, to guide the PDN optimization so that the limited PDN design resources can be allocated targeting at the most sensitive area.
Minimizing the supply noise induced jitter is the ultimate goal of power integrity in ultra high speed I/O interface systems. In the past, the primary target of PDN design has been to lower the impedance profile over wide frequency. The supply noise issue has been mostly concerning about reducing the worst peak-to-peak dynamic range. While aiming at these goals is a commonly accepted practice in power integrity analysis, they are usually overly pessimistic and sometimes hard to achieve without requesting additional on- or off-chip resources, resulting in increased system cost. In reality, in a typical I/O interface system, some circuits are more sensitive to supply noise in one frequency range and less sensitive to supply noise in other frequency ranges. Many aspects of nature like this can be and should be utilized to help optimize the chip and system design. Therefore, supply induced jitter in an interface system is the result of the interaction of two separate and largely independent parameters. The first parameter is the amplitude and spectrum of the supply noise generated in the system. The second parameter is the sensitivity of the interface circuits to noise at different frequencies. Understanding both parameters independently as well as the interaction of these parameters provides us with insight necessary to predict and optimize supply noise induced jitter in the system. II.2 Multi-gigabit I/O Test System To analyze the on-chip power supply noise characteristics, a test system shown in Figure 1 was investigated. The interface system is a serial-to-serial transceiver delivering high bandwidth point-to-point interconnection across system backplanes at data rates up to 6.4Gbps. It integrates eight bi-directional serial links, each operating at a data rate of up to 6.4GHz. Additionally, it contains a Data Route Logic to control the data flow traffic between the different links and Control Logic containing general logic for the initialization of the links as well as logic used for characterization like pattern generators. Figure 1. Multi-gigabit I/O interface test system. Four separate on-chip supply domains are adopted for different circuit blocks inside the test system. The sensitive timing controlling circuits, e.g., PLLs, are supplied by V DDA. All the circuits inside the eight link slices are supplied by V DD, except for channel termination resistors supplied by V TT. The control logic and data route logic are powered by V DDCORE. In this paper we will focus on V DD and V DDA because they are the major
sources of system jitter. On-chip supply noise measurement circuits were integrated on the interface test chip. Two on-die noise monitors are dedicated to each supply domain. The two noise monitors are used to capture the supply voltage statistics and convert them to digital outputs for post-processing so that the supply voltage dynamics can be recovered. III. Frequency Domain Characterization of Supply Noise Induced Jitter The supply noise induced jitter is a combined effect of two largely independent factors. The first one is supply noise itself, which serves as the stimulus to the system to impact jitter performance. The second one is how the system reacts to the stimulus in generating jitter correspondingly. From the system point of view, this process can be modeled by an LTI system responding to an input stimulus. To characterize such a system, naturally the most convenient means is to model both the input stimulus and system transfer function in frequency domain. Therefore, in this work we propose a frequency domain-based methodology to characterize the supply noise induced jitter. It is, however, important to first discuss the underline assumptions under which the proposed method is valid. III.1 Assumptions Basically, there are two fundamental assumptions. First, as typical for power distribution impedances, the impedance achieves small amplitudes at low and high frequencies, but shows a large amplitude peak at medium frequencies, where the inductance of the package system resonates with the on-chip capacitors. The resulting noise on the power supply rail of the system can be calculated as the product of the current spectrum I noise (f) and the impedance of the power supply network Z PDN (f): V noise ( f ) = Z ( f ) I ( f ) (1) PDN noise Figure 2. Current profile and normalized typical impedance profile from a multi-gigabit I/O system.
The simulated current profile and the supply impedance profile from the PDN model of the test system are shown in Figure 2. It is expected to see the supply noise spectrum features the spectral peaks as the original current spectrum, but the background level of the supply noise spectrum follows the profile of the supply impedance Z PDN (f). This effect emphasizes any noise contributions at medium-frequency, where the supply impedance Z PDN (f) shows a large amplitude due to package-chip resonance. Figure 3. Linearity on supply noise-induced jitter. Another important assumption is that the supply noise induced jitter component in frequency domain is a linear function of supply noise at the same frequency component. Figure 3 shows the simulation validation of the assumed linearity. Moreover, this assumption was also supported by two important measurement observations in our study. First, exciting single-frequency supply noise generates single frequency jitter at the same frequency. Second, jitter amplitude is a linear function of noise amplitude, given that the circuits are operating in the linear region under normal system operation. Given above justifications, it now makes sense to introduce the jitter sensitivity due to supply noise as the ratio of the resulting jitter in ps to 1mVpp amplitude supply noise at a frequency f: J ( f ) S ( f ) = (2) V ( f ) III.2 Frequency Domain-based Methodology Figure 4 illustrates the flow for the proposed frequency domain-based supply noise induced jitter characterization. To obtain the jitter for the system operating in different modes with various activities, we need to get the activity-dependent supply noise spectral content V(f) and the activity-independent but likely operating mode-dependent jitter sensitivity profile S(f). Under the above LTI assumption, the jitter spectrum J(f) can be generated by multiplying the stimulus V(f) and the transfer function S(f): J ( f ) = V ( f ) S( f ) (3)
Figure 4. Diagram of frequency domain-based approach for characterizing supply noise induced jitter. The jitter spectrum J(f) as stated above serves as a key parameter in characterizing the jitter impact due to supply noise in a system. It can be used in various ways to understand various aspects of the supply noise induced jitter. First, the spectral profile itself indicates over frequency where the strong jitter components are located and how they are related to the system operating conditions, e.g., reference clock frequency, data rate, operation mode, transaction data pattern, etc. Second, since it is a complete characterization on jitter in frequency domain, it can be applied to derive the time domain counterpart of jitter. The worst peak-to-peak jitter j pp can derived as: 0 j pp = 2 J ( f ) df (4) Often it is also constructive to use the accumulated jitter percentage to help identify the biggest jitter contribution components in frequency domain. The accumulated jitter percentage is defined as follows: f J ( f ) df 0 η ( f ) = 100% (5) 0 J ( f ) df Moreover, the time domain jitter, j(t), for instance, TIE, can be reconstructed by performing inverse Fourier transform of J(f): j( t) = 0 J ( f ) e j2πft df (6) This general approach is to be used for both simulation and measurement in this work. The required enabling methodologies and techniques will be discussed in the following sections for simulation and measurement, respectively.
IV. Simulation Methodologies In order to comprehend the supply noise dynamics, both simulation methodology and measurement technique are needed so that not only the system supply noise can be predicted reliably in both pre- and post-layout design phases but also the actual supply noise under chip operation in real life can be monitored and verified. This section discusses the simulation aspects and the measurement methodology will be discussed in Section V. In the past, there have been many efforts with focus on optimizing the power deliver network to reduce the worst-case supply noise dynamic range to meet the supply noise budget, e.g., [4], [5]. CAD algorithms to extract power grids to be used in supply noise simulation have also been reported, e.g., [6]. In this section, both pre- and post-layout simulation methodologies are discussed first, including different power distribution network modeling approaches suitable for pre- and post-layout analysis and current profile extraction. The simulation methodologies will be applied to simulate the supply noise profile. It is followed by two simulation approaches to characterize the jitter sensitivity profile. IV.1 On-chip Supply Noise Simulation Simulating on-chip supply noise requires modeling and extraction of four components: off-chip power distribution network (off-chip PDN), on-chip power distribution network (on-chip PDN), on-chip supply current profiles, and on-chip decap distribution. The off-chip PDN is typically modeled by passive RLC components resulting from voltage regulator, PCB, and package parasitics as well as low and medium frequency decoupling capacitances. The on-chip PDN represents the physical power grids from die pads to all over the chip, typically including RC parasitics. The third component is the current profiles as the stimulus to the complete PDN system. Lastly but very importantly, it is required to have the on-chip decap information not only just the total amount but also the distribution. All these components are the inputs to the simulation engine [7] to simulate the on-chip supply noise dynamics. Figure 5. Supply noise simulation flow diagram.
Figure 6. Schematic of pre-layout on-chip supply noise simulation IV.1.1 PDN Modeling The primary design target of a PDN is to deliver an off-chip power supply to on-chip grids with maximum delivery efficiency and minimal degradation and noise. A complete PDN includes off-chip and on-chip PDN, for which different modeling approaches should be applied. Typically, an off-chip PDN consists of VRM, PCB, and package, where the associated parasitics are modeled by resistances and inductances. Decoupling capacitances, ESC, are deployed on PCB and package to filter the low and medium frequency noise in the power supply, where the associated parasitics are modeled by ESR and ESL. A typical off-chip PDN is illustrated in Figure 6. There are well established methods to extract all the parasitics. The on-chip PDN can be modeled in two fashions, lumped modeling and distributed modeling. Lumped modeling method is suitable for pre-layout supply noise estimation. Although it assumes that on-chip supply has insignificant spatial dependence, this method can largely capture the overall supply noise characteristics when the circuit die size is small. A simple lumped on-chip model is shown in the middle part in Figure 6. On-chip power grids are simplified and lumped into R onchip, which can be estimated by using the static IR drop specification and the nominal DC power supply current. All the on-chip decaps are lumped into C decap, which represents the overall capacitive decoupling effects from intentional decaps (MOS or MIM caps), parasitic capacitances due to non-switching gates in digital circuits, and interconnect parasitic capacitances. The loss associated with C decap is represented by R decap, which is determined by the fabrication process-dependent relaxation time constant as: R = τ / C (7) decap process decap To model the effect of supply voltage collapse to the first order, two additional elements, R shunt and I feedback, are introduced into the on-chip lumped model as following: R V no min al shunt = (8) α I DC
I feedback = α I (9) DC where α is an empirical factor representing the portion of the current compensated from the average current degradation. Depending on the type of circuit, the value of α ranges from 0 to 1. The smaller α is, the less the voltage collapse effect is. Despite the ease of use and reasonable accuracy of lumped on-chip model, distributed on-chip model is much more preferable in post-layout supply noise simulation. Full chip power grids need to be extracted to get the detailed, distributed 2-D RC models. Distributed on-chip decaps should be correctly identified and accurately estimated. Moreover, current sink nodes connecting the circuit blocks or transistor terminals need to be back-annotated so that the provided current profiles can be correctly tied to. The extraction of distributed on-chip PDN model is performed using a commercially available tool [7]. IV.1.2 Decap and Current Extraction In supply noise simulation environment, it is usually prohibitively expensive to simulate the entire circuit with fully extracted on-chip PDN model. Therefore, transient supply currents are usually first extracted by simulating the circuit under ideal supply environment. The extracted current profiles are then used to replace the active devices and equivalently represent the current draw due to circuit activities. Extracting the lumped, top-level current profiles for all the supply domains is often straightforward, which typically only involves probing the current draw from the voltage sources. This type of current profiles suits the need for pre-layout simulation. It can also be used in post-layout simulation if being properly distributed among all the current sink nodes. Figure 7. On-chip decap and current distribution maps from the test I/O system. To achieve better accuracy in post-layout simulation, detailed current profiles should be extracted at the sub-block circuit-level or even down to the device-level. This can be done by first generating current probes from the circuit netlist by recognizing all the nodes connected to supply or ground and then including them into circuit simulations. The resulted current profiles are then connected to the back-annotated on-chip PDN at their corresponding physical locations.
Although the current profiles are considered as the sources of supply noise, it should be pointed out that the supply voltage noise is determined by both current profile and impedance profile. To minimize the dynamic range of the resulted supply voltage, the design effort should include trying to avoid overlapping the impedance resonance frequency with any strong components in the current profile [2]. IV.1.3 Supply Noise Simulation Results The pre- and post-layout simulation methods described above have been applied to one of the link slices in the I/O interface test system to predict the on-chip supply noise in VDD and VDDA domain. The link slice under test was configured to continuously transmit the PRBS7 data pattern bit stream at 6.4Gbps with PLL reference clock at 640MHz. The same condition was also set for the test system in the lab and the on-chip supply noise measurement monitors were used to capture the VDD and VDDA supply noise transient waveform in real-time sampling scope mode and their frequency spectrum in autocorrelation mode. Figure 8. Post-layout worst dynamic IR drop map. The off-chip PDN models are extracted using EM simulation. The lumped-model of on-chip PDN for pre-layout simulation is determined based on design knowledge, process information, and static IR drop target. The distributed on-chip power grid and decaps for post-layout simulation are extracted by a commercially available tool [7]. The current profiles are extracted by probing the top level supply currents during a full chip transistor-level circuit simulation. Apply the above PDN model and current profiles, prelayout simulation was carried out using Hspice and post-layout simulation was performed using the tool in [7]. The simulated post-layout dynamic IR drop map is presented in Figure 8, showing the worst case peak-to-peak noise distribution. Figure 9 and 10 summarizes the pre- and postlayout simulation results for VDD and VDDA, respectively. As seen in Figure 9(a)-(b), the peak-to-peak VDD supply noise from pre-layout simulation and post-layout
simulation are 42mVpp and 37mVpp. Both simulation results are in line with each other. More insight can be observed by looking at the frequency spectrum shown by Figure 9(c)-(d). All noise spectra reveal that the strong frequency components are at the data rate frequency as well as its sub-harmonics for VDD. This reflects the fact that the VDD current profile is shaped by the VDD PDN impedance profile, which tends to emphasize more at the 100-300MHz range, the typical PDN resonance frequency. Figure 10(a)-(b) shows that the VDDA peak-to-peak noise from two simulation methods and measurement data all agree with each other, 12mV PP and 16mV PP, respectively. If comparing the frequency spectra shown in Figure 10(c)-(d), one can clearly see that the measurement data shows a spike at 640MHz. The pre-layout simulation also shows the strong presence at this frequency. The post-layout simulation, however, shows a hump at around 640MHz. (a) (b) (c) (d) Figure 9. Simulated V DD supply noise in the I/O interface test system with data rate of 6.4Gbps. (a)transient waveform from pre-layout simulation, (b)transient waveform from post-layout simulation, (c)spectrum from pre-layout simulation, and (d)spectrum from post-layout simulation.
(a) (b) (c) (d) Figure 10. Simulated V DDA supply noise in the I/O interface test system with data rate of 6.4Gbps. (a)transient waveform from pre-layout simulation, (b)transient waveform from post-layout simulation, (c)spectrum from pre-layout simulation, and (d)spectrum from post-layout simulation. IV.2 Jitter Sensitivity Profile Simulation IV.2.1 Conventional Approach A widely adopted approach for determining the jitter sensitivity profile is to use brute force transient simulation with any standard circuit simulator, e.g., HSPICE. Since the sensitive jitter analysis is concerned here, it is preferred to use post-layout SPICE netlist incorporating RC parasitics and distributed RLC models if long, multi-ghz clock wires are used. Usually a single-tone sinusoidal signal with small but sufficient amplitude is injected into supply node as the stimulus. After the circuit simulation stables, the resulting jitter transient can be recorded by observing the output clock TIE. Performing FFT on the output clock TIE, the jitter spectrum can be obtained. It is expected to see a spike in the jitter spectrum at the same frequency as the stimulus signal. Thus, the jitter sensitivity at this frequency can be determined as the ratio of the observed jitter spike amplitude to the stimulus amplitude. Figure 11 shows an example of the spectrum of the jitter as the result of 70MHz, 50mVpp sinusoidal supply noise. Same procedure has to be performed at multiple frequency points to obtain the jitter sensitivity profile over
frequency. It is not surprising to see that each such simulation takes about 10 hours to run. Figure 11. Supply noise induced jitter spectrum from transient simulation. IV.2.2 Faster Approach Circuits like PLL/DLL/DCC are strongly nonlinear in voltage-domain but inherently linear in other domains like phase/delay/duty-cycle-domain. Mapping the voltage variables to/from the variables in linear domain would allow characterization of circuits by using the linear analysis techniques rather than transient simulations. An efficient approach for extracting jitter sensitivity profile was recently introduced in [12]. This approach exploits variable domain transformation to map harder nonlinear voltage domain problem into easier linear phase domain problem. Figure 12 shows the phase transformation application in PLL characterization Figure 12. Phase domain transformation in PLL [12]. In order to apply the method to simulate jitter sensitivity, two variable domain translators were implemented in [12] as Verilog-A modules. One is phase-to-voltage translator and the other one is voltage-to-phase translator. The phase domain simulation is performed by using Spectre-RF periodic steady state (PSS) and periodic AC (PAC) features. PSS carries out large signal analysis to compute the periodic steady-state response of a circuit at a specified fundamental frequency. PAC analysis linearizes the circuit over its PSS response. The impact of small perturbations is obtained using linear analysis method, which results in much faster simulation. Figure 13 shows the example of jitter sensitivity profile simulated by using the PSS/PAC method. It takes about 1 hour to get PSS converged, followed by minutes to run PAC to sweep over the desired frequency range to obtain the final sensitivity profile.
Figure 13.Example of jitter sensitivity simulated by PSS/PAC method IV.2.3 Jitter Sensitivity Simulation Comparison The transient simulation approach is straight forward to setup and simulate. In most cases, it offers the best accuracy and is regarded as golden standard. However, the transient analysis involved is notably time consuming and it gets ever more so when simulating the jitter sensitivity at relatively low frequency in the order of 10MHz. Instead of directly solving time domain problem, the PSS/PAC-based approach essentially solves small-signal problem around its DC operating point in the periodic domain sense. Therefore, it only takes minor simulation to sweep over frequency range in order to get the jitter sensitivity profile. In principle, it promises much faster solution. However, its main challenge is PSS convergence. Sometimes it is difficult to get PSS converged even for experienced engineers. Figure 14 shows the comparison between these two methods on the jitter sensitivity profile extraction for a typical PLL design. Good correlation can be seen in terms of the peaking frequency location and spike. Figure 14.Comparison between two approaches on jitter sensitivity extraction.
V. Measurement Techniques In the past, various measurement circuits have been designed to observe the over- and under-shoot events over certain time window [8] or capture the repetitive supply noise in sub-sampling scope mode [9]. However, these techniques can only be used to measure specific properties of supply noise and can not capture multi-gigahertz high frequency noise components due to their underlying time domain measurement scheme. To overcome these limitations, an autocorrelation-based measurement method and circuits have been recently introduced in [10]. For our analysis, we need to measure supply noise on the internal power rails for frequencies up to a multiple of the fastest toggle frequency. For a system with a data rate of 6.4Gbps, i.e. with the fastest data toggle rate of 3.2GHz, noise has to be measured for frequencies up to 10GHz or more. Measuring supply noise on an internal supply rail at these high frequencies is a challenging task, and requires special noise monitor circuits. We are primarily interested in the frequency domain spectrum of the supply noise. For correlation with simulated noise waveforms, however, we would also like to have the ability to measure characteristic supply noise waveforms in time domain. Thus, we need a noise monitor with sufficiently high bandwidth suitable for frequencies beyond 10GHz, which can not only provide measurement results for the frequency domain noise spectrum but also can be used to construct characteristic time domain noise waveforms. V.1. On-chip Supply Noise Measurement Module V.1.1 Noise Monitor Circuit Figure 15. On-chip supply noise monitor circuit. Figure 15 shows the circuit schematic of the noise monitor implemented along with the test gigabit I/O system. The supply voltage being monitored is first sensed by the sample-and-hold circuit. The sampling circuit is implemented using PMOS switches so that it is easier to measure the VDD supply. Moreover, simple PMOS switch can achieve very high bandwidth, which is necessary for the monitor system to adequately capture the dynamic behavior of the supply noise up to several harmonics of the data rate. During the hold mode, the buffered sampled voltage is used as the control voltage to set the frequency of a VCO. The VCO is implemented as a ring oscillator to obtain high frequency since ring type oscillators can easily achieve several times FO4 cycle time. As shown in Figure 4, the output of the VCO is the input to a 16-bit counter. The counter is enabled during the same specified time window as the hold time window of the hold
circuit to digitally estimate the VCO frequency by counting the number of clock edges of the VCO output. The resulting digital count is proportional to the VCO control voltage, which is the sampled supply voltage. After obtaining the VCO calibration curve, the original supply voltage can be easily derived from the stored digital counts. The counting process actually ensures that the averaged VCO frequency gets measured. Hence, it essentially filters out the high frequency noise, typically coupled from other sources other than the supply voltage of interest. The achievable resolution by the VCO A/D converter is determined by the VCO gain in Hz/V and the conversion time. V.1.2 Noise Generator Circuit Figure 16. On-Chip Noise Generator Circuits Noise generator circuits are implemented attached to each supply rail to generate additional supply noise in the system. Figure 16 shows the block diagram of the noise monitors. The noise generator clock signal nclk connects current sources to the supply rail, creating a clock signal shaped current as noise source to the supply rail. The fundamental frequency of this clock shaped noise signal is the frequency of the noise generator clock nclk. The amplitude of the noise waveform is adjusted by a 4-bit control register (ngc[3] ngc[0]). This makes it possible to adjust the noise amplitude to the impedance of the power distribution network at any frequency. For fixed noise current amplitude, the resulting supply voltage noise would be large at frequencies where the supply impedance of the power distribution network is high and small at frequencies where the supply impedance is small. Using the 4-bit control register, the noise current amplitude can be adjusted to achieve a reasonable supply voltage noise at any frequency. V.2 Measurement Setup and Operation Figure 17. Supply noise measurement setup
Figure 17 shows the supply noise measurement setup. Each of the power supplies has two samplers to monitor the voltage on it. Both samplers are attached to individual VCO counters. As shown in Figure 15, the two samplers are enabled by two externally supplied clocks, vclk1 and vclk2, which are at the same frequency but with controllable relative delay between them. By controlling the clock duration and relative phase of the two clocks, the auto-correlation of the two samples can be collected by comparing the values obtained from each of the VCO converters. Typically, supply noise can be characterized as a cyclostationary random process [10]. The auto-correlation can be used to describe many important statistical properties of supply noise: {[ V 1( t0 )] [ VDD2 ( τ )]} A( τ ) = E DD t0 + (10) Subsequently, the power spectral density (PSD) can be obtained. The Nyquist frequency of the measurement is determined by the minimum adjustable delay between the two clocks and not by the repetition rate of the sampling itself. This significantly reduces the usually stringent requirement on the throughput of the high speed sampling circuits. (a) (b) Figure 18. Example of noise sampler data. (a) Sampling mode data, (b) auto-correlation mode data The noise monitor system can be used in different ways to capture different aspects of power supply noise. Using only one monitor as a sampling oscilloscope, one can collect the distribution of the supply noise at each point in time. Deterministic noise waveform can be extracted by taking the mean of all the sampled voltages at each point in time. Meanwhile, the extent of the variation around the deterministic, repetitive noise waveform indicates how much random noise exists on the supply rail. Typically, one would expect the noise on VDD exhibits much larger random variation than that on VDDA. When both noise monitors are used with controlled clocks by varying the relative phase (delay) between them, one can collect the auto-correlation data and therefore derive the cyclo-stationary, or time-averaged power spectrum density (PSD) of the supply
noise. Figure 18 shows the example sampling data from two noise monitors in sampling mode and in auto-correlation mode. V.3 Supply Noise Measurements The noise in both VDD and VDDA supplies are measured in the test system when operating at 6.4Gbps. Figure 19(a) shows that the peak-to-peak VDD supply is 45mVpp, which is in line with the previously simulated results. The VDD spectrum also reveals that the strong frequency components are at the data rate frequency as well as its subharmonics for VDD, as seen in Figure 19(b). Meanwhile, the 100-300MHz range contains significant energy due to the impedance resonance. Figure 20(b) shows that the VDDA peak-to-peak is 18mVpp. Figure 20(b) shows a peaking at around 640MHz, which is the reference clock frequency. (a) (b) Figure 19. Measured VDD noise. (a) Transient waveform, and (b) frequency spectrum (a) (b) Figure 20. Measured VDDA noise. (a) Transient waveform, and (b) frequency spectrum
V.4 Jitter Sensitivity Measurements In order to measure the supply noise induced jitter sensitivity at one frequency, supply noise is generated at this frequency and the resulting jitter at this frequency is measured. Sweeping the noise frequency provides the sensitivity profile over the frequency range of interest. The NMOS devices in the noise generator can be selectively turned on or off to generate noise current modulated by NCLK at desired frequency. The current is pumped into supply rail and consequently it excites additional supply noise on top of any background supply noise. In order to measure the timing clock jitter by observing the waveform at the data transceiver pin(s), it is required that serial link transmits a clock-like data pattern. The transmitted data signal and thus TIE are stored and processed by a real time scope. The jitter component at the frequency of interest is extracted from its spectrum. The amplitude of the supply noise at the frequency of interest is measured using the noise monitor circuits. Dividing the measured jitter by the measured supply noise amplitude provides the jitter sensitivity at the frequency of the supply noise. Figure 21 shows an example of jitter sensitivity extraction. The noise generator generates current modulated by a 50MHz clock and injects it into VDDA supply. As a result, the measured VDDA spectrum shows an outstanding spike at 50MHz. Meanwhile, the measured jitter spectrum also shows a corresponding component spike at the same frequency. Caution needs to be taken to make sure that in each case the spike at the frequency of interest is at least 20dB above the background noise level. In cases that such requirement fails, the data may become less reliable and thus should be disregarded. Figure 21. Example of measuring jitter sensitivity at 50MHz. The above measurement procedure was performed on the high speed I/O interface test system shown in Figure 1 to obtain its jitter sensitivity profiles. The results were then compared with the simulated jitter profiles depicted in Figure 22. The final comparison
between the measured and simulated jitter profile for VDDA in the test system is illustrated in Figure 22. The measurement data points generally agree well with the simulation curve well. There are a few outliers, which however are justifiably removed. The outliers mainly result from the higher than expected background noise level present in the noise monitors. In general, both profiles suggest band-pass behavior for the VDDA supply jitter sensitivity. The most sensitive frequency range centers around 50 to 60MHz. The sensitivity is low at frequency as well as at high frequency. This band-pass behavior is expected since it closely related to the PLL loop bandwidth configuration in the test system. The good correlation further verifies that the simulation methodology can very reasonably predict the system jitter behavior and on the other hand the measurement procedure works well. Figure 22. Jitter sensitivity measurement and simulation correlation VI. Evaluating Supply Noise Induced Jitter Having established the simulation and measurement methodologies for supply noise spectrum and jitter sensitivity profile, now we can come to our ultimate goal to estimate the supply noise induced jitter. Basically, the jitter impact profile J(f) is determined by Equation (2) and is repeated here for convenience: J ( f ) = V ( f ) S( f ) (11) where V(f) is the supply noise frequency spectrum, which is dependent on system operation condition, and S(f) is the jitter sensitivity profile, which is independent on operation condition. It is worth mentioning again that the final jitter performance depends on both the stimulus V(f) and the transfer function S(f). In other words, it is the relative alignment of the spectral contents of noise and jitter sensitivity that matters. The strongest single frequency component in supply noise itself does not necessarily contribute to more jitter than other weaker components if it is not aligned with the jitter profile peak region. On the other hand, the group components in supply noise emphasized by the impedance resonance usually contains more energy. They can potentially contribute significant portion of total jitter albeit the sensitivity profile may or may not necessarily show high sensitivity at this frequency. This also means that the worst scenario would be that both
noise spectrum and jitter sensitivity peak at around the typical impedance profile resonance frequency. (a) (b) Figure 23. Measured VDDA jitter (a) Jitter spectrum J(f) and (b) Accumulated jitter over frequency η(f). Based on the supply noise spectrum shown in Figures 19 and 20 and the jitter sensitivity profile shown in Figure 22, the jitter profile over frequency is obtained using Equation (7). Figure 23(a) shows the measured VDDA jitter spectrum on one serial link in the test system transmitting a 0xAAAA clock-like data pattern on the data rate of 6.4Gbps. It can be seen that multiple spikes are present at data rate frequency 3.2GHz and its sub-harmonics and at the internal timing reference clock 640MHz and its subharmonics. Meanwhile, the ground components below 250MHz represent lots of energy. To gain more insight, the accumulative jitter percentage η(f) is calculated using Equation (5) and plotted in Figure 23(b). It can be clearly seen that about 50% of the total jitter is generated at frequencies below 200MHz and about 95% of the total jitter is present at frequencies below 1GHz. Theses frequencies are way below the data rate frequency and the internal timing reference clock frequency. The overall trend indicated by η(f) confirms the predication of the supply noise spectrum and jitter sensitivity profile. Figure 24. Predicted supply noise induced jitter profile for VDD and VDDA under 0xAAAA data pattern.
The predicted VDDA and VDD jitter spectra are overlaid in Figure 24. In both cases, the jitter profile peaks at medium frequencies, 200MHz for VDDA and 300MHz for VDD. It suggests that the medium frequency noise contributes significantly to the total jitter despite the fact that strongest spikes in current spectrum are at much higher frequencies. Independent of the data rate and even internal timing clock frequency, the medium frequency supply noise is still the biggest concern from the jitter impact point of view. It is also noted from the figure that despite of the common belief in engineering practice that the VDDA supply is most sensitive and deserves meticulous attention, the VDD jitter contribution is actually higher than VDD. This can be understood by using the frequency domain theory discussed in this work. Although indeed the VDD jitter sensitivity profile is lower than the VDDA jitter sensitivity profile, the VDD supply noise itself often contains more energy than VDDA. Moreover, unlike the VDDA noise, the VDD noise strongly depends on the data activity. In the worst case excitation, the VDD noise becomes even worse while the VDDA noise stays pretty much the same. Therefore, design optimization effort should be paid equally to both supplies. VII. Conclusion In this paper, a frequency-domain approach for characterizing supply noise induced jitter was proposed. Using this approach, a detailed analysis of supply noise induced jitter in high-speed I/O systems was performed. The jitter prediction results were shown to correlate well with measurements on a 6.4GHz serial interface. Supply noise induced jitter is the result of combined effects of two independent system characteristics, supply noise and jitter sensitivity. It was shown that the full characterization of the induced jitter can be obtained by using supply noise frequency spectrum V(f) and jitter sensitivity profile over frequency S(f). Both simulation methodologies and measurement techniques were discussed in the paper. The simulation of supply noise requires proper modeling of off-chip and on-chip PDN, on-chip decap extraction and current profile extraction. While the lumped on-chip PDN suffices for prelayout analysis, it is preferred to use distributed on-chip power grid model for postlayout. As for simulating the jitter sensitivity profile, it was shown that the conventional transient analysis gives better accuracy with easier run configuration at the cost of long computation time. A faster approach based on voltage-phase domain variable transformation was also successfully applied with good correlation with transient analysis. On the measurement side, it was shown that supply noise and jitter sensitivity profile can be characterized by using the auto-correlation-based on-chip noise measurement module implemented in the test system. Finally, using the supply noise spectrum and jitter sensitivity profiles confirmed by both simulation and measurement, the noise induced jitter was evaluated. Due to the shape of the power distribution impedance, supply noise close to the frequency of package/chip resonance is emphasized in the system, generating significant noise energy at medium frequency even if the current excitation in this frequency range is very small. As a result, the generation of supply noise energy at these frequencies is largely independent of the data rate of the interface. On the other hand, the noise sensitivity profile of the interface circuits also shows larger sensitivity at medium frequencies. This emphasizes the impact of supply noise at medium frequencies on the
timing of the interface. As a result, the jitter generated by supply noise is dominated by jitter contributions at medium frequencies, way below the data rate or the frequency of internal clock signals. The presented results with good correlation between the simulated prediction and the on-chip measurements validated the frequency domain based approach. This approach can be applied to predict the jitter impact from different supply rails in high speed I/O interface systems as well as other timing budget driven system design. Acknowledgement The authors would like to thank Xiaoning Qi for his significant contribution to the jitter sensitivity measurement and simulation. References [1] K. Chang, et. al., A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell, Proc. IEEE VLSI Circuits Symposium, June 18-20, 2008, pp. 126-127. [2] R. Schmitt, H. Lan, C. Madden, and C. Yuan, Analysis of supply noise induced jitter in Gigabit I/O interfaces, DesignCon, Jan. 29-Feb. 1, 2007, Santa Clara, CA. [3] R. Schmitt, H. Lan, C. Madden, and C. Yuan, Investigating the impact of supply noise on the jitter in gigabit I/O interfaces, Proc. of EPEP, Oct. 28-31, 2007, Atlanta, GA. [4] O. Mandhana, Optimizing the output impedance of a power delivery network for microprocessor systems, Proc. of ECTC, June 2004, Las Vegas, NV. [5] R. Schmitt, C. Yuan, and W. Kim, Modeling and correlation of supply noise for a 3.2 GHz bidirectional differential memory bus, DesignCon, Feb. 2005, Santa Clara, CA. [6] S. R. Nassif and J. N. Kozhaya, Fast power grid simulation, in Proc. IEEE Design Automation Conf., Jun. 2000, pp. 156-161. [7] RedHawk, Apache Design Automation, Milpitas, CA. [8] A. Muhtaroglu, G. Taylor, and T. Rahal-Arabi, On-die droop detector for analog sensing of power supply noise, IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 651-660, April 2004. [9] M. Takamiya, M. Mizuno, and K. Nakamura, An on-chip 100 GHz smapling rate 8- channle sampling oscilloscope with embedded sampling clock generator, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, San Francisco, CA, pp. 820-828. [10] E. Alon, V. Stojanovic, and M. Horowitz, Circuits and Techniques for High- Resolution Measurement of On-Chip Power Supply Noise, IEEE J. Solid-State Circuits, vol. 40, no. 4, April 2005, pp. 820-828. [11] H. Lan, R. Schmitt, and C. Yuan, Simulation and Measurement of On-Chip Supply Noise in Multi-gigabit I/O Intgerfaces, in Proc. IEEE ISQED, March, 2009. [12] Jaeha Kim, Variable Domain Transformation for Linear PAC Analysis of Mixed- Signal Systems, Proc. of ICCAD, Nov. 2007.