MITSBISHI SEMICODCTOR <Intelligent ower ower Module> TYE TYE TEGRTED OWER FCTIOS 4th generation (planar) IGBT inverter bridge for three phase DC-to-C power conversion. TEGRTED DRIE, ROTECTIO D SYSTEM COTROL FCTIOS r upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage () protection. ote : Bootstrap supply scheme can be applied. r lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (), Short-circuit protection (SC). Fault signaling : Corresponding to a SC fault (Low-side IGBT) or a fault (Low-side IGBT). Input interface : 5 line CMOS/TTL compatible, Schmitt Trigger receiver circuit. LICTIO C100~200 three-phase inverter drive for small power motor control. Fig. 1 CKGE OTLES (30.5) (0.75) (1.778) (6.25) (6.25) (6.25) (1.778 26) 28 27 26 25 24 23 22 21 20 19 18 16 1513 12 10 987 654 321 17 14 11 29 30 (1) (8) (8) HET SK SIDE Type name, Lot o. 35 34 33 32 31 (7.62) (7.62 4) (41) (42) (49) (4M) (6.5) (10.5) DMMY (3.556) (1) TERML (17.4) (φ2 DETH 2) (φ3.3) (17.4) (1.5) (5) (35 ) (1.2) (1.25) (2.5) (3.556) (1.656) CB (1.8M) (1) (1.9) TTER SLIT (CB LYOT) Detail *ote2 HET SK SIDE *ote 2: In order to increase the surface distance between terminals, cut a slit, etc. on the CB surface when mounting a module. TERML CODE 1 FS 2 (G) 3 FB 4 1 5 () 6 7 FS 8 (G) 9 FB 10 1 11 () 12 13 WFS 14 (WG) 15 WFB 16 1 17 () 18 W 19 (G) 20 O(C) 21 22 23 W 24 FO 25 26 27 C 28 1 29 (WG) 30 (G) 31 32 33 34 W 35 *ote1:(***) = Dummy in. Dimensions in mm
Fig. 2 TERL FCTIOS BLOCK DIGRM (TYICL LICTIO EXMLE) : Tight tolerance, temp-compensated electrolytic type (ote : The capacitance value depends on the WM control scheme used in the applied system). C4 : 0.22~2µF R-category ceramic capacitor for noise filtering. Inrush current limiter circuit High-side input (WM) (5 line) (ote 1,2) Input signal coditioning Level shifter Level shifter Level shifter rotection circuit () Input signal coditioning rotection circuit () Input signal coditioning rotection circuit () Drive circuit Drive circuit Drive circuit CB CB+ CBW+ CBW CB+ CB C4 (ote 6) C input Z Z : ZR (Surge absorber) C : C filter (Ceramic capacitor 2.2~6.5nF) (ote : dditionally, an appropriate line to line surge absorber circuit may become necessary depending on the application environment.) C C Low-side input (WM) (5 line) (ote 1, 2) (ote 4) Fig. 3 1 Drive circuit Input signal conditioning logic SC protection FO FO output (5 line) (ote 3, 5) Control supply nder-oltage protection H-side IGBTS M W C line output L-side IGBTS ote1: To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 6) (15 line) 2: By virtue of integrating an application specific type HIC inside the module, direct coupling to C terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 6) 3: This output is open collector type. The signal line should be pulled up to the positive side of the 5 power supply with approximately 5.1kΩ resistance. (see also Fig. 6) 4: The wiring between the power DC link capacitor and the /1 terminals should be as short as possible to protect the against catastrophic high surge voltages. r extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these and 1 DC power input terminals. 5: output pulse width should be decided by connecting external capacitor between and C terminals. (Example : =22nF tfo=1.8ms (Typ.)) 6: High voltage (600 or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. C D Fig. 3 EXTERL RT OF THE ROTECTIO CIRCIT Drive circuit Short Circuit rotective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal () is output. Since the SC fault may be repetitive, it is recommended to stop the system when the signal is received and check the fault. IC () H-side IGBTS W SC rotection Trip Level External protection circuit L-side IGBTS 1 Shunt Resistor (ote 1) C C R Drive circuit B rotection circuit C (ote 2) ote1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0. 2: To prevent erroneous protection operation, the wiring of, B, C should be as short as possible. 0 Collector current waveform 2 tw ()
MXIMM RTGS (Tj = 25 C, unless otherwise noted) ERTER RT Symbol Ratings nit CC CC(surge) CES ±IC ±IC C Tj Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature pplied between - pplied between - Tf = 25 C Tf = 25 C, instantaneous value (pulse) Tf = 25 C, per 1 chip (ote 1) 450 500 600 10 20 25 20~+150 ote 1 : The maximum junction temperature rating of the power chips integrated within the is 150 C (@ Tf 100 C). However, to ensure safe operation of the, the average junction temperature should be limited to Tj(ave) 125 C (@ Tf 100 C). W C COTROL (ROTECTIO) RT Symbol Ratings nit D DB FO IFO SC Input voltage Fault output supply voltage Fault output current Current sensing input voltage pplied between 1-C, 1-C pplied between FB-FS, FB-FS, WFB-WFS pplied between,, W-C,,, W-C pplied between FO-C Sink current at FO terminal pplied between -C 20 20 0.5~+5.5 0.5~D+0.5 15 0.5~D+0.5 m TOTL SYSTEM Symbol Ratings nit CC(ROT) Self protection supply voltage limit D = 13.5~16.5, Inverter part Tj = 125 C, non-repetitive, less than 2 (short-circuit protection capability) Tf Heat-fin operation temperature (ote 2) Tstg iso Storage temperature Isolation voltage 60Hz, Sinusoidal, C 1 minute, connection pins to heat-sink plate 400 20~+100 40~+125 2500 C C rms ote 2 : Tf MESREMET OT l Board Specifications: Dimensions 100 100 10mm, finishing: 12s, warp: 50~100µm Control Terminals 18mm 16mm FWD Chip l Board IGBT/FWD Chip Groove IGBT Chip Temp. measurement point (inside the l board) W ower Terminals Temp. measurement point (inside the l board) 100~200µm of evenly applied Silicon-Grease
THERML RESISTCE Symbol Rth(j-f)Q Rth(j-f)F Junction-to-heat sink thermal resistance Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) ote 3 : Grease with good thermal conductivity should be applied evenly about +100µm ~ +200µm on the contact surface of a and a Heat sink. Min. Typ. Max. 5.0 6.5 nit C/W ELECTRICL CHRCTERISTICS (Tj = 25 C, unless otherwise noted) ERTER RT CE(sat) EC ton trr Symbol tc(on) toff tc(off) ICES Collector-emitter saturation voltage FWD forward voltage Switching times Collector-emitter cut-off current D = DB = 15 IC = 10, Tj = 25 C = 0 IC = 10, Tj = 125 C Tj = 25 C, IC = 10, = 5 CC = 300, D = DB =15 IC = 10, Tj = 125 C Inductive load (upper-lower arm) = 5 0 CE = CES Tj = 25 C Tj = 125 C Min. Typ. Max. 0.10 1.80 1.90 2.10 0.60 0.10 0.20 1.10 0.35 2.45 2.60 2.85 1.10 0.60 2.20 1.25 1 10 nit m COTROL (ROTECTIO) RT Symbol D DB ID FOH FOL FOsat tdead SC(ref) DBt DBr Dt Dr tfo th(on) th(off) Circuit current Fault output voltage rm shoot-through blocking time Short-circuit trip level Supply circuit under-voltage protection Fault output pulse width O threshold voltage OFF threshold voltage pplied between 1-C, 1-C pplied between FB-FS, FB-FS, WFB-WFS D = DB =15 Total of 1-C, 1-C = 5 FB-FS, FB-FS, WFB-WFS SC = 0, FO = 10kΩ 5 pull-up SC = 1, FO = 10kΩ 5 pull-up SC = 1, IFO = 15m Relates to corresponding input signal for blocking arm shoot-through. 20 C Tf 100 C Tj = 25 C, D = 15 (ote 4) Trip level Reset level Tj 125 C Trip level Reset level = 22nF (ote 5) pplied between:,, W-C,,, W-C Min. Typ. Max. ote 4 : Short-circuit protection operates only at the low-arms. lease select the value of the external shunt resistor such that the SC trip level is less than 17 5:Fault signal is outputted when the low-arm short-circuit or control supply under-voltage protective functions operate. The fault output pulse-width tfo depends on the capacitance value of according to the following approximate equation. : = (12.2 10-6 ) tfo [F] 13.5 13.5 4.9 0.8 3 0.45 10.0 10.5 10.3 10.8 1.0 0.8 2.5 15.0 15.0 0.8 1.2 0.5 1.8 1.4 3.0 16.5 16.5 8.50 1.00 1.2 1.8 0.55 12.0 12.5 12.5 13.0 2.0 4.0 nit m ms
MECHICL CHRCTERISTICS D RTGS Mounting torque Terminal pulling strength Bending strength Weight Heat-sink flatness Mounting screw : M3 Weight 9.8 Weight 4.9. 90deg bend (ote 6) EIJ-ED-4701 EIJ-ED-4701 Min. 0.59 10 2 50 Typ. 0.78 20 Max. 0.98 100 nit m s times g µm ote 6: Measurement point of heat-sink flatness + Measurement Range 3mm Heat-sink + Heat-sink REMEDED OERTIO CODITIOS Symbol CC D DB D, DB tdead fwm (O) (OFF) Supply voltage Control supply variation rm shoot-through blocking time WM input frequency Input O voltage Input OFF voltage pplied between - pplied between 1-C, 1-C pplied between FB-FS, FB-FS, WFB-WFS Relates to corresponding input signal for blocking arm shoot-through Tj 125 C, Tf 100 C pplied between,, W-C,,, W-C Min. Typ. Max. 0 13.5 13.5 1 3 300 15.0 15.0 15 0~0.65 4.0~5.5 400 16.5 16.5 1 nit / khz
Fig. 4 THE TERL CIRCIT FB FS 1 HIC 1 CC B IGBT1 Di1 S FB FS 1 HIC 2 CC B IGBT2 Di2 S WFB WFS 1 HIC 3 CC B IGBT3 Di3 W S W LIC IGBT4 Di4 OT 1 CC IGBT5 Di5 OT IGBT6 Di6 WOT W W C GD O O(C) ote: The IGBTs gates and the HICs terminals are connected to the dummy pins.
Fig. 5 TIMG CHRTS OF THE ROTECTIE FCTIOS [] Short-Circuit rotection (-side only) (r the external shunt resistor and CR connection, please refer to Fig. 3.) a1. ormal operation : IGBT O and carrying current. a2. Short-circuit current detection (SC trigger). a3. IGBT gate interrupt. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor. a6. Input H : IGBT OFF state. a7. Input L : IGBT O state. a8. IGBT OFF state. -side control input a6 a7 rotection circuit state SET RESET Internal IGBT gate a3 a2 Output current Ic() a1 SC a4 a8 Sense voltage of the shunt resistor SC reference voltage CR circuit time constant DELY Fault output a5 [B] nder-oltage rotection (-side, D) a1. ormal operation : IGBT O and carrying current. a2. nder-voltage trip (Dt). a3. IGBT OFF in spite of control input condition. a4. FO timer operation starts. a5. nder-voltage reset (Dr). a6. ormal operation : IGBT O and carrying current. Control input rotection circuit state SET RESET D Dr Dt a2 a5 a1 a3 a6 Output current Ic() Fault output a4
[C] nder-oltage rotection (-side, DB) a1. rises : fter the voltage level reachs DBr, the circuits start to operate when the next input is applied. a2. ormal operation : IGBT O and carrying current. a3. nder-voltage trip (DBt). a4. IGBT OFF in spite of control input condition (there is no FO signal output). a5. nder-voltage reset (DBr). a6. ormal operation : IGBT O and carrying current. Control input rotection circuit state RESET SET RESET DBr DB a1 DBt a3 a5 a2 a4 a6 Output current Ic() Fault output High-level (no fault output) Fig. 6 REMEDED C I/O TERFCE CIRCIT 5 line 5.1kΩ 4.7kΩ,,W,,,W C 1nF 1nF C (GD) ote : RC coupling at each input (parts shown dotted) may change depending on the WM control scheme used in the application and on the wiring impedance of the application s printed circuit board.
Fig. 7 TYICL LICTIO CIRCIT EXMLE C1: Tight tolerance temp-compensated electrolytic type; C2,: 0.22~2 µ F R-category ceramic capacitor for noise filtering 5 line C2 C1 FB FS 1 CC B C2 S FB C1 FS C C2 C1 1 WFB WFS 1 W CC CC B S B M IT S W OT 1 CC 5 line OT 15 line W C W GD WOT O If this wiring is too long, short circuit might be caused. C C4() C5 B R1 Shunt resistor The long wiring of GD might generate noise on input signals and cause IGBT to be malfunctioned. If this wiring is too long, the SC level fluctuation might be large and cause SC malfunction. 1 ote 1 : To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short as possible (less than 2cm). 2:By virtue of integrating an application specific type HIC inside the module, direct coupling to C terminals without any opto-coupler or transformer isolation is possible. 3:FO output is open collector type. This signal line should be pulled up to the positive side of the 5 power supply with approximately 5.1kΩ resistance. 4:FO output pulse width should be decided by connecting an external capacitor between and C terminals (). (Example : = 22 nf tfo = 1.8 ms (typ.)) 5:Each input signal line should be pulled up to the positive side of the 5 power supply with approximately 4.7kΩ resistance (other RC coupling circuits at each input may be needed depending on the WM control scheme used and on the wiring impedances of the system s printed circuit board). pproximately a 0.22~2µF by-pass capacitor should be used across each power supply connection terminals. 6:To prevent errors of the protection function, the wiring of, B, C should be as short as possible. 7:In the recommended protection circuit, please select the R1C5 time constant in the range of 1.5~2. 8:Each capacitor should be put as nearby the terminals of the as possible. 9:To prevent surge destruction, the wiring between the smoothing capacitor and the &1 terminals should be as short as possible. pproximately a 0.1~0.22µF snubber capacitor between the &1 terminals is recommended.