ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline! Pass Transistor Logic! Performance Lec 15: March 1, 2018 Combination Logic: Pass Transistor Logic, and Performance 2 Pass Transistor Logic Teaser! What does this do? 4 Identify Function! What function is this?! What is Vout if A=1, B=1? 0 1 1 1 5 6 1
! What is Vout if A=1, B=1?! What is Vout if A=0, B=1? 0 1 1 0 1 1 7 8! What is Vout if A=0, B=1?! What is Vout if A=0, B=0? if A=1, B=0? 0 1 1 1 0 1 1 1 9 10 Area! What is Vout if A=0, B=0? if A=1, B=0?! Compare PT with CMOS circuit? 0 0 1 1 1 1 11 12 2
! Is this a regenerating/restoring gate? 0 0 1 1 1 1! What does output look like (DC transfer)? " (B=1, notb=0, sweep A, nota=cmos inv(a)) 13 14 Pass TR transfer (B=1) CMOS Inverter Transfer Sweep A 15 16 Reasonable Input to CMOS Inverter? Pass Transistor xor2 with inv restore 17 18 3
Compare CMOS Required to use?! Is this a fair comparison?! What should we add to make substitutable with CMOS? 19 20 Restore Restore! Area? (compare to CMOS) 21 22 Chain Together Focus on Pass Transistor! Vgs?! Operation mode?! Current flow direction? V dd =1V V thn =-V thp =0.3V 23 24 4
At t=0 (after Vin transition 1#0) At t=4τ (after Vin transition 1#0)! What is Vmid? Vout? " Vgs of A? Vgs of B? V dd =1V V thn =-V thp =0.3V! What is mode of operation of A and B? V dd =1V V thn =-V thp =0.3V 25 26 At t= (after Vin transition 1#0) Voltage of Chain! What is Va? Vmid? Vout? V dd =1V V thn =-V thp =0.3V! What is voltage at output? V dd =1V V thn =-V thp =0.3V 27 28 How compare DC Analysis chain of 3! Compare 29 30 5
DC Analysis chain of 6 Conclude! Can chain any number of pass transistors and only drop a single V th 31 32 Transient Transient: Zoomed Closeup 33 34 Gate Cascade? Chain Together! What are voltages? 35 36 6
Cascaded Pass Gates Delay A=1, B=0, C DB =C diff =C d? Penn ESE 570 Spring 2017 Khanna 37 38 Delay A=1, B=0, C DB =C diff =C d? Delay A=1, B=0, C DB =C diff =C d?! What s the equivalent RC circuit?! What s the equivalent RC circuit? 39 40 Delay A=1, B=0, C DB =C diff =C d? Delay A=1, B=0, C DB =C diff =C d?! What s the equivalent RC circuit?! What s the equivalent RC circuit? " What is the total delay? " From A to Y 3C d 2C d + 3C d 2C d + 41 42 7
Delay A=1, B=1, C DB =C diff =C d? Delay A=1, B=1, C DB =C diff =C d?! What s the equivalent RC circuit? 43 44 Bonus! What does this do? B 0 1 1 1 Transmission Gates A 45 CMOS Transmission Gates CMOS Transmission Gates Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD 47 48 8
CMOS Transmission Gates CMOS Transmission Gates Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD - V Tp 49 - V Tp 50 CMOS Transmission Gates CMOS Transmission Gates Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD - V Tp 51 - V Tp 52 Transmission Gate, R eq Transmission Gate, R eq k p (- V DD - V Tp ) 2 k p [2(- V DD - V tp ) (V out V DD ) - (V out V DD ) 2 ] k p [2(- V DD - V tp ) - (V out V DD )] k p [2(- V DD - V tp ) - (V out V DD )] 53 54 9
Transmission Gate, R eq Transmission Gate Layouts 55 56 Logic Types Idea! CMOS Gates " Dual pull-down and pull-up networks, only one enabled at a time " Performance of gate is strong function of the fanin of gate " Techniques to improve performance include sizing, input reordering, and buffering (staging)! Ratioed Gates " Have active pull-down (-up) network connected to load device " Reduced gate complexity at expense of static power asymmetric transfer function " Techniques to improve performance include sizing to improve noise margins and reduce static power! Pass Gates " Implement logic gate as switch network for reduced area and load capacitance " Long cascades of switches result in quadratic increase in delay " Also suffer from reduced noise margins (V T drop) " Use level-restoring buffers to improve noise margins! CMOS " Design for worst case input switching case and delay! There are other logic disciplines " Ratioed logic " Can use pass transistors for logic " Transmission gates " Will see in use in dynamic logic! Dynamic logic coming up soon 57 58 Midterm Exam Midterm Topics List! Midterm 3/14 " During class; starts at exactly 1:30pm, ends at exactly 2:50pm (80 minutes) " Location: LRSM Auditorium " Old exams posted on old course websites " Covers Lec 1-13 " Closed book, no notes or cheat sheets " Calculators allowed and recommended, no smart phones " Review Session by TA TBD " Watch piazza for time and location " Office Hours " cancelled during spring break, use Piazza for questions " Tania: Monday (3/12) 2-4:30pm! Identify CMOS/non- CMOS! Any logic function $# CMOS gate! Noise Margins! Circuit first order switching rise/fall times " equivalent resistance " Load capacitance! Transistor " Regions of operation " Parasitic Capacitance Model! Layout and stick diagrams! Sizing! 1 st order delay " Worst case " Elmore delay! Ratioed logic 59 60 10