NTHDN Power MOSFET V,.9 A, Dual N Channel ChipFET Features Planar Technology Device Offers Low R DS(on) and Fast Switching Speed Leadless ChipFET Package has % Smaller Footprint than TSOP. Ideal Device for Applications Where Board Space is at a Premium. ChipFET Package Exhibits Excellent Thermal Capabilities. Ideal for Applications Where Heat Transfer is Required. These Devices are Pb Free and are RoHS Compliant Applications DC DC Buck or Boost Converters Low Side Switching Optimized for Battery and Low Side Switching Applications in Computing and Portable Equipment V (BR)DSS V D (7, ) G R DS(on) TYP m @ V m @. V D (, ) G I D MAX.9 A MAXIMUM RATINGS (T J = C unless otherwise noted) Parameter Symbol Value Unit Drain to Source Voltage V DSS V Gate to Source Voltage V GS ± V Continuous Drain Steady T A = C I D.9 A Current (Note ) State T A = C. Power Dissipation (Note ) Continuous Drain Current (Note ) Power Dissipation (Note ) t s T A = C.9 Steady P D. W State T A = C t s. T A = C I D. A Steady State T A = C. T A = C P D. W Pulsed Drain Current t p = s I DM A ESD Capability (Note ) C = pf, R S = ESD HBM Operating Junction and Storage Temperature T J, T STG V to Source Current (Body Diode) I S. A Lead Temperature for Soldering Purposes (/ from case for s) C T L C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Surface Mounted on FR Board using in sq pad size (Cu area =.7 in sq [ oz] including traces).. Surface Mounted on FR Board using the minimum recommended pad size (Cu area =. in sq).. ESD Rating Information: HBM Class. () PIN CONNECTIONS D D D D 7 S G S G ChipFET CASE A STYLE MARKING DIAGRAM ORDERING INFORMATION Device Package Shipping NTHDNTG S () N Channel MOSFET () ChipFET (Pb Free) C M C = Specific Device Code M = Month Code = Pb Free Package S () 7 /Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD/D. Semiconductor Components Industries, LLC, June, Rev. Publication Order Number: NTHDN/D
NTHDN THERMAL RESISTANCE RATINGS Parameter Symbol Max Unit Junction to Ambient Steady State (Note ) R JA C/W Junction to Ambient t s (Note ) R JA Junction to Ambient Steady State (Note ) R JA 9 Junction to Foot Steady State (Note ) R JF. Surface Mounted on FR Board using in sq pad size (Cu area =.7 in sq [ oz] including traces).. Surface Mounted on FR Board using the minimum recommended pad size (Cu area =. in sq). Input Capacitance C ISS ELECTRICAL CHARACTERISTICS (T J = C unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Units OFF CHARACTERISTICS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = A V Zero Gate Voltage Drain Current I DSS V GS = V, V DS = V. A V GS = V, V DS = V, T J = C Gate to Source Leakage Current I GSS V DS = V, V GS = V na ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = A... V Drain to Source On Resistance R DS(on) V GS = V, I D =.9 A 7 m V GS =. V, I D =. A Forward Transconductance g FS V DS = V, I D =.9 A. S CHARGES AND CAPACITANCES Input Capacitance C ISS pf Output Capacitance C V GS = V, f =. MHz, OSS V DS = V Reverse Transfer Capacitance C RSS pf Output Capacitance C V GS = V, f =. MHz, OSS V DS = V 7 Reverse Transfer Capacitance C RSS Total Gate Charge Q G(TOT). 7. nc Threshold Gate Charge Q G(TH) V GS = V, V DS = V,. Gate to Source Charge Q GS I D =.9 A. Gate to Drain Charge Q GD.7 Total Gate Charge Q G(TOT).9 nc Threshold Gate Charge Q G(TH) V GS =. V, V DS = V,. Gate to Source Charge Q GS I D =.9 A. Gate to Drain Charge Q GD.9. Pulse Test: Pulse Width s, Duty Cycle %.
NTHDN ELECTRICAL CHARACTERISTICS (continued) (T J = C unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Units DRAIN SOURCE DIODE CHARACTERISTICS Forward Diode Voltage V SD V GS = V, I S =. A.. V Reverse Recovery Time t RR VGS = V, I S =.9 A,. ns Reverse Recovery Charge Q RR di S /dt = A/ s. nc Reverse Recovery Time t RR VGS = V, I S =. A,. ns Reverse Recovery Charge Q RR di S /dt = A/ s. nc SWITCHING CHARACTERISTICS (Note 7) Turn On Delay Time t d(on). ns Rise Time t r V GS = V, V DD = V,. Turn Off Delay Time t d(off) I D = A, R G =.9 Fall Time t f.. Turn On Delay Time t d(on) 7. ns Rise Time t r V GS =. V, V DD = V,. Turn Off Delay Time t d(off) I D =.9 A, R G =. 9. Fall Time t f. 7. Switching characteristics are independent of operating junction temperatures.
NTHDN TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (AMPS) V GS =,,,. &. V resp. T J = C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) V. V. V. V. V V. V. V I D, DRAIN CURRENT (AMPS) V DS V C C T J = C V GS, GATE TO SOURCE VOLTAGE (VOLTS) Figure. On Region Characteristics Figure. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( )...... I D =.9 A T J = C 7 9 V GS, GATE TO SOURCE VOLTAGE (VOLTS) R DS(on), DRAIN TO SOURCE RESISTANCE ( ). T J = C. V GS =. V..9 V GS = V..7 I D, DRAIN CURRENT (AMPS) Figure. On Resistance vs. Gate to Source Voltage Figure. On Resistance vs. Drain Current and Gate Voltage R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED)...... I D =.9 A V GS = V I DSS, LEAKAGE (na) V GS = V T J = C T J = C. 7. T J, JUNCTION TEMPERATURE ( C) V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure. On Resistance Variation with Temperature Figure. Drain to Source Leakage Current vs. Voltage
NTHDN TYPICAL PERFORMANCE CURVES C, CAPACITANCE (pf) V DS = V C ISS C RSS V GS = V T J = C C OSS V GS, GATE TO SOURCE VOLTAGE (VOLTS) V GS V DS Q G, TOTAL GATE CHARGE (nc) GATE TO SOURCE OR DRAIN TO SOURCE VOLTAGE (VOLTS) Figure. Gate to Source and Figure 7. Capacitance Variation Drain to Source Voltage vs. Total Charge V DS Q GS Q GD Q G V GS I D =.9 A T J = C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) t, TIME (ns). t d(off) t d(on) t r t f R G, GATE RESISTANCE (OHMS) V DD = V I D =. A V GS = V I S, SOURCE CURRENT (AMPS). V GS = V T J = C....7..9 V SD, SOURCE TO DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure. Diode Forward Voltage vs. Current
NTHDN PACKAGE DIMENSIONS ChipFET CASE A ISSUE K H E e D 7 e b E A L c. (.) 7 STYLE : PIN. SOURCE. GATE. SOURCE. GATE. DRAIN. DRAIN 7. DRAIN. DRAIN NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 9.. CONTROLLING DIMENSION: MILLIMETER.. MOLD GATE BURRS SHALL NOT EXCEED. MM PER SIDE.. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED. MM.. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A....9.. b...... c...... D.9..... E...7...7 e. BSC. BSC e. BSC. BSC L......7 HE..9..7.7.79 NOM NOM SOLDERING FOOTPRINT....9.. PITCH X.7. X.. mm inches ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado 7 USA Phone: 7 7 or Toll Free USA/Canada Fax: 7 7 or 7 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 79 9 Japan Customer Focus Center Phone: 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTHDN/D