Power MOSFET PRODUCT SUMMARY (V) 600 R DS(on) () = 10 V 1. Q g max. (nc) 39 Q gs (nc) 10 Q gd (nc) 19 Configuration Single D TO0AB G S G DS NChannel MOSFET ORDERING INFORMATION Package Lead (Pb)free SnPb FEATURES Ultra low gate charge Reduced gate drive requirement Available Enhanced 30 V, rating Reduced C iss, C oss, C rss Available Extremely high frequency operation Repetitive avalanche rated Material categorization: for definitions of compliance please see www.vishay.com/doc?9991 Note * This datasheet provides information about parts that are RoHScompliant and / or parts that are nonrohscompliant. For example, parts with lead (Pb) terminations are not RoHScompliant. Please see the information / tables in this datasheet for details. DESCRIPTION This new series of low charge power MOSFETs achieve significantly lower gate charge over conventional Power MOSFETs. Utilizing the new LCDMOS technology, the device improvements are achieved without added product cost, allowing for reduced gate drive requirements and total system savings. In addition reduced switching losses and improved efficiency are achievable in a variety of high frequency applications. Frequencies of a few MHz at high current are possible using the new low charge power MOSFETs. These device improvements combined with the proven ruggedness and reliability that are characteristic of power MOSFETs offer the designer a new standard in power transistors for switching applications. TO0AB IRFBC40LCPbF SiHFBC40LCE3 IRFBC40LC SiHFBC40LC ABSOLUTE MAXIMUM RATINGS (T C = C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 600 V GateSource Voltage ± 30 Continuous Drain Current at 10 V T C = C 6. I D T C = 100 C 3.9 A Pulsed Drain Current a I DM Linear Derating Factor 1.0 W/ C Single Pulse Avalanche Energy b E AS 30 mj Repetitive Avalanche Current a I AR 6. A Repetitive Avalanche Energy a E AR 13 mj Maximum Power Dissipation T C = C P D 1 W Peak Diode Recovery dv/dt c dv/dt 3.0 V/ns Operating Junction and Storage Temperature Range T J, T stg to 10 Soldering Recommendations (Peak temperature) d for 10 s 300 C Mounting Torque 63 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. V DD = 0 V, starting T J = C, L = mh, R g =, I AS = 6. A (see fig. 1). c. I SD 6. A, di/dt 80 A/μs, V DD, T J 10 C. d. 1.6 mm from case. 10 lbf in 1.1 N m S160763Rev. D, 0May16 1 Document Number: 91114
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient R thja 6 CasetoSink, Flat, Greased Surface R thcs 0.0 C/W Maximum JunctiontoCase (Drain) R thjc 1.0 SPECIFICATIONS (T J = C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage = 0 V, I D = 0 μa 600 V Temperature Coefficient /T J Reference to C, I D = 1 ma 0.70 V/ C GateSource Threshold Voltage (th) =, I D = 0 μa.0 4.0 V GateSource Leakage I GSS = 0 ± 100 na = 600 V, = 0 V 100 Zero Gate Voltage Drain Current I DSS = 480 V, = 0 V, T J = 1 C 00 μa DrainSource OnState Resistance R DS(on) = 10 V I D = 3.7 A b 1. Forward Transconductance g fs = 100 V, I D = 3.7 A b 3.7 S Dynamic Input Capacitance C iss VGS = 0 V 1100 Output Capacitance C oss = V 140 pf Reverse Transfer Capacitance C rss f = 1.0 MHz, see fig. 1 Total Gate Charge Q g 39 GateSource Charge Q gs I = 10 V D = 6. A, = 360 V, see fig. 6 and 13 b 10 nc GateDrain Charge Q gd 19 TurnOn Delay Time t d(on) 1 Rise Time t r V DD = 300 V, I D = 6. A 0 TurnOff Delay Time t d(off) R g = 9.1, R D = 47, see fig. 10 b 7 ns Fall Time t f 17 Between lead, Internal Drain Inductance L D 6 mm (0.") from 4. D package and center of nh G Internal Source Inductance L S die contact 7. Gate Input Resistance R g f = 1 MHz, open drain 0.6 3.9 DrainSource Body Diode Characteristics MOSFET symbol Continuous SourceDrain Diode Current I S showing the 6. D integral reverse G Pulsed Diode Forward Current a I SM p n junction diode Body Diode Voltage V SD T J = C, I S = 6. A, = 0 V b 1. V Body Diode Reverse Recovery Time t rr 440 680 ns Body Diode Reverse Recovery Charge Q rr T J = C, I F = 6. A, di/dt = 100 A/μs b.1 3. μc Forward TurnOn Time t on Intrinsic turnon time is negligible (turnon is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle %. S S A S160763Rev. D, 0May16 Document Number: 91114
TYPICAL CHARACTERISTICS ( C, unless otherwise noted) 91114_01 10 1 10 0 10 1 Top Bottom 1 V 10 V 8.0 V 7.0 V 6.0 V. V.0 V 4. V 4. V 0 µs Pulse Width T C = C 10 10 10 1 10 0 10 1 10, DraintoSource Voltage (V) Fig. 1 Typical Output Characteristics, T C = C R DS(on), DraintoSource On Resistance (Normalized) 91114_04 3. 3.0..0 1. 1.0 0. I D = 6. A = 10 V 0.0 60 40 0 0 0 40 60 80 100 10 140 160 T J, Junction Temperature ( C) Fig. 4 Normalized OnResistance vs. Temperature 10 1 10 0 10 1 Top Bottom 1 V 10 V 8.0 V 7.0 V 6.0 V. V.0 V 4. V 4. V Capacitance (pf) 400 000 1600 100 800 = 0 V, f = 1 MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd C iss C oss 91114_0 0 µs Pulse Width T C = 10 C 10 10 10 1 10 0 10 1 10, DraintoSource Voltage (V) Fig. Typical Output Characteristics, T C = 10 C 91114_0 C rss 400 0 10 0 10 1, DraintoSource Voltage (V) Fig. Typical Capacitance vs. DraintoSource Voltage 0 I D =. A 91114_03 10 1 10 0 10 1 4 10 C C 0 µs Pulse Width = 100 V 6 7 8 9 10, GatetoSource Voltage (V), GatetoSource Voltage (V) 91114_06 16 1 8 4 = 180 V = 40 V = 300 V For test circuit see figure 13 0 0 8 16 4 3 40 Q G, Total Gate Charge (nc) Fig. 3 Typical Transfer Characteristics Fig. 6 Typical Gate Charge vs. GatetoSource Voltage S160763Rev. D, 0May16 3 Document Number: 91114
7.0 I SD, Reverse Drain Current (A) 91114_07 10 1 10 C C = 0 V 10 0 0.6 0.8 1.0 1. 1.4 V SD, SourcetoDrain Voltage (V) Fig. 7 Typical SourceDrain Diode Forward Voltage 91114_09 6.0.0 4.0 3.0.0 1.0 0.0 0 7 100 1 10 T C, Case Temperature ( C) Fig. 9 Maximum Drain Current vs. Case Temperature 91114_08 10 3 10 10 1 0.1 10 0.1 Operation in this area limited by R DS(on) T C = C T J = 10 C Single Pulse 10 µs 100 µs 1 ms 10 ms 1 10 10 10 3 10 4, DraintoSource Voltage (V) Fig. 8 Maximum Safe Operating Area Fig. 10a Switching Time Test Circuit 90 % R g 10 V Pulse width 1 μs Duty factor 0.1 % R D D.U.T. 10 % t d(on) t r t d(off) t f V DD Fig. 10b Switching Time Waveforms 10 Thermal Response (Z thjc ) 1 0.1 0 0. 0. 0.1 0.0 0.0 0.01 Single Pulse (Thermal Response) 10 10 10 4 10 3 10 0.1 1 10 P DM t 1 t Notes: 1. Duty Factor, D = t 1 /t. Peak T j = P DM x Z thjc T C 91114_11 t 1, Rectangular Pulse Duration (s) Fig. 11 Maximum Effective Transient Thermal Impedance, JunctiontoCase S160763Rev. D, 0May16 4 Document Number: 91114
L Vary t p to obtain required I AS t p R G I AS D.U.T. V DD V DD 10 V t p 0.01 Ω I AS Fig. 1a Unclamped Inductive Test Circuit Fig. 1b Unclamped Inductive Waveforms E AS, Single Pulse Energy (mj) 91114_1c 100 1000 800 600 400 00 Top Bottom V DD = 0 V 0 0 7 100 1 10 Starting T J, Junction Temperature ( C) I D.8 A 3.9 A. A Fig. 1c Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. Q g 0 kω 1 V 0. μf 0.3 μf Q gs Q gd D.U.T. V DS V G Charge 3 ma I G I D Current sampling resistors Fig. 13a Basic Gate Charge Waveform Fig. 13b Gate Charge Test Circuit S160763Rev. D, 0May16 Document Number: 91114
Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period = 10 V a D.U.T. I SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple % I SD Note a. = V for logic level devices Fig. 14 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91114. S160763Rev. D, 0May16 6 Document Number: 91114
Package Information TO01 D L H(1) Q L(1) 1 E 3 M * b(1) Ø P A F DIM. MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 4.4 4.6 0.167 0.183 b 0.69 1.0 0.07 0.040 b(1) 1.14 1.78 0.04 0.070 c 0.36 0.61 0.014 0.04 D 14.33 1.8 0.64 0.64 E 9.96 10. 0.39 0.414 e.41.67 0.09 0.10 e(1) 4.88.8 0.19 0.08 F 1.14 1.40 0.04 0.0 H(1) 6.10 6.71 0.40 0.64 J(1).41.9 0.09 0.11 L 13.36 14.40 0.6 0.67 L(1) 3.33 4.04 0.131 0.19 Ø P 3.3 3.94 0.139 0.1 Q.4 3.00 0.100 0.118 ECN: X10364Rev. C, 14Dec1 DWG: 6031 Note M* = 0.0 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM e b C e(1) J(1) ASE Package Picture Xi an Revison: 14Dec1 1 Document Number: 664
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