Power MOSFET PRODUCT SUMMARY (V) 300 R DS(on) (Ω) = 0 V 0.75 Q g (Max.) (nc) 7 Q gs (nc) 4.8 Q gd (nc) 7.6 Configuration Single TO220 G DS ORDERING INFORMATION Package Lead (Pb)free SnPb G D S NChannel MOSFET FEATURES Reduced Gate Drive Requirement Enhanced 30 V Rating Reduced C iss, C oss, C rss Extremely High Frequency Operation Repetitive Avalanche Rated Lead (Pb)free Available Available RoHS* COMPLIANT DESCRIPTION This new series of low charge Power MOSFETs achieve significantly lower gate charge over conventional Power MOSFETs. Utilizing the new LCDMOS technology, the device improvements are achieved without added product cost, allowing for reduced gate drive requirements and total system savings. In addition, reduced switching losses and improved efficiency are achievable in a variety of high frequency applications. Frequencies of a few MHz at high current are possible using the new low charge Power MOSFETs. These device improvements combined with the proven ruggedness and reliability that are characteristics of Power MOSFETs offer the designer a new standard in power transistors for switching applications. TO220 IRF737LCPbF SiHF737LCE3 IRF737LC SiHF737LC ABSOLUTE MAXIMUM RATINGS T C = 25 C, unless otherwise noted PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 300 GateSource Voltage ± 30 V Continuous Drain Current at 0 V T C = 25 C 6. T C = 00 C 3.9 A Pulsed Drain Current a M 24 Linear Derating Factor 0.59 W/ C Single Pulse Avalanche Energy b E AS 20 mj Avalanche Current a I AR 6. A Repetiitive Avalanche Energy a E AR 7.4 mj Maximum Power Dissipation T C = 25 C P D 74 W Peak Diode Recovery dv/dt c dv/dt 3.4 V/ns Operating Junction and Storage Temperature Range T J, T stg 55 to 50 Soldering Recommendations (Peak Temperature) for 0 s 300 d C Mounting Torque 632 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. V DD = 25 V, starting T J = 25 C, L = 5.7 mh, R G = 25 Ω, I AS = 6. A (see fig. 2). c. I SD 6. A, di/dt 270 A/µs, V DD, T J 50 C. d..6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply 0 lbf in. N m Document Number: 9050 S82998Rev. A, 2Jan09
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient R thja 62 CasetoSink, Flat, Greased Surface R thcs 0.50 C/W Maximum JunctiontoCase (Drain) R thjc.7 Note a. When mounted on " square PCB (FR4 or G0 material). SPECIFICATIONS T J = 25 C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage = 0 V, = 250 µa 300 V Temperature Coefficient Δ /T J Reference to 25 C, = ma 0.39 V/ C GateSource Threshold Voltage (th) =, = 250 µa 2.0 4.0 V GateSource Leakage I GSS = ± 20 V ± 00 na = 300 V, = 0 V 25 Zero Gate Voltage Drain Current SS = 240 V, = 0 V, T J = 50 C 250 µa DrainSource OnState Resistance R DS(on) = 0 V = 3.7 A b 0.75 Ω Forward Transconductance g fs = 50 V, = 3.7 A b 2.7 S Dynamic Input Capacitance C iss = 0 V, 430 Output Capacitance C oss = 25 V, 20 pf Reverse Transfer Capacitance C rss f =.0 MHz, see fig. 5 9.2 Total Gate Charge Q g 7 GateSource Charge Q gs I = 0 V D = 6. A, = 240 V, see fig. 6 and 3 b 4.8 nc GateDrain Charge Q gd 7.6 TurnOn Delay Time t d(on) 6.6 Rise Time t r V DD = 50 V, = 6. A, 2 TurnOff Delay Time t d(off) R G = 2 Ω, R D = 24 Ω, see fig. 0 b 3 ns Fall Time t f 2 D Between lead, Internal Drain Inductance L D 4.5 6 mm (0.25") from G package and center of Internal Source Inductance L S die contact 7.5 nh DrainSource Body Diode Characteristics MOSFET symbol Continuous SourceDrain Diode Current I S D 6. showing the integral reverse Pulsed Diode Forward Current a G I SM 24 p n junction diode S A Body Diode Voltage V SD T J = 25 C, I S = 6. A, = 0 V b.6 V Body Diode Reverse t rr 320 490 ns Recovery Time T J = 25 C, I F = 6. A, di/dt = 00 A/µs b Body Diode Reverse Recovery Charge Q rr.5 2.2 µc Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Pulse width 300 µs; duty cycle 2 %. S Document Number: 9050 2 S82998Rev. A, 2Jan09
TYPICAL CHARACTERISTICS 25 C, unless otherwise noted, DraintoSource Current (A) 9050_0 Top 5 V 0 V 8.0 V 0 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 0 2 4.5 V 20 µs Pulse Width T C = 25 C 0, DraintoSource Voltage (V), DraintoSource Current (A) 9050_03 0 0 2 4 T J = 50 C T J = 25 C 20 µs Pulse Width = 50 V 5 6 7 8 9 0, GatetoSource Voltage (V) Fig. Typical Output Characteristics, T C = 25 C Fig. 3 Typical Transfer Characteristics, DraintoSource Current (A) 9050_02 0 0 2 Top Bottom 5 V 0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V 4.5 V 20 µs Pulse Width T C = 50 C 0, DraintoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) 9050_04 3.0 2.5 2.0.5.0 0.5 = 6. A = 0 V 0.0 60 40 20 0 20 40 60 80 00 20 40 60 T J, Junction Temperature ( C) Fig. 2 Typical Output Characteristics, T C = 50 C Fig. 4 Normalized OnResistance vs. Temperature Document Number: 9050 S82998Rev. A, 2Jan09 3
C, Capacitance (pf) 9050_05 800 700 600 500 400 300 200 00 0 0 = 0 V, f = MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd C iss C oss C rss, DraintoSource Voltage (V) Fig. 5 Typical Capacitance vs. DraintoSource Voltage I SD, Reverse Drain Current (A) 9050_07 0 T J = 50 C T J = 25 C = 0 V 0.2 0.4 0.6 0.8.0.2.4 V SD, SourcetoDrain Voltage (V) Fig. 7 Typical SourceDrain Diode Forward Voltage, GatetoSource Voltage (V) 9050_06 20 6 2 8 4 0 = 6. A = 60 V = 50 V = 240 V 0 4 8 2 6 Q G, Total Gate Charge (nc) For test circuit see figure 3, Drain Current (A) 9050_08 0 Operation in this area limited by R DS(on), DraintoSource Voltage (V) 0 µs 00 µs ms 0 ms T C = 25 C T J = 50 C Single Pulse 0 0 3 Fig. 6 Typical Gate Charge vs. GatetoSource Voltage Fig. 8 Maximum Safe Operating Area Document Number: 9050 4 S82998Rev. A, 2Jan09
R D, Drain Current (A) 7.0 6.0 5.0 4.0 3.0 2.0.0 Fig. 0a Switching Time Test Circuit 90 % R G 0 V Pulse width µs Duty factor % D.U.T. V DD 9050_09 0.0 25 50 75 00 25 50 T C, Case Temperature ( C) 0 % t d(on) t r t d(off) t f Fig. 9 Maximum Drain Current vs. Case Temperature Fig. 0b Switching Time Waveforms 0 Thermal Response (Z thjc ) D = 0.50 0.20 0 0.05 0.02 0.0 Single Pulse (Thermal Response) 0 2 0 5 0 4 0 3 0 2 P DM t t 2 Notes:. Duty Factor, D = t /t 2 2. Peak T j = P DM x Z thjc T C 9050_ t, Rectangular Pulse Duration (s) Fig. Maximum Effective Transient Thermal Impedance, JunctiontoCase L Vary t p to obtain required I AS R G D.U.T. I AS V DD t p V DD 0 V t p 0.0 Ω I AS Fig. 2a Unclamped Inductive Test Circuit Fig. 2b Unclamped Inductive Waveforms Document Number: 9050 S82998Rev. A, 2Jan09 5
E AS, Single Pulse Avalanche Energy (mj) 9050_2c 240 200 60 20 80 40 Top Bottom V DD = 50 V 0 25 50 75 00 25 50 Starting T J, Junction Temperature ( C) 2.7 A 3.9 A 6. A Fig. 2c Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 0 V Q G 2 V 0.2 µf 50 kω 0.3 µf Q GS Q GD D.U.T. V DS V G Charge Fig. 3a Basic Gate Charge Waveform 3 ma Fig. 3b Gate Charge Test Circuit I G Current sampling resistors Document Number: 9050 6 S82998Rev. A, 2Jan09
Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by duty factor "D" D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period = 0 V* D.U.T. I SD waveform Reverse recovery current Reapplied voltage Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt Inductor current Body diode forward drop V DD Ripple 5 % I SD * = 5 V for logic level devices Fig. 4 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?9050. Document Number: 9050 S82998Rev. A, 2Jan09 7
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