An Alternative for Design Checking through Electrical Performance A Assessment t y Wu Paddy Principal AE Aug.13 2013
Agenda The Package/PCB Electrical Performance Checking Challenge Allegro Sigrity Integration for Package/PCB Checking Flow Electrical Performance Checking for PKG/PCB items- Trace Impedance / Coupling Check Electrical Performance Checking for PKG items- Power/Ground Inductance Power/Ground Current Density Customer real case Summary 2 2013 Cadence Design Systems, Inc. All rights reserved.
The Electrical Performance Checking Challenge Two basic q questions and request q for high g speed p signals g Impedance & Timing 10Layers FCBGA 4L PCB 22x12cm How fast can you check these Layouts performance? 3 2013 Cadence Design Systems, Inc. All rights reserved.
Layout and Analysis Engineers Co-work Flow Different tool environments Different languages Layout Engineer Analysis Engineer Provide layout v1 Iteration Manufacture rule Constraint rule Route-ability Request to modify layout Performance (Electrical,themal,..) Timing Impedanced Cadence can provide the seamless working environment. 4 2013 Cadence Design Systems, Inc. All rights reserved.
Analyzed/Checking Work Flow (Cont d) One layout, one model build One kind of simulation, one model build Model Build (60mins) Model Sim. (? Mins.) Data Analysis Provide Rule Cadence can provide model re-used function for specific simulation. 5 2013 Cadence Design Systems, Inc. All rights reserved.
Analyzed/Checking Work Flow Time consumed for model build and exchanged Tool A Impedance Checking? Tool B I/O P/G RLC Checking Model build- 60mins Model build- 60mins Electrical l Engineer Layout version1 Layout version2 Model build- 60mins Model build- 60mins Tool C Current density Checking Tool D Timing Checking? 6 2013 Cadence Design Systems, Inc. All rights reserved.
Allegro Sigrity Integration for Checking Flow Optimized Design More Faster Timingi Checking XIM, PowerSI, Speed2000 PowerDC Thermal Checking XIM, PowerDC Current desity Checking.SPD file 60mins Impedance Checking P/G per pin RLC Checking XIM, PowerSI, Speed200 P/G RLC Checking XIM XIM 7 2013 Cadence Design Systems, Inc. All rights reserved.
What is Allegro Sigrity Suite Edits can be made in base tool and quickly investigated in XIM, PDC, 3D-EM,.. 1 2 3 8 2013 Cadence Design Systems, Inc. All rights reserved.
Agenda The Package/PCB Electrical Performance Checking Challenge Allegro Sigrity Integration for Package Checking Flow Electrical Performance Checking for PKG/PCB items- Trace Impedance / Coupling Check Electrical Performance Checking for PKG items- Power/Ground Inductance Power/Ground Current Density Customer real case Summary 9 2013 Cadence Design Systems, Inc. All rights reserved.
Electrical Checking for PKG/PCB items - Trace Impedance --- function1 Impedance are displayed along the length of the nets Potential issue Top-to-bottom layer transition dogleg traces do not have good reference planes A A top-to-bottom transitions 10 2013 Cadence Design Systems, Inc. All rights reserved.
Electrical Checking for PKG/PCB items - Trace Impedance --- function2 Fast find out the impedance discontinuity location Potential issue The traces do not have the same trace width Layer1 Impedance value Impedance table 11 2013 Cadence Design Systems, Inc. All rights reserved.
Electrical Checking for PKG/PCB items - Trace Impedance --- Applications i Find the each groups impedance and define limited impedance zone Simulation time 3 min. Impedance plot DDR_DQ9 Spec. 12 2013 Cadence Design Systems, Inc. All rights reserved.
Electrical Checking for PKG/PCB items - Trace Impedance --- Applications i Fast find out the numbers of impedance discontinuity on each nets Layer1 impedance Impedance table More discontinuities, SI more worse. 13 2013 Cadence Design Systems, Inc. All rights reserved.
Electrical Checking for PKG/PCB items - Trace Timing i Different languages Complicated relationships mil mv & ps Layout Design Rules multiple individual geometry-based Layout SI Performance collective combined electrical-based 14 2013 Cadence Design Systems, Inc. All rights reserved.
Electrical Checking for PKG/PCB items - Trace Timing i --- Applications i Find the each nets and groups timings Timing table DDR_DQ0 per layer timing Group1 Group2 Group3 These timing table can give electrical/layout engineers with the same languages. Group4 15 2013 Cadence Design Systems, Inc. All rights reserved.
Electrical Checking for PKG/PCB items - Trace Coupling --- Applications i Coupling is defined with Near-ended ended Crosstalk as a victim. User can define the coupling coefficient for each of nets. 16 2013 Cadence Design Systems, Inc. All rights reserved.
Agenda The Package/PCB Electrical Performance Checking Challenge Allegro Sigrity Integration for Package Checking Flow Electrical Performance Checking for PKG/PCB items- Trace Impedance / Coupling Check Electrical Performance Checking for PKG items- Power/Ground Inductance Power/Ground Current Density Customer real case Summary 17 2013 Cadence Design Systems, Inc. All rights reserved.
Electrical Performance Checking for PKG items - XtractIM Electrical l Performance Assessment (EPA) 1 XtractIM EPA mode 2 For Signal Analysis Impedance and discontinuity, Trace timing Coupling co-efficient For P/G Analysis Per net-pair properties Per pin-based properties 3 For DC Current Analysis Check DC current density IR drop 18 2013 Cadence Design Systems, Inc. All rights reserved.
For P/G Analysis (Cont d) - Per net-pair properties --- function1 6-layer side-by-side flipchip package Run time 1 hour. One common reference GND (ph) Net Die-1 Die-2 VDD 3.722 3.746 VCCQ 27.589 25.002 Die-1 Die-2 Find worse loop inductance & unbalance inductance! 19 2013 Cadence Design Systems, Inc. All rights reserved.
For P/G Analysis (Cont d) - Per net-pair properties --- function2 6-layer single-die flipchip package Find which ground net with the minimum loop inductance. Layer4 Layer5 Layer6 GNDA VCC25A GND VCC2IO Wrong ground net for VCC25A!! 20 2013 Cadence Design Systems, Inc. All rights reserved.
For P/G Analysis (Cont d) - Per pin-based properties Assess Bump/BGA pin properties Self loop inductance Total loop inductance Resistance Intuitive 2D and 3D graphics Both die-side and board-side assessment With the assessment, pins with R&L higher than specified value will be found. The problematic area in the power/ground distribution system can be optimized to avoid design risk! 21 2013 Cadence Design Systems, Inc. All rights reserved.
Per-pin self loop inductance The loop inductance seen looking into one pin of the net being assessed when all other pins of all other enabled nets can serve as potential return paths. The jωl voltage at pin 3 with AC current forced into only pin 3 with return current flowing in pins {1,4,5,6,7,8}. The noise voltage at a pin due to current flow in that pin. 1 2 3 4 5 6 7 8 Legend VSS (ground) VDD1 (power) VDD2 (power) Identifies individually weak pins with respect to loop inductance. 22 2013 Cadence Design Systems, Inc. All rights reserved.
Per-pin total loop inductance The sum of self and all mutual inductances seen looking into one pin for the net being assessed. The jωl voltage at a pin with the same AC current forced into all pins of the net being assessed. The noise voltage at a pin due to current flow in all pins of that net. 1 2 3 4 5 6 7 8 Legend VSS (ground) VDD1 (power) VDD2 (power) Identifies pins/areas with potentially high voltage noise under general operating conditions. 23 2013 Cadence Design Systems, Inc. All rights reserved.
Per-pin R DC The DC resistance from a pin on one side of the package to the other side of the package where all pins of the same net on the other side are shorted together. For example: R 1 = R 1-ADEH,R 2 = R 2-BC,R F = R F-67 1 2 3 4 5 6 7 8 A B C D E F G H Legend VSS (ground) VDD1 (power) VDD2 (power) Identifies individually weak pins for DC IR drop. 24 2013 Cadence Design Systems, Inc. All rights reserved.
For P/G Analysis (Cont d) - Per pin-based properties --- Self loop inductance Easy to find per pin inductance 25 2013 Cadence Design Systems, Inc. All rights reserved.
For P/G Analysis (Cont d) - Per pin-based properties --- Self loop inductance 6-layer flipchip p package VCC25A to GNDA VCC25A to GND For the per-pin p results, the lump inductance of VCC25A/GND should be smaller than VCC25A/GNDA. 26 2013 Cadence Design Systems, Inc. All rights reserved.
For P/G Analysis (Cont d) - Per pin-based properties --- Total loop inductance Find the power pin with the lowest coupling Per-pin Self inductance Total inductance Per-pin Self inductance 2D plot Link the minimum loop inductance for the critical nets 27 2013 Cadence Design Systems, Inc. All rights reserved.
For DC Current Analysis (Cont d) IR drop Calculate l IR drop on vias, traces and planes Identify IR drop bottleneck area Current density Calculate current density on vias, traces and planes Identify high current density area that exceeds limit Avoid regional over-heat caused by high current density 28 2013 Cadence Design Systems, Inc. All rights reserved.
For DC Current Analysis (Cont d) - Check DC Current Density 4-layer wirebond package Layout Via current density Plane current density 29 2013 Cadence Design Systems, Inc. All rights reserved.
For DC Current Analysis (Cont d) - Check Thermal Effect (PowerDC) 4-layer wirebond package Layout Via temperature Plane temperature Hot spot 25.06 Head spread 25.05 Hot spot 30 2013 Cadence Design Systems, Inc. All rights reserved.
Agenda The Package/PCB Electrical Performance Checking Challenge Allegro Sigrity Integration for Package Checking Flow Electrical Performance Checking for PKG/PCB items- Trace Impedance / Coupling Check Electrical Performance Checking for PKG items- Power/Ground Inductance Power/Ground Current Density Customer real case Summary 31 2013 Cadence Design Systems, Inc. All rights reserved.
The P/G performance checking flow for AC field PKG Layout XIM-EPA Check Net-based Inductance Pass Spec. Done PDC-Current density Equal current mode XIM-EPA Check Pin-based PDC-Current density Equal voltage mode Layout Modified 32 2013 Cadence Design Systems, Inc. All rights reserved.
The P/G performance checking flow for DC field PKG Layout XIM-EPA P/G DC current check PowerDC- P/G DC current check Via current by layer Voltage distribution by layer Plane current density by layer Via current by layer Voltage distribution by layer Plane current density by layer Via/trace/shape constraint DC IR drop table DC current vector show IR drop/ via current /trace current Pass Spec. Done Layout Modified 33 2013 Cadence Design Systems, Inc. All rights reserved.
Step1 - Net based inductance checking 745L FCCSP 13.5x13.5mm 2+2+2 layers Bump height: ht 90um (Sim.1); 40um (sim.2) Simulation time 5 mins Net VDD VDD_AP VDD_APMEM VDD_DDRDDR VDD_G3D VDD_ON Spec. 3.5 18 80 130 20 50 Sim.1 50 5.0 23.8 84.2 161.2 27.77 56.9 Sim.2 4.9 23.1 81.0 156.7 26.8 53.4 Unit:pH 34 2013 Cadence Design Systems, Inc. All rights reserved.
Step2 Pin-based inductance checking VDD_G3D/VSS per pin-based properties imulation time 24 mins VDD_G3D bump side VSS bump side VDD_G3D ball side VSS ball side 35 2013 Cadence Design Systems, Inc. All rights reserved.
VDD_G3D/VSS DC current density plot DC current density plot checking Simulation time 24 mins PDC-Equal voltage mode PDC-Equal current mode Find minimum DC-R path Find maximum IR drop 36 2013 Cadence Design Systems, Inc. All rights reserved.
VDD_G3D/VSS DC current density plot PDC current plot Simulation time 2 mins Original Net Spec. VDD_G3D 20pH Sim.1 27.7 Sim.2 (Lower bump) Sim.3 Add via with lower bump 26.8 26.7 Modified Add via 37 2013 Cadence Design Systems, Inc. All rights reserved.
VDD_DDR/VSS loop inductance reduction Add/Change VDD_DDR/VSS ball locations Simulation time 5 mins Net Spec. Sim.1 Sim.2 (lower bump) Sim.3 Sim.4 VDD_ DDR 130pH 161.2pH 156.7pH 122.8pH 111.7pH Original Modified sim3 sim4 38 2013 Cadence Design Systems, Inc. All rights reserved.
Agenda Package Performance Checking Challenge Allegro Sigrityit Integration ti for Package Checking Flow Package Performance Checking Items- Impedance / Trace Timing Power/Ground Inductance Power/Ground Current Density Thermal Effect ASE Case Studied Results & ASI Live Demo Summary 39 2013 Cadence Design Systems, Inc. All rights reserved.
Summary Allegro + Sigrity enables seamless physical and electrical design flow Easy for use Well layout version control for simulation Fast for simulation Fast to find and optimize potential risk Impedance/ Trace Timing Power/Ground Inductance Power/Ground Current Density Thermal Effect 40 2013 Cadence Design Systems, Inc. All rights reserved.