LOW POWER DESIGN METHODOLOGIES

LOW POWER DESIGN METHODOLOGIES

LOW POWER DESIGN METHODOLOGIES edited by Jan M. Rabaey University Califomia and Massoud Pedram University of Southem Califomia SPRINGER SCIENCE+BUSINESS MEDIA, LLC

ISBN 978-1-46 13-5975-3 DOI 10.1007/978-1-4615-2307-9 ISBN 978-1-4615-2307-9 (ebook) Consulring Editor: Jonathan Allen, Massachuseus Insrüute of Techn%gy Library of Congress Cataloging-in-Publication Data A C.I.P. Catalogue record for this book is available from the Library of Congress. Copyright 10 1996 by Springer Science+Business Media New York. Originally published by KJuwer Academic Publishers in 1996 Softcover reprint ofthe hardcover I st edition 1996 All rights reserved. No pan of Ihis publication may be reproduced, stored in a retrieval system or Iransmitted in any fonn or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media. LLC Printed on acid-free paper. This printing is a digital duplication of the original edition.

Table of Contents Table of Contents Preface Author Index v ix xi 1. Introduction 1 Jan M.Rabaey, Massolld Pedram and Palll Landman 1.1. Motivation... 1 1.2. Sources of Dissipation in Digital Integrated Circuits... 5 1.3. Degrees of Freedom... 8 1.4. Recurring Themes in Low-Power... 12 1.5. Emerging Low Power Approaches - An Overview... 14 1.6. Sununary... 15 PART I Technology and Circuit Design Levels 2. Device and Technology Impact on Low Power Electronics 21 Chenming Hu 2.1. Introduction... 21 2.2. Dynamic Dissipation in CMOS... 21 2.3. Effects of and on Speed... 22 2.4. Constraints on Reduction... 25 2.5. Transistor Sizing and Optimal Gate Oxide Thickness... 26 2.6. Impact of Technology Scaling... 28 2.7. Technology and Device Innovations... 31 2.8. Sununary... 33

vi Low Power Design Methodologies 3. Low Power Circuit Techniques 37 Christer Svensson and Dake ill 3.1. Introduction... 37 3.2. Power Consumption in Circuits... 38 3.3. Flip-flops and Latches... 47 3.4. Logic... 52 3.5. High Capacitance Nodes... 57 3.6. Summary... 62 4. Energy-Recovery CMOS 65 William C. Athas 4.1. A Simple Example... 67 4.2. A look at some practical details... 72 4.3. Retractile Logic... 76 4.4. Reversible Pipelines... 79 4.5. High-Performance Approaches... 84 4.6. Summary... 94 5. Low Power Clock Distribution 101 Joe G. Xi and Wayne W-M. Dai 5.1. Power Dissipation in Clock Distribution... 101 5.2. Single Driver vs. Distributed Buffers... 103 5.3. Buffer and Device Sizing under Process Variations... 109 5.4. Zero Skew vs. Tolerable Skew... 114 5.5. Chip and Package Co-Design of Clock Network... 119 5.6. Summary... 123

Table of Contents vii PART II Logic and Module Design Levels 6. Logic Synthesis for Low Power 129 Massoud Pedram 6.1. Introduction... 129 6.2. Power Estimation Techniques... 132 6.3. Power Minimization Techniques... 146 6.4. Concluding Remarks... 156 7. Low Power Arithmetic Components 161 Thomas K. Callaway alld Earl E. Swartzlallder 7.1. Introduction... 161 7.2. Circuit Design Style... 162 7.3. Adders... 170 7.4. Multipliers... '"... 186 7.5. Division... 194 7.6. Summary... 198 8. Low Power Memory Design 201 Kiyoh Itoh 8.1. Introduction... 201 8.2. Sources and Reductions of Power Dissipation in Memory Subsystem... 205 8.3. Sources of Power Dissipation in DRAM and SRAM... 213 8.4. Low Power DRAM Circuits... 218 8.5. Low Power SRAM Circuits... 241

viii Low Power Design Methodologies PART III Architecture and System Design Levels 9. Low-Power Microprocessor Design 255 Sonya Gary 9.1. System Power Management Support... 256 9.2. Architectural Trade-Offs For Power...,... 260 9.3. Choosing the Supply Voltage... 273 9.4. Low-Power Clocking... 276 9.5. Implementation Options for Low Power... 281 9.6. Power and PeIformance: Comparing Microprocessors... 284 9.7. Summary... 286 10. Portable Video-on-Demand in Wireless Communication 289 Teresa H. Meng. Benjamin M. Gordon. and Ely K. Tsern 10.1. Introduction... 290 10.2. Video Compression for Portable Applications... 292 10.3. Subband Decomposition and Pyramid Vector Quantization... 296 10.4. Error-Resilient Compression... 302 10.5. Low-Power Circuit Design Techniques... 308 10.6. Low-Power Decoder Architectures... 317 10.7. Summary... 332 11. Algorithm and Architectural Level Methodologies 335 Renll Mehra. David Udsky. Arthur Abnolls. Palll Landman and Jan Rabaey 11.1. Introduction... 335 11.2. Design Flow... 336 11.3. Algorithm level: Analysis and Optimization... 338 11.4. Architecture level: Estimation and Synthesis... 350 11.5. Summary... 359 Index 363

Preface Most of the research and development efforts in the area of digital electronics have been oriented towards increasing the speed and the complexity of single chip digital systems. This has resulted in a powerful, but power-hungry, design technology, which enabled the development of personal workstations, sophisticated computer graphics, and multi-media capabilities such as real-time speech recognition and real-time video. While focusing the attention on speed and area, power consumption has long been ignored. This picture is, however, undergoing some radical changes. Power consumption of individual components is reaching the limits of what can be dealt with by economic packaging technologies, resulting in reduced device reliability. Dealing with power is rapidly becoming one of the most demanding issues in digital system design. This situation is aggravated by the increasing demand for portable systems in the areas of communication, computation and consumer electronics. Improvements in battery technology are easily offset by the increasing complexity and performance of those applications. To guarantee a reasonable battery operation time, a dramatic (e.g., loox) reduction of the power consumption is essential. These realizations spurred a renewed interest in low power design over the last five years. Researchers learned quickly that there is no single solution to the power dissipation problem. In fact, to be meaningful and have a real impact, power optimization should occur at all levels of the design hierarchy, including the technology, circuit, layout, logic, architectural and algorithmic levels. It is our experience that combining optimizations at all those levels easily results in orders of magnitude of power reduction. Realizing these potential savings requires a thorough understanding of where power is dissipated in a digital integrated circuit. Once the dominant sources of dissipation are identified, a whole battery of low power design techniques can be brought in action. A significant portion of the overall challenge of making low power design techniques and methodologies practical involves going

x Low Power Design Methodologies Preface through the existing synopsis of power conscious techniques and finding the right combination of methods and tools for a particular application domain. It is a fair statement to say that low power design is foremost an educational problem. For too long. digital integrated circuit courses focused solely on performance and area optimization. To make low power design a reality. it is essential to make the power dimension an integral part of the design process. even in the early phases of the design conception. This book has been conceived as an effort to bring all aspects of low power design together in a single document. It covers all layers of the design hierarchy from the technology. circuit. logic and architectural levels up to the system layer. Besides offering an in-depth insight into the mechanisms of power dissipation in digital circuits. it also presents the state-of-the-art approaches to power estimation and reduction. Finally. it introduces a global view on low power design methodologies and how these are being captured in the latest design automation environments. The different chapters from this manuscript were developed by the leading researchers in their respective areas. Contributions are from both academia and industry. The many contributors of this book have extensively documented the various approaches for designing and implementing power efficient circuits and systems. and have presented them in a way that is understandable and useful to the designers as well as developers. The book can also be used as a textbook for teaching an advanced course on low power design methodologies and approaches. Instructors can select various combinations of chapters and augment them with some of the many references provided at the end of each chapter to tailor the book to their educational needs. We are convinced that this document will serve as a broad and thorough introduction for anyone interested in the low-power dimension of design and hope that it will spur further research in all aspects of low power design. Again. mastering the power problem is mandatory if integrated circuits are to maintain their growth curve of the last decades. Jail M. Rabaey. Tokyo Massolld Pedram. Los Angeles

Author Index Arthur Abnous University of California, Berkeley abnous@eecs.berkeley.edu William Athas Information Sciences Institute (lsi) athas@isledu Thomas K. Callaway University of Texas. Austin tkc@pine.ece.utexas.edu Wayne W M. Dai University of California, Santa Cruz dai@ce.ucsc.edu Sonya Gary Motorola Somerset sonyag@ibmoto.com Benjamin M. Gordon Stanford University bgordon@tilden.stanford.edu Chenming Hu University of California, Berkeley hu@eecs.berkeley.edu Kiyoh Hoh Hitachi Ltd., Kokubunji-shi 81-423-27-7694 (fax) Paul E. Landman Texas Instruments, Dallas landman@nikki.hc.ti.co David Lidsky University of California, Berkeley lidsky@eecs.berkeley.edu Dake Liu University of Linkoping. Sweden dake_l@ifm.liu.se Renll Mehra University of California, Berkeley mehra@eecs.berkeley.edu Teresa H. Meng Stanford University teresa@tilden.stanford.edu Massolld Pedram University of Southern California massoud@zugros.usc.edu Jan M. Rabaey University of California, Berkeley jan@eecs.berkeley.edu Christer Svensson University of Linkoping, Sweden chs@ifm.liu.se Earl E. Swartzlander University of Texas, Austin e.swartzlander@compmail.com Ely K. Tsern Stanford University tsern@tilden.stanford.edu Joe G. Xi University of California. Santa Cruz joex@ce.ucsc.edu

LOW POWER DESIGN METHODOLOGIES