R DS(on), Drainto Source On Resistance (m ) I D, Drain Current (A) PD 97782A Applications StrongIRFET l Brushed Motor drive applications l BLDC Motor drive applications l Battery powered circuits l Halfbridge and fullbridge topologies l Synchronous rectifier applications l Resonant mode power supplies l ORing and redundant power switches l DC/DC and AC/DC converters l DC/AC Inverters G D S V DSS HEXFET Power MOSFET R DS(on) typ. max. I D (Silicon Limited) I D (Package Limited) 40V.0m.3m 409Ac 95A D Benefits l l l l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and Avalanche SOA Enhanced body diode dv/dt and di/dt Capability LeadFree S D G TO220AB G D S Gate Drain Source Ordering Information Base Part Number Package Type Standard Pack Complete Part Number Form Quantity TO220 Tube 50 6.0 500 I D = A 400 Limited By Package 4.0 300 T J = 25 C 200 0.0 4 6 8 2 4 6 8 20 V GS, Gate to Source Voltage (V) Fig. Typical OnResistance vs. Gate Voltage 0 25 50 75 25 50 75 T C, Case Temperature ( C) Fig 2. Maximum Drain Current vs. Case Temperature www.irf.com 05/22/2
Absolute Maximum Ratings Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V (Silicon Limited) 409c I D @ T C = C Continuous Drain Current, V GS @ V (Silicon Limited) 289c I D @ T C = 25 C Continuous Drain Current, V GS @ V (Wire Bond Limited) 95 A I DM Pulsed Drain Current d 524 P D @T C = 25 C Maximum Power Dissipation 375 W Linear Derating Factor 2.5 W/ C V GS GatetoSource Voltage ± 20 V T J Operating Junction and 55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds (.6mm from case) 300 C lbfx in (.Nx m) Mounting torque, 632 or M3 screw Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 760 mj E AS (tested) Single Pulse Avalanche Energy Tested Value k 360 I AR Avalanche Currentd See Fig. 4, 5, 22a, 22b A E AR Repetitive Avalanche Energy d mj Thermal Resistance Symbol Parameter Typ. Max. Units R JC JunctiontoCase j 0.40 R CS CasetoSink, Flat Greased Surface 0.50 R JA JunctiontoAmbient 62 C/W Static @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V (BR)DSS DraintoSource Breakdown Voltage 40 V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.04 V/ C R DS(on) Static DraintoSource OnResistance V GS(th) Gate Threshold Voltage 2.2 3.9 V I DSS DraintoSource Leakage Current.0 μa 50 I GSS GatetoSource Forward Leakage na GatetoSource Reverse Leakage R G Internal Gate Resistance 2. Conditions V GS = 0V, I D = 250μA Reference to 25 C, I D =.0mAd.0.3 m V GS = V, I D = A g.2 V GS = 6.0V, I D = 50A g V DS = V GS, I D = 250μA V DS = 40V, V GS = 0V V DS = 40V, V GS = 0V, T J = 25 C V GS = 20V V GS = 20V Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 95A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN40) Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by T Jmax, starting, L = 0.5mH R G = 50, I AS = A, V GS =V. I SD A, di/dt 990A/μs, V DD V (BR)DSS, T J 75 C. Pulse width 400μs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from 0 to 80% V DSS. ˆ R is measured at T J approximately 90 C.. This value determined from sample failure population, starting, L= 0.5mH, R G = 50, I AS = A, V GS =V. 2 www.irf.com
Dynamic @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 50 S Q g Total Gate Charge 300 460 nc Q gs GatetoSource Charge 77 Q gd GatetoDrain ("Miller") Charge 98 Q sync Total Gate Charge Sync. (Q g Q gd ) 202 t d(on) TurnOn Delay Time 32 ns t r Rise Time 5 t d(off) TurnOff Delay Time 60 t f Fall Time C iss Input Capacitance 4240 pf C oss Output Capacitance 230 C rss Reverse Transfer Capacitance 460 C oss eff. (ER) Effective Output Capacitance (Energy Related) i 2605 C oss eff. (TR) Effective Output Capacitance (Time Related)h 2920 Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current 394c A Conditions V DS = V, I D = A I D = A V DS =20V V GS = V g I D = A, V DS =0V, V GS = V V DD = 20V I D = 30A R G = 2.7 V GS = V g V GS = 0V V DS = 25V ƒ =.0 MHz V GS = 0V, V DS = 0V to 32V i V GS = 0V, V DS = 0V to 32V h Conditions MOSFET symbol (Body Diode) showing the I SM Pulsed Source Current 576 A integral reverse G (Body Diode)d pn junction diode. S V SD Diode Forward Voltage 0.86.2 V, I S = A, V GS = 0V g dv/dt Peak Diode Recovery f 2.7 V/ns T J = 75 C, I S = A, V DS = 40V t rr Reverse Recovery Time 52 ns V R = 34V, 52 T J = 25 C I F = A Q rr Reverse Recovery Charge 97 nc di/dt = A/μs g 97 T J = 25 C I RRM Reverse Recovery Current 2.3 A t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by LSLD) D www.irf.com 3
C, Capacitance (pf) V GS, GatetoSource Voltage (V) I D, DraintoSource Current (A) R DS(on), DraintoSource On Resistance (Normalized) I D, DraintoSource Current (A) I D, DraintoSource Current (A) 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 4.8V BOTTOM 4.5V 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 4.8V BOTTOM 4.5V 4.5V 4.5V 60μs PULSE WIDTH Tj = 25 C 0. V DS, DraintoSource Voltage (V) Fig 3. Typical Output Characteristics 60μs PULSE WIDTH Tj = 75 C 0. V DS, DraintoSource Voltage (V) Fig 4. Typical Output Characteristics 0.8 I D = A V GS = V.6.4 T J = 75 C.2.0 V DS = 25V 60μs PULSE WIDTH.0 2 3 4 5 6 7 V GS, GatetoSource Voltage (V) Fig 5. Typical Transfer Characteristics 0.8 0.6 60 40 20 0 20 40 60 80 20406080 T J, Junction Temperature ( C) Fig 6. Normalized OnResistance vs. Temperature 000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 4.0.0 I D = A V DS = 32V V DS = 20V 00 C iss C oss 8.0 6.0 C rss 4.0 0 0.0 0 50 50 200 250 300 350 400 V DS, DraintoSource Voltage (V) Q G, Total Gate Charge (nc) Fig 7. Typical Capacitance vs. DraintoSource Voltage Fig 8. Typical Gate Charge vs. GatetoSource Voltage 4 www.irf.com
R DS (on), Drainto Source On Resistance ( m ) V (BR)DSS, DraintoSource Breakdown Voltage (V) Energy (μj) I SD, Reverse Drain Current (A) I D, DraintoSource Current (A) 0 00 OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 75 C 0 msec μsec Limited by package msec 0. 47 46 45 V GS = 0V 0.0 0.5.0.5 2.5 V SD, SourcetoDrain Voltage (V) Fig 9. Typical SourceDrain Diode Forward Voltage Id =.0mA Tc = 25 C DC Tj = 75 C Single Pulse 0. 0. V DS, DraintoSource Voltage (V) Fig. Maximum Safe Operating Area 2.5 V DS = 0V to 32V 44.5 43.0 42 4 0.5 40 60 40 20 0 20 40 60 80 20406080 T J, Temperature ( C ) Fig. DraintoSource Breakdown Voltage 0.0 0 5 5 20 25 30 35 40 45 V DS, DraintoSource Voltage (V) Fig 2. Typical C OSS Stored Energy 6.0 4.0 V GS = 5.5V V GS = 6.0V V GS = 7.0V V GS = 8.0V V GS =V 0.0 0 200 400 600 800 0 200 I D, Drain Current (A) Fig 3. Typical OnResistance vs. Drain Current www.irf.com 5
E AR, Avalanche Energy (mj) Avalanche Current (A) Thermal Response ( Z thjc ) C/W 0. 0.0 D = 0.50 0.20 0. 0.05 0.02 0.0 0.00 0.000 E006 E005 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) 0 SINGLE PULSE ( THERMAL RESPONSE ) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc Fig 4. Maximum Effective Transient Thermal Impedance, JunctiontoCase Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 50 C and Tstart =25 C (Single Pulse) Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25 C and Tstart = 50 C..0E06.0E05.0E04.0E03.0E02.0E0 tav (sec) Fig 5. Typical Avalanche Current vs.pulsewidth 800 700 600 500 400 300 200 TOP Single Pulse BOTTOM.0% Duty Cycle I D = A Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) 0 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) Fig 6. Maximum Avalanche Energy vs. Temperature P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av 6 www.irf.com
Q RR (nc) I RRM (A) Q RR (nc) V GS(th), Gate threshold Voltage (V) I RRM (A) 4.0 2 I F = 60A 3.5 V R = 34V 3.0 8 T J = 25 C 2.5 I D = 250μA I D =.0mA I D =.0A 6 4.5 2.0 75 50 25 0 25 50 75 25 50 75 T J, Temperature ( C ) 0 0 200 400 600 800 0 di F /dt (A/μs) Fig 7. Threshold Voltage vs. Temperature Fig. 8 Typical Recovery Current vs. di f /dt 2 8 I F = A V R = 34V T J = 25 C 300 250 200 I F = 60A V R = 34V T J = 25 C 6 4 50 2 0 0 200 400 600 800 0 di F /dt (A/μs) Fig. 9 Typical Recovery Current vs. di f /dt 50 0 200 400 600 800 0 di F /dt (A/μs) Fig. 20 Typical Stored Charge vs. di f /dt 260 220 80 I F = A V R = 34V T J = 25 C 40 60 0 200 400 600 800 0 di F /dt (A/μs) Fig. 2 Typical Stored Charge vs. di f /dt www.irf.com 7
D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG V DD Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test ReApplied Voltage Body Diode Inductor Current Curent Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 22. Peak Diode Recovery dv/dt Test Circuit for NChannel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 20V V GS tp D.U.T IAS 0.0 V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 90% R G V DD VV GS Pulse Width µs Duty Factor % V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 50K Vgs 2V.2 F.3 F V GS D.U.T. V DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform 8 www.irf.com
TO220AB Package Outline Dimensions are shown in millimeters (inches) TO220AB Part Marking Information (;$03/( 7,6,6$,5) /27&2'( $66(0%/('2::,7($66(0%/</,(& RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'( 3$5780%(5 '$7(&2'( <($5 :((. /,(& TO220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Qualification information Qualification level RoHS compliant Industrial (per JEDEC JESD47F guidelines) TO220 Not applicable Yes Qualification standards can be found at International Rectifier s web site: http://www.irf.com/productinfo/reliability/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information: http:www.irf.com/whotocall/salesrep/ Applicable version of JEDEC standard at the time of product release. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: N. Sepulveda Blvd., El Segundo, California 90245, USA Tel: (3) 25275 TAC Fax: (3) 2527903 Visit us at www.irf.com for sales contact information. 05/202 www.irf.com 9