Structured Electronic Design

Structured Electronic Design Building the nullor: Biasing R R bias1 bias 2 V + I ce c R bias 2 C 2 C couple couple1 1

Today Specs 1 2 N D B Bias Verification Biasing Verification (simulation) 2

At the end of small-signal design C comp R f I source R source R load I c =... V c =... I c =... V c =... I c =... V c =... I c =... V c =... noise model simplification LP-product clipping Bias quantities are just parameters 3

At the end of small-signal design C comp R f C μ I source R source R load r o C μ C μ r o C μ r o r o I c =... V c =... I c =... V c =... I c =... V c =... I c =... V c =... noise model simplification LP-product clipping Bias quantities are just parameters 4

The small-signal model 5

Inside de small-signal model r b c μ A "real" rπ cπ r o transistor A battery 6

Conclusion When only DC energy sources exist, a non-linear element is needed for amplification P DCpower f P Signal Amplifier AC-power f 7

Using the non-linear element I c Distortion Offset I cq Offset I c di V ) = IcQ + + d V beq 2 c( be d f( Vbe) ( Vbe VbeQ ) 2 V be 2dV V = V be V = V be beq be beq V be 2 ( Vbe Vbe Q ) +... 8

Biasing is translation to the origin I c I cq Distortion V beq V be 9

Adding and subtracting offsets v be + + Σ I c di V = IcQ+ + d 2 c( be) d f( Vbe) ( Vbe VbeQ) 2 V be 2dV V = V be V = V be beq be beq + 2 ( Vbe Vbe Q)... + _ Σ i c v beq I cq 10

Translation (bias) sources V ce V ds V be V gs I b I c I g I d No current or voltage offset No current or voltage offset No current or voltage offset 2 independent sources 2 sources need control I c,d and V ce,ds independent 11

Output voltage not enforced internally. (Device is a current source) V be Boundary conditions V ce I b I c Following stage acts as short-circuit (usually) Preceding stage is an open-circuit (usually) 12

Implementation of the control current sensor V ds V gs I offset Preceding stage I g I d Following stage The loops need a loop filter but we will deal with that later 13

The current sensor current sensor I offset I g Find or create a voltage Measure the voltage 14

Poor mans current sensor Voffset I offset C biasfilter C biasfilter V offset I offset V offset I offset 15

Special case at input I offset V gs current sensor V ds Signal source current sensor I g I d I offset Following stage 16

Special case at output Floating node 17

Floating nodes can be very useful current sensor I offset I g Current sensitive voltage Free implementation of a current sensor 18

Biasing a single transistor Filter I b Vbe Vce I c 19

Biasing a single transistor Ib Voffset C biasfilter V be V ce I c 20

Biasing a single transistor Ib Voffset V be C biasfilter V ce I c Conflict: High gain gives high bandwidth (undesired for bias signals) Low gain gives much offset 21

Biasing a single transistor (2) ΔI b Voffset V be C biasfilter V ce I c I bnom, Add I b,nom to reduce offset at limited loop gain. 22

Local voltage control loops V control V beq1 There is no current through V control V control does not produce power V control can be a passive component 23

Local voltage control loops V control C control V beq1 V beq1 Only possible because this bias source is not delivering power 24

Practical examples 25

Biasing a single transistor ΔI b Voffset V be C biasfilter R bias V ce I c I b, nom V be IbRbias = Vce Vbe V ce C biasfilter I c Problem: Filter function is lost! 26

Biasing a single transistor Rbias1 R bias 2 C biasfilter V be V ce C Vce I c ( ) I R + R = V V b bias1 bias2 ce be 27

Biasing a single transistor Rbias1 R bias 2 C biasfilter C control V ce C Vce I c ( ) I R + R = V V b bias1 bias2 ce be 28

Non-ideal biasing a single transistor Rbias1 R bias 2 Filter I b C biasfilter Vbe Vce C control C Vce I c I c 5 non-idealities: 1. R bias1 loads input 2. R bias2 loads output 3. Collector bias voltage depends on I b 4. C control increases noise contribution of I b 5. C Vce increases output voltage swing: distortion 29

C Vce increases output voltage swing: distortion Rbias1 R bias 2 C biasfilter C control C Vce I c Biasing components are inside the loop 30

How about this? R R bias1 bias 2 V + I ce c R bias2 C Vce C control 1. R bias1 loads input 2. R bias2 loads output 3. Collector bias voltage depends on I c 4. C couple control increases noise contribution of I b 5. C Vce increases output voltage swing: distortion 6.??? Collector current depends on I b and D (unreliable) 31

An active implementation 2I b R bias 2 V ce C biasfilter C control C Vce I c 1. R bias2 loads output (but it can be large) 2. C control increases noise contribution of I b 3. C Vce increases output voltage swing: distortion 4. takes a lot of transistors 32

Biasing a circuit It works, but too many sources too many controls current sensor current sensor current sensor 33

Removing a voltage control loop V ce3 V be4 Q 3 Q 4 V beq4 Set source V be at nominal value Δ V = V V Bias voltage error for Q 3 : ceq3 be beq4 34

Removing voltage controls current sensor current sensor current sensor V V CE Error V CE Error CE Error V Error V CE Error CE Error V CE Not Not removed 35

Removing current control loops Q 1 current sensor current sensor current sensor Q3 Q4 Q 2 ΔI B Try to preserve floating nodes as sensing point Bias current error I +Δ I c B 36

One overall current control loop Q 1 Q 2 Q3 Q4 Bias Bias current current error error Bias Bias current current error error Bias Bias current current error error Bias Bias current current correct correct 37

Circuit with 2 loops and 6 errors V V CE Error V CE Error CE Error V Error V CE Error CE Error V CE Bias Bias current current error error Bias Bias current current error error Bias Bias current current error error Last transistor has no biasing errors Other transistors have acceptable errors One voltage loop to be implemented One current loop to be implemented 38

The local voltage loop 39

The current sensor + Σ - V ce4 V ce4 + Σ - V ce4 40

The bias current loop V ce4 V ce4 Practical loop Voltage and current sources at inconvenient places 41

- Shifting of voltage sources I v n,1 + 2 1 - v n + 4 III II - v n,2 + 3 R load v n,1 = v n,2 = v n + V 2 V + 1 R load + + + V 2 V 1 V 1 Preference for grounded branches Grounded sources become supply voltages 42

Shifting voltage sources V ce4 V ce4 43

Shifting voltage sources V ce4 V ce4 44

Merging current sources 3 i n,1 i n,2 1 2 i n Create grounded current sources 1 source 2 equal sources 45

Merging the current sources V ce4 2 equal sources 46

Result V + CC 4 - I b2 I c1,2 I I c3 c 4 Q 1 Q 2 + V CC1 + - V CC 2 - Q + Q3 4 V CC 3-47

Supply voltage or current minimization I I I d1d 1 Id2 d2= 0 I d V d2 I d Q 2 V d1 V g2 Q 2 V g1 Q 1 V g1 Q 1 V d1 V g2 V d1 V d2 Current minimization 48

Changing transistor type Bias sources change sign I d V d2 I d V g2 Q 2 2I d V d1 Q 1 Q 2 Q 1 I d V g1 I d Vg2 V d1 V g1 Voltage minimization 49

Low voltage or current designs Current sharing saves power? I d 2I d Q 2 Q 1 Q 2 Q 1 V d1 V d1 V g1 I d Vg2 V d1 V g1 V g2 V d2 Always 4 sources Low power? Power dissipation does not change Power reduction? Choice between low voltage or low current 50

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Unstable bias loop 52

Frequency compensation bias loop V CC 4 R Comp I c1,2 I I c3 c 4 Q 1 Q 2 Q Q 3 4 V CC1 V V CC 2 CC 3 Brute force : C biasfilter large Delicate : R Comp phantom zero 53

Differential circuits (b) Extra options that can be used as filter: Nodes that carry no signal Sum of node voltages that carries no signal 54

Differential/Common mode Common Common mode mode loop loop Σ Σ Differential Differential mode mode loop loop (needs (needs filter filter in in frequency frequency domain) domain) Still 2 loops and 2 loop filters (1 in f domain, 1 to filter out common mode via adder) Rely on matching, skip differential loop Then no filter in frequency domain needed Result: differential bias error 55

Summary of bias procedure Insert bias sources Reduce number of voltage control loops Reduce number of current control loops Shift voltage sources Merge current sources Implement current sensors Try to implement local loops with capacitor Implement bias filter Do frequency compensation 56

The finishing touch 57

Ideal sources Clipping 58

Practical voltage sources V CC Battery Voltage divider Decoupled voltage divider Non-linear voltage divider 59

Power supply rejection 150mV 100mV 50mV 0V 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(R3:1) V(D1:1) V(R1:1) Frequency 60

Power supply rejection 150mV 100mV 50mV 0V 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(R3:1) V(D1:1) V(R1:1) Frequency 61

Decoupling 1.0V 0.5V 0V 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(R7:2) V(R3:1) V(R1:1) Frequency 62

Decoupling 1.0V 0.5V 0V 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(R7:2) V(R3:1) V(R1:1) Frequency 63

Current source: implementation Resistor Transistor I out I out R V ref V ref R 64

Influence on the circuit I out I out C μ R Vcircuit Vcircuit V ref V ref R I r out out S i n = = = ( V ) ref Vcircuit R R 4kT R I r out out S i n ( V ) ref Vbe = R ro = = β fro D 4kT = + 2qI R b 65

Insert impedance only one by one V ref + - + - C μ C + μ + C μ - - 66

Current source: noise I out 4kTrb 2qI c V ref 2qI b R 4kT R 67

Influence of R on noise 2qI c 2qI c V ref V ref 2qI b I out 2qI b Extreme: lim R Extreme: lim R 0 68

Influence of R on noise 2qI b 2qI c 2qI c 2qI c V ref V ref 2qI b I out 2qI b Extreme: lim R Extreme: lim R 0 69

Current source: noise 4kTrb I out 2qI c β = 100 f V ref 2qI b R 4kT R S i out 2qIc 2qIb 4 kt ( R + rb) = + + 2 2 2 β f R r r 1 π π + 1+ R + rπ β fr β f 70

Noise resistor = Shot noise 2qI 2qI 4kTR β c + b = 2 2 2 R 1 f r r + 1+ π R + π r β R β π f f R = 2r π V = I R R out 5V β f = 100 kt 26mV q 71

Simulation **** TRANSISTOR SQUARED NOISE VOLTAGES (SQ V/HZ) RB RC RE IBSN IC IBFN TOTAL 1.313E-17 1.496E-20 0.000E+00 6.280E-15 1.095E-16 0.000E+00 6.403E-15 **** RESISTOR SQUARED NOISE VOLTAGES (SQ V/HZ) R_RL R_RE TOTAL 4.116E-17 8.040E-15 **** TOTAL OUTPUT NOISE VOLTAGE = 1.448E-14 SQ V/HZ = 1.204E-07 V/RT HZ 72

Simulation output **** TRANSISTOR SQUARED NOISE VOLTAGES (SQ V/HZ) **** TRANSISTOR SQUARED NOISE VOLTAGES (SQ V/HZ) RB RC RE IBSN IC IBFN 1.313E-17 1.496E-20 0.000E+00 6.280E-15 1.095E-16 0.000E+00 RB RC RE IBSN IC IBFN 1.754E-12 1.389E-20 0.000E+00 2.107E-15 2.310E-12 0.000E+00 (5 (5 kω) kω) (0 (0 Ω) Ω) TOTAL 6.403E-15 TOTAL 4.066E-12 **** RESISTOR SQUARED NOISE VOLTAGES (SQ V/HZ) **** RESISTOR SQUARED NOISE VOLTAGES (SQ V/HZ) R_RL R_RE R_RL TOTAL 4.116E-17 8.040E-15 **** TOTAL OUTPUT NOISE VOLTAGE = 1.448E-14 SQ V/HZ = 1.204E-07 V/RT HZ TOTAL 1.183E-16 **** TOTAL OUTPUT NOISE VOLTAGE = 4.066E-12 SQ V/HZ = 2.017E-06 V/RT HZ 73

Low power Low voltage Injected noise: 2qDI 2qI c = Injected noise: D ( I ) b 4q D = 4qD I I c I b 1V V be 6V 5V +Vbe Q 2 DI c Q 2 DI c 2qI b Q 1 I c 2qI b Q 1 I c Double noise current Negligible effect 74

Current source: power supply rejection v noise v noise V CC V CC C μ C μ i noise Q 1 I c i noise Q 1 I c Only HF injection Wide-band injection Cascode does not reduce the effect 75

Simulation tools 76

Simulation After design During the design Simulation result is never a surprise 77

Nullator and norrator Voltage amplifier E-type nullor implementation is first choice Source model To To prevent prevent single single connection connection error error Load 78

Simulation result 100V E=-10000 80V E=-1000 60V E=-100 40V 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(C3:2) V(C2:2) V(C1:2) Frequency 79

Nullator and norrator Voltage amplifier G-type nullor implementation Source model To To prevent prevent single single connection connection error error Load 80

Simulation results 120V G=-1000 80V G=-100 40V G=-10 0V 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(C3:2) V(C2:2) V(C1:2) Frequency 81

Simulation results G=-100, C1=10n, 20n 20n 100n 120V 80V 40V 0V 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(C3:2) V(C2:2) V(C1:2) Frequency 82

Transistor parameters **** **** BIPOLAR BIPOLAR JUNCTION JUNCTION TRANSISTORS TRANSISTORS NAME NAME Q_Q1 Q_Q1 MODEL MODEL Q2N3904 Q2N3904 IB IB 7.39E-06 7.39E-06 IC IC 9.93E-04 9.93E-04 VBE VBE 6.65E-01 6.65E-01 VBC VBC -1.00E+00-1.00E+00 VCE VCE 1.67E+00 1.67E+00 BETADC BETADC 1.34E+02 1.34E+02 GM GM 3.78E-02 3.78E-02 RPI RPI 4.06E+03 4.06E+03 RX RX 1.00E+01 1.00E+01 RO RO 7.56E+04 7.56E+04 CBE CBE 1.79E-11 1.79E-11 CBC CBC 2.80E-12 2.80E-12 CJS CJS 0.00E+00 0.00E+00 BETAAC BETAAC 1.54E+02 1.54E+02 CBX/CBX2 CBX/CBX2 0.00E+00 0.00E+00 FT/FT2 FT/FT2 2.91E+08 2.91E+08 83

C μ 4.0p 0V 0V 3.0p 1V 1V 2V 2V 2.0p 3V,4V,5V IMG(IC(Q1))/(6.28* Frequency) 1.0p 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz Frequency 84

Gummel plot DC-sweep V2 1 1.0A 2 200 150 100uA 100 10nA 50 1.0pA >> 0 0.2V 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1.0V 1 Ic(Q1) IB(Q1) 2 IC(Q1)/ IB(Q1) V_V2 85

Ideal transistor 1 100K 2 1.0 1.0u >> 100f 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1.0V 1 Ib(Q1) Ic(Q1) IC(Q1)/ IB(Q1) V_V2 86

Non-ideal high and low current behavior 1 100A 2 400 BF BF 416.4 416.4 IKF IKF.06678.06678 ISE ISE 1.000000E-12 1.000000E-12 NE NE 22 1.0A 300 1.0mA 200 ISE ISE and and NE NE IKF IKF 1.0uA 100 1.0nA >> 0 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1.0V 1 Ib(Q3) Ic(Q3) 2 IC(Q3)/ IB(Q3) V_V2 87

Biasing a transistor The The other stages Take current values from Gummel plot 88

NAME Q_Q1 MODEL Q2N3904 IB 7.39E-06 IC 9.89E-04 VBE 6.65E-01 VBC -7.40E-01 VCE 1.41E+00 BETADC 1.34E+02 GM 3.77E-02 RPI 4.07E+03 RX 1.00E+01 RO 7.56E+04 CBE 1.78E-11 CBC 2.94E-12 CJS 0.00E+00 BETAAC 1.53E+02 CBX/CBX2 0.00E+00 FT/FT2 2.89E+08 89

10V 1.0V G=1000 100mV 10mV 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(Rl1:2) Frequency 10V 1.0V G=100 100mV 10mV 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz V(Rl1:2) Frequency 90

Noise **** TRANSISTOR SQUARED NOISE VOLTAGES (SQ V/HZ) Q_Q1 RB RC RE IBSN IC IBFN TOTAL 1.360E-17 3.681E-25 0.000E+00 7.087E-16 3.975E-17 0.000E+00 7.620E-16 **** RESISTOR SQUARED NOISE VOLTAGES (SQ V/HZ) R_R1 R_R2 R_Rsim1 R_Rl1 R_Rs1 TOTAL 1.249E-16 1.101E-15 1.360E-20 1.199E-19 1.360E-15 **** TOTAL OUTPUT NOISE VOLTAGE = 3.348E-15 SQ V/HZ = 5.787E-08 V/RT HZ TRANSFER FUNCTION VALUE: V($N_0003)/V_Vs1 = 9.060E+00 EQUIVALENT INPUT NOISE AT V_Vs1 = 6.387E-09 V/RT HZ 91

Creating noise sources 92

Linda 93

Linda simulation 94

Linda: root locus 95

Linda: bode plot (magnitude) 96

Conclusions Idealized circuits can be simulated For verification To find transistor parameters To obtain transistor characteristics To see more complex information (e.g. f-behavior noise) Never a surprising result Linda A To see synthesis parameters (Loopgain, etc.) t 97