APT5010B2FLL APT5010LFLL 500V 46A 0.100

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Transcription:

POWER MOS 7 R FREDFET APT51B2FLL APT51LFLL 5V 46A.1 B2FLL Power MOS 7 is a new generation of low loss, high voltage, N-Channel enhancement mode power MOSFETS. Both conduction and switching losses are addressed with Power MOS 7 by significantly lowering R DS(ON) and Q g. Power MOS 7 combines lower conduction and switching losses along with exceptionally fast switching speeds inherent with APT's patented metal gate structure. Lower Input Capacitance Increased Power Dissipation Lower Miller Capacitance Easier To Drive Lower Gate Charge, Qg Popular T-MAX or TO-264 Package FAST RECOVERY BODY DIODE MAXIMUM RATINGS T-MAX All Ratings: T C = 25 C unless otherwise specified. G LFLL D S Symbol Parameter APT51B2FLL_LFLL S Drain-Source Voltage 5 M Continuous Drain Current @ T C = 25 C Pulsed Drain Current 1 46 184 M Gate-Source Voltage Continuous Gate-Source Voltage Transient ±3 ±4 P D Total Power Dissipation @ T C = 25 C Linear Derating Factor 52 4. Watts W/ C,T STG T L Operating and Storage Junction Temperature Range Lead Temperature:.63" from Case for 1 Sec. -55 to 15 3 C I AR Avalanche Current 1 (Repetitive and Non-Repetitive) 5 E AR E AS Repetitive Avalanche Energy 1 Single Pulse Avalanche Energy 4 5 16 mj STATIC ELECTRICAL CHARACTERISTICS Symbol Characteristic / Test Conditions BS Drain-Source Breakdown Voltage ( = V, = 25µA) 5 R DS(on) Drain-Source On-State Resistance 2 ( = 1V, = 23A).1 Ohms SS Zero Gate Voltage Drain Current ( = 5V, = V) Zero Gate Voltage Drain Current ( = 4V, = V, T C = 125 C) 25 1 µa I GSS Gate-Source Leakage Current ( = ±3V, = V) ±1 na (th) Gate Threshold Voltage ( =, = 2.5mA) 3 5 CAUTION: These Devices are Sensitive to Electrostatic Discharge. Proper Handling Procedures Should Be Followed.

DYNAMIC CHARACTERISTICS Symbol Characteristic C iss Input Capacitance C oss Output Capacitance C rss Reverse Transfer Capacitance Q g Total Gate Charge 3 Q gs Gate-Source Charge Q gd Gate-Drain ("Miller") Charge t d(on) Turn-on Delay Time t r Rise Time t d(off) Turn-off Delay Time Fall Time SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Symbol Characteristic / Test Conditions I S Continuous Source Current (Body Diode) I SM Pulsed Source Current 1 (Body Diode) V SD Diode Forward Voltage 2 ( = V, I S = -46A) Peak Diode Recovery dv / 5 dt dv / dt t rr Q rr I RRM THERMAL CHARACTERISTICS Symbol Characteristic R JC Junction to Case Junction to Ambient R JA.3 Turn-on Switching Energy 6 Turn-off Switching Energy Turn-on Switching Energy 6 Turn-off Switching Energy Reverse Recovery Time (I S = -46A, di / dt = 1A/µs) Reverse Recovery Charge (I S = -46A, di / dt = 1A/µs) Peak Recovery Current (I S = -46A, di / dt = 1A/µs) 1 Repetitive Rating: Pulse width limited by maximum junction temperature 2 Pulse Test: Pulse width < 38 µs, Duty Cycle < 2% 3 See MIL-STD-75 Method 3471 Test Conditions = V = 25V f= 1 MHz = 1V = 25V = 46A @ 25 C RESISTIVE SWITCHING =15V =25V =46A@ 25 C R G =.6 INDUCTIVE SWITCHING @ 25 C =333V, = 15V =46A, R G =5 INDUCTIVE SWITCHING @ 125 C =333V = 15V =46A, R G =5 APT Reserves the right to change, without notice, the specifications and inforation contained herein. APT51B2FLL_LFLL 436 895 pf 6 95 24 nc 5 11 15 25 ns 3 545 51 µj 845 595 46 184 1.3 15 T j = 25 C 28 T j = 125 C 6 T j = 25 C 2.28 T j = 125 C 6.41 T j = 25 C 15.7 T j = 125 C 23.6.25 4 V/ns ns µc C/W 4 Starting T j = +25 C, L = 1.51mH, R G =25, Peak I L = 46A 5 dv / dt numbers reflect the limitations of the test circuit rather than the device itself. I S - 46A di / dt 7A/µs V R 5V 15 C 6 Eon includes diode reverse recovery. See figures 18, 2..25.9.2.7.15.5 Note:.1.3 t 1.5.1.5 SINGLE PULSE t 2 Duty Factor D = t 1/t 2 Peak = P DM x Z JC + T C 1-5 1-4 1-3 1-2 1-1 1. RECTANGULAR PULSE DURATION (SECONDS) FIGURE 1, MAXIMUM EFFECTIVE TRANSIENT THERMAL IMPEDANCE, JUNCTION-TO-CASE vs PULSE DURATION

Typical Performance Curves Junction temp. ( C) RC MODEL.131.266F 12 1 15 &1V 8V 7.5V APT51B2FLL_LFLL 8 7V Power (watts).789.811.584f.796f 6 4 6.5V 6V.23.46F 2 5.5V Case temperature. ( C) FIGURE 2, TRANSIENT THERMAL IMPEDANCE MODEL 1 9 8 > (ON) x R DS (ON)MAX. 25µSEC. PULSE TEST @ <.5 % DUTY CYCLE 5 1 15 2 25 3 FIGURE 3, LOW VOLTAGE OUTPUT CHARACTERISTICS 1.2 1.15 NORMALIZED TO = 1V @ 23A 7 1.1 6 =1V 5 1.5 4 =2V 1. 3 2 = +125 C 1 = +25 C = -55 C.95.9 1 2 3 4 5 6 7 8 9 1 2 4 6 8, GATE-TO-SOURCE VOLTAGE (VOLTS), DRAIN CURRENT (AMPERES) FIGURE 4, TRANSFER CHARACTERISTICS FIGURE 5, R DS (ON) vs DRAIN CURRENT 5 1.15 4 3 2 1.1 1.5 1..95 1.9.85 25 5 75 1 125 15-5 -25 25 5 75 1 125 15 T C, CASE TEMPERATURE ( C), JUNCTION TEMPERATURE ( C) FIGURE 6, MAXIMUM DRAIN CURRENT vs CASE TEMPERATURE FIGURE 7, BREAKDOWN VOLTAGE vs TEMPERATURE 2.5 1.2 = 23A = 1V 1.1 2. 1.5 1..5 1..9.8.7..6-5 -25 25 5 75 1 125 15-5 -25 25 5 75 1 125 15, JUNCTION TEMPERATURE ( C) T C, CASE TEMPERATURE ( C) FIGURE 8, ON-RESISTANCE vs. TEMPERATURE FIGURE 9, THRESHOLD VOLTAGE vs TEMPERATURE

184 2, APT51B2FLL_LFLL 1 OPERATION HERE LIMITED BY R DS (ON) 1µS 1, Ciss 1mS 1, Coss 1 T C =+25 C =+15 C SINGLE PULSE 1mS 1 Crss 1 1 1 1 1 5 1 2 3 4 5 FIGURE 1, MAXIMUM SAFE OPERATING AREA FIGURE 11, CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 16 2 = 46A 1 12 8 =25V =1V =4V 1 =+15 C =+25 C 4 1 2 4 6 8 1 12 14.3.5.7.9 1.1 1.3 1.5 Q g, TOTAL GATE CHARGE (nc) V SD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) FIGURE 12, GATE CHARGES vs GATE-TO-SOURCE VOLTAGE FIGURE 13, SOURCE-DRAIN DIODE FORWARD VOLTAGE 8 7 6 5 4 3 2 1 15 12 9 t d(off) V = 33V L = 1µH t d(on) V = 33V L = 1µH t r 1 2 3 4 5 6 7 1 2 3 4 5 6 7 (A) (A) FIGURE 14, DELAY TIMES vs CURRENT FIGURE 15, RISE AND FALL TIMES vs CURRENT V = 33V L = 1µH E ON includes diode reverse recovery. = 33V I = 46A D T = 125 C 2 J L = 1µH E ON includes diode reverse recovery. 15 1 9 8 7 6 5 4 3 2 1 25 6 1 3 5 1 2 3 4 5 6 7 5 1 15 2 25 3 35 4 45 5 (A) R G, GATE RESISTANCE (Ohms) FIGURE 16, SWITCHING ENERGY vs CURRENT FIGURE 17, SWITCHING ENERGY VS. GATE RESISTANCE

APT51B2FLL_LFLL 1 % t d(on) Gate Voltage = 125 C 9% t d(off) Gate Voltage = 125 C t r Drain Voltage Drain Current 5 % Switching Energy 1 % 9% 5 % Drain Voltage 9% Switching Energy 1% Drain Current Figure 18, Turn-on Switching Waveforms and Definitions Figure 19, Turn-off Switching Waveforms and Definitions APT3DF6 G D.U.T. Figure 2, Inductive Switching Test Circuit T-MAX TM (B2) Package Outline TO-264 (L) Package Outline 5.31 (.29) 2.49 (.98) 16.26 (.64) 6.2 (.244) 5.21 (.25) 2.1 (.79) 2.5 (.87) 3.1 (.122) 3.48 (.137) 21.46 (.845) 6.2 (.244) 26.49 (1.43).79 (.31) 2.32 (.8) 4.5 (.177) Max. 1.4 (.55) 3.12 (.123) 2.13 (.84) Gate Drain Source 21.39 (.842) 2.69 (.16) 2.29 (.9) 2.69 (.16) Gate Drain Source.84 (.33) 1.3 (.51) 2.59 (.12) 5.45 (.215) BSC 3. (.118) 3.18 (.125) 2-Plcs. 5.45 (.215) BSC These dimensions are equal to the TO-247 without the mounting hole. 2-Plcs. Dimensions in Millimeters and (Inches) Dimensions in Millimeters and (Inches) APTs products are covered by one or more of U.S.patents 4,895,81 5,45,93 5,89,434 5,182,234 5,19,522 5,262,336 6,53,786 5,256,583 4,748,13 5,283,22 5,231,474 5,434,95 5,528,58 and foreign patents. US and Foreign patents pending. All Rights Reserved.