SEAMS DUE TO MULTIPLE OUTPUT CCDS

Similar documents
AND9100/D. Paralleling of IGBTs APPLICATION NOTE. Isothermal point

AND8285/D. NCP1521B Adjustable Output Voltage Step Down Converter Simulation Procedure SIMULATION NOTE

AND8388/D. Input Dynamic Range Extension of the BelaSigna 300 Series

EVALUATION BOARD FOR STK N, 120N, 140N. Phenol 1-layer Board) Figure 2. STK NGEVB Figure 3. STK NGEVB Figure 4.

PCS2I2309NZ. 3.3 V 1:9 Clock Buffer

AND8450/D. NCV7680 LED Driver Linear Regulator Performance APPLICATION NOTE

1. DEFINE THE SPECIFICATION 2. SELECT A TOPOLOGY

NSVEMD4DXV6T5G. Dual Bias Resistor Transistors. NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network

Is Now Part of To learn more about ON Semiconductor, please visit our website at

FJP13007 High Voltage Fast-Switching NPN Power Transistor

Is Now Part of To learn more about ON Semiconductor, please visit our website at

NUF8401MNT4G. 8-Channel EMI Filter with Integrated ESD Protection

Low Capacitance Transient Voltage Suppressors / ESD Protectors CM QG/D. Features

MUN5216DW1, NSBC143TDXV6. Dual NPN Bias Resistor Transistors R1 = 4.7 k, R2 = k. NPN Transistors with Monolithic Bias Resistor Network

PCS2P2309/D. 3.3V 1:9 Clock Buffer. Functional Description. Features. Block Diagram

NTHD4502NT1G. Power MOSFET. 30 V, 3.9 A, Dual N Channel ChipFET

Is Now Part of To learn more about ON Semiconductor, please visit our website at

Is Now Part of To learn more about ON Semiconductor, please visit our website at

MBD110DWT1G MBD330DWT1G. Dual Schottky Barrier Diodes

PIN CONNECTIONS MAXIMUM RATINGS (T J = 25 C unless otherwise noted) SC 75 (3 Leads) Parameter Symbol Value Unit Drain to Source Voltage V DSS 30 V

PZTA92T1. High Voltage Transistor. PNP Silicon SOT 223 PACKAGE PNP SILICON HIGH VOLTAGE TRANSISTOR SURFACE MOUNT

NTNS3164NZT5G. Small Signal MOSFET. 20 V, 361 ma, Single N Channel, SOT 883 (XDFN3) 1.0 x 0.6 x 0.4 mm Package

Parameter Symbol Conditions Ratings Unit

MBRA320T3G Surface Mount Schottky Power Rectifier

MPSL51. Amplifier Transistor PNP Silicon MAXIMUM RATINGS. THERMAL CHARACTERISTICS

NSR0340V2T1/D. Schottky Barrier Diode 40 VOLT SCHOTTKY BARRIER DIODE

NUF4401MNT1G. 4-Channel EMI Filter with Integrated ESD Protection

MRA4003T3G Series, NRVA4003T3G Series. Surface Mount Standard Recovery Power Rectifier. SMA Power Surface Mount Package

NVLJD4007NZTBG. Small Signal MOSFET. 30 V, 245 ma, Dual, N Channel, Gate ESD Protection, 2x2 WDFN Package

TIP120 / TIP121 / TIP122 NPN Epitaxial Darlington Transistor

BD809 (NPN), BD810 (PNP) Plastic High Power Silicon Transistor 10 AMPERE POWER TRANSISTORS 80 VOLTS 90 WATTS

AND9006/D. Using Transmission Line Pulse Measurements to Understand Protection Product Characteristics APPLICATION NOTE

MURS320T3G, SURS8320T3G, MURS340T3G, SURS8340T3G, MURS360T3G, SURS8360T3G. Surface Mount Ultrafast Power Rectifiers

NTNUS3171PZ. Small Signal MOSFET. 20 V, 200 ma, Single P Channel, 1.0 x 0.6 mm SOT 1123 Package

COLOR FILTER PATTERNS

BD809 (NPN), BD810 (PNP) Plastic High Power Silicon Transistors 10 AMPERE POWER TRANSISTORS 80 VOLTS 90 WATTS

ASM3P2669/D. Peak EMI Reducing Solution. Features. Product Description. Application. Block Diagram

MBR20200CT. Switch mode Power Rectifier. Dual Schottky Rectifier SCHOTTKY BARRIER RECTIFIER 20 AMPERES, 200 VOLTS

MURS120T3G Series, SURS8120T3G Series. Surface Mount Ultrafast Power Rectifiers

Is Now Part of To learn more about ON Semiconductor, please visit our website at

Single stage LNA for GPS Using the MCH4009 Application Note

NSBC114EDP6T5G Series. Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network

AND9097/D. Ayre SA3291 Getting Started Guide APPLICATION NOTE

NTK3139P. Power MOSFET. 20 V, 780 ma, Single P Channel with ESD Protection, SOT 723

CAX803, CAX809, CAX Pin Microprocessor Power Supply Supervisors

CAT5126. One time Digital 32 tap Potentiometer (POT)

KSC2383 NPN Epitaxial Silicon Transistor

SMA3109. MMIC Amplifier, 3V, 16mA, 0.1 to 3.6GHz, MCPH6. Features. Specifications. Low current. : ICC=16mA typ. Absolute Maximum Ratings at Ta=25 C

MBR130LSFT1G. Surface Mount Schottky Power Rectifier. Plastic SOD 123 Package SCHOTTKY BARRIER RECTIFIER 1.0 AMPERES, 30 VOLTS

MMBFU310LT1G. JFET Transistor. N Channel. These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant. Features.

434MHz LNA for RKE Using the 2SC5245A Application Note

BAV103 High Voltage, General Purpose Diode

MMSD301T1G SMMSD301T1G, MMSD701T1G SMMSD701T1G, SOD-123 Schottky Barrier Diodes

Is Now Part of To learn more about ON Semiconductor, please visit our website at

NTJD1155LT1G. Power MOSFET. 8 V, 1.3 A, High Side Load Switch with Level Shift, P Channel SC 88

EMC2DXV5T1G, EMC3DXV5T1G, EMC4DXV5T1G, EMC5DXV5T1G. Dual Common Base-Collector Bias Resistor Transistors

NBSG86ABAEVB. NBSG86A Evaluation Board User's Manual EVAL BOARD USER S MANUAL.

P2042A LCD Panel EMI Reduction IC

MJL21195 (PNP), MJL21196 (NPN) Silicon Power Transistors 16 A COMPLEMENTARY SILICON POWER TRANSISTORS 250 V, 200 W

NSS1C201MZ4, NSV1C201MZ4 100 V, 2.0 A, Low V CE(sat) NPN Transistor

MJE15032 (NPN), MJE15033 (PNP) Complementary Silicon Plastic Power Transistors 8.0 AMPERES POWER TRANSISTORS COMPLEMENTARY SILICON 250 VOLTS, 50 WATTS

KSH122 / KSH122I NPN Silicon Darlington Transistor

NUF6105FCT1G. 6-Channel EMI Filter with Integrated ESD Protection

2N6667, 2N6668. Darlington Silicon Power Transistors PNP SILICON DARLINGTON POWER TRANSISTORS 10 A, V, 65 W

SMA3107. MMIC Amplifier, 3V, 6mA, 0.1 to 2.8GHz, MCPH6. Features. Specifications

P2I2305NZ. 3.3V 1:5 Clock Buffer

NUF6400MNTBG. 6-Channel EMI Filter with Integrated ESD Protection

NUF8001MUT2G. 8-Channel EMI Filter with Integrated ESD Protection

Is Now Part of To learn more about ON Semiconductor, please visit our website at

J109 / MMBFJ108 N-Channel Switch

CMPWR ma SmartOR Regulator with V AUX Switch

NSS1C201L, NSV1C201L. 100 V, 3.0 A, Low V CE(sat) NPN Transistor. 100 VOLTS, 3.0 AMPS NPN LOW V CE(sat) TRANSISTOR

2N6400 Series. Silicon Controlled Rectifiers. Reverse Blocking Thyristors. SCRs 16 AMPERES RMS 50 thru 800 VOLTS

NTK3043N. Power MOSFET. 20 V, 285 ma, N Channel with ESD Protection, SOT 723

MJD44H11 (NPN) MJD45H11 (PNP)

MJ21195G - PNP MJ21196G - NPN. Silicon Power Transistors 16 AMPERES COMPLEMENTARY SILICON- POWER TRANSISTORS 250 VOLTS, 250 WATTS

SS13FL, SS14FL. Surface Mount Schottky Barrier Rectifier

Is Now Part of To learn more about ON Semiconductor, please visit our website at

LM339S, LM2901S. Single Supply Quad Comparators

S1AFL - S1MFL. Surface General-Purpose Rectifier

NTTFS3A08PZTWG. Power MOSFET 20 V, 15 A, Single P Channel, 8FL

MBRA320T3G Surface Mount Schottky Power Rectifier

NCP786L. Wide Input Voltage Range 5 ma Ultra-Low Iq, High PSRR Linear Regulator with Adjustable Output Voltage

2N5194G, 2N5195G. Silicon PNP Power Transistors 4 AMPERE POWER TRANSISTORS PNP SILICON VOLTS

MMSZ5221BT1 Series. Zener Voltage Regulators. 500 mw SOD 123 Surface Mount

P3P85R01A. 3.3V, 75 MHz to 200 MHz LVCMOS TIMING SAFE Peak EMI Reduction Device

NJT4031N, NJV4031NT1G, NJT4031NT3G. Bipolar Power Transistors. NPN Silicon NPN TRANSISTOR 3.0 AMPERES 40 VOLTS, 2.0 WATTS

Is Now Part of To learn more about ON Semiconductor, please visit our website at

KA431 / KA431A / KA431L Programmable Shunt Regulator

FGH12040WD 1200 V, 40 A Field Stop Trench IGBT

PNP Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

74VHC14 Hex Schmitt Inverter

MJ PNP MJ NPN. Silicon Power Transistors 16 AMP COMPLEMENTARY SILICON POWER TRANSISTORS 250 VOLTS, 250 WATTS

General Description. Applications. Power management Load switch Q2 3 5 Q1

NTA4001N, NVA4001N. Small Signal MOSFET. 20 V, 238 ma, Single, N Channel, Gate ESD Protection, SC 75

Is Now Part of To learn more about ON Semiconductor, please visit our website at

Is Now Part of To learn more about ON Semiconductor, please visit our website at

NSV2029M3T5G. PNP Silicon General Purpose Amplifier Transistor PNP GENERAL PURPOSE AMPLIFIER TRANSISTORS SURFACE MOUNT

MJW21195 (PNP) MJW21196 (NPN) Silicon Power Transistors 16 AMPERES COMPLEMENTARY SILICON POWER TRANSISTORS 250 VOLTS, 200 WATTS

BCP53 Series. PNP Silicon Epitaxial Transistors MEDIUM POWER HIGH CURRENT SURFACE MOUNT PNP TRANSISTORS

Transcription:

Seam Correction for Sensors with Multiple Outputs Introduction Image sensor manufacturers are continually working to meet their customers demands for ever-higher frame rates in their cameras. To meet this need, ON Semiconductor produces image sensors with multiple outputs, currently making sensors with two and four outputs. Increasing the number of CCD output amplifiers, combined with splitting the vertical and/or horizontal registers, allows higher frame rates while still keeping the fundamental image quality unchanged. While ON Semiconductor image sensors have very good correlation of output characteristics between the individual outputs of its multi-output sensors, there will still be small differences between the outputs on the same image sensor. APPLICATION NOTE These are due to small differences in lithography, doping or other aspects of the semiconductor manufacturing process. When the images from such a sensor are reconstructed, these small differences, if left uncompensated, may be noticeable at the boundaries where the channels meet producing a seam in the image. In some applications these seams may need correction above what can be provided by electronic gain and offset. This application note explores the theory behind these seam errors and provides techniques to correct them. SEAMS DUE TO MULTIPLE OUTPUT CCDS Linear Detector Output When characterizing the complete signal path of a CCD camera, the CCD output signal for a given pixel, expressed in ADU (Analog to Digital Unit as output from the Analog to Digital Converter, ADC), is related to the detected light by this formula: OutSignal(l) off G I (eq. 1) Where: I the input signal can be either expressed in electrons per pixels or relative illumination. off black level offset, expressed in ADU. G the gain expressed in ADU per electrons. The CCD exhibits a linear behavior with respect to the incoming light. This application note assumes that this basic linear behavior is not jeopardized by other factors (such as temperature, electronic instability, etc.). The camera should have a sound electronic design. For a CCD with N (1, 2, 3, 4 ) outputs where k = 1 N, each output of the CCD device can be expressed as: With multiple output CCDs, each output will have very small lithographic and process mismatches and will be slightly different from the other outputs, therefore: CCD Outputs Do Not Have the Same Offset Level (off k ) CCD Outputs Do Not Have the Same Gain (G k ) If identical signals appear in areas of the sensors that are read through different outputs, the results in the image will be slightly different. This leads to areas of image non uniformity. Since the number of outputs (N) is usually equal to 2 or 4, the overall image will exhibit either 2 or 4 areas having brightness and contrast differences. The seams effect refers to the boundaries where the areas meet. The image of Figure 1 shows the seam effect (located vertically in the middle of the image) provided by a dual output CCD. All off k are identical, but with different gains: G 2 / G 1 =.95 NOTE: The seam effect is not as visible in image areas where there is a large amount of detail; it is more visible in uniform image sections, such as the sky. OutSignal(l) k off k G k I (eq. 2) Semiconductor Components Industries, LLC, 214 October, 214 Rev. 2 1 Publication Order Number: AND9193/D

Figure 1. Dual Output CCD (Left/Right) Image with No Seam Correction How to Correct this Effect Before any correction can be applied all output of the CCD must be characterized. The output response, off k and G 2 for each detector will need to be measured. This paper presents two techniques that could be used to do this. In each case the method should be performed on all outputs of the detector. The first method requires only a flat field illumination source and the ability to sweep the integration time of the camera. 1. Place the CCD detector in front of a constant and flat illumination source. 2. Start with the integration time set such that the CCD output is zero. 3. Incrementally increasing the integration time and record an image at each increment. 4. When the output reaches the saturation collect the data from the stored images and plot as shown in Figure 2. NOTES: The number of frames captured will determine the accuracy of the results. Exposure time and the light source must be very stable (.1%) during the measurement. Best Linear Fit Camera Output (ADU) Variable Exposure Time (sec) Proportionnal to Captured Light Figure 2. Detector CCD Output vs. Exposure Time 2

The second requires a variable intensity flat field illumination source with a range of no light to detector saturation. Place the detector in front of the illumination source. Records various frames with a constant exposure time by only changing the illumination level. 1. This requires the relative amount of light to be known and to be stable (.1%) during the measurements. 2. Knowledge of the absolute output of the light source is not necessary for this method. 3. Relative illumination can be used without any impact on the final result. Collect the data from the saved images at the completion of all captures, and plot as in Figure 3. NOTE: This method is much closer to the usual operational condition and could, therefore, be more representative. It also eliminates any artifacts that may be induced by the cameras integration control circuitry. Best Linear Fit Camera Output (ADU) Variable Amount of Light with Fixed Exposure Time Figure 3. Detector CCD Output vs. Illumination Sweep and Constant Exposure Time To confirm that the measured results are stable and representative, it is suggested that the process of collecting results is repeated several times. 5 1 3 4 1 3 Det. Output ADUs 3 1 3 2 1 3 1 1 3 Output 1 Output 2 Output 3 Output 4 5 1 15 2 Figure 4. The 4 CCD Output Signal vs. Different Illumination Levels 3

Correction for Linear CCD Outputs With linear output CCD response, the correction is straightforward. The goal is to make all outputs (1 k) behave the same by matching their output characteristics to the channel that best matches the expected performance. This translates mathematically to: off 1 G 1 I off k sh k H k G k I (eq. 3) Where: off k are the offsets at zero illumination. G k is the slope for each output. Here, off 1, G 1, off k and G k are known, because of the previous measurements and H k and sh k can be calculated by: sh k off 1 off k (eq. 4) H k Gk G 1 Correction for Non-linear CCD Outputs As the detector and its analog electronic signal path do not have perfect linear characteristics, some applications need to take this into account. This is especially the case at low lights levels and also levels close to the sensor saturation. The output signal can be modeled as a polynomial function: OutSignal(I) k off k G k 1 I Gk 2 I2 G k 3 I3 (eq. 5) Which can be generalized to: OutSignal(I) k off k i m i 1 Gk i I i (eq. 6) G k i are non-linear terms, and the output signal is being modeled to a polynomial function. m, the degree of the polynomial can be a figure up to the 7 9 th degree but as m becomes larger more processing is required and also the accuracy of the measurements may not be sufficient to justify this effort. The more linear the CCD output, the closer to zero are the G k i terms. G k i are regarded as constant terms in this equation. However they can also be affected by changes in temperature T (or other parameters): OutSignal(I, T) k off k (T) i m i 1 Gk i (T) Ii (eq. 7) Note that other factors contributing to the non-linear behavior of a CCD output amplifier and its external signal path such as temperature stabilization issues, jitter in CDS timing, poor linearity near CCD saturation, and insufficient dark pixel used for black level measurement will all have an impact on system performance. Care should be taken to minimize any variation of the output linearity caused by them given the engineering constraints of the camera design. This approach can be difficult to implement in a practical system. A more experimental approach follows. Once CCD output behavior is stable, the correction process can be put into effect. For reference the Figure 5 illustrates a simulated non-linear output characteristic from a CCD and its external signal path as measured at the ADC. 1. Non-linear Detector Output Behavior.8 Det. Output ADUs.6.4.2 5 1 15 Figure 5. Simulated Non-linear CCD/Detector Output Behavior The measurement of the CCD output and its respective readout chain linearity is best achieved using automated tools and software. The system used must be able to illuminate the CCD with different lights levels, perform the readout and compute automatically the final digitized signal coming from a small window inside the image. This measurement allows N number of, OutputDect i discrete values to be retrieved from the CCD output and a plot of the output versus relative illumination to be made. The offset for no illumination has been removed to simplify computations. 4

The final output signal needs to be linear: Line (illumination) A illumination (eq. 8) Each previously measured point (i = 1 to N) is then matched according to the data shown in Figure 6, using a discrete or point to point approach: Line i A illumination i (eq. 9) 1. Linearized Output vs. Non-linear Output.8 Det. Output ADUs.6.4.2 5 1 15 Raw Output Linearized Output Figure 6. Non-linear Output to Be Corrected The correction factors (Fact_corr i ) can be now be computed for each measured point, by using Equation 1: A illuminationi Fact_corr i (eq. 1) OutputDect i The A factor is chosen to minimize the Fact_corr i. This is done by minimizing the Error figure in Equation 11: Error N i 1 1 Fact_corr i 2 (eq. 11) The Error figure should be minimized using iteratively, or with a least square straight fit algorithm. 8 Correction Factors 6 Correction Factor 4 2 5 1 15 Figure 7. Fact_Corr i vs. Relative Illumination 5

As can be seen in Figure 7, Fact_corr i can be large at small illuminations, so measurements have to be accurate in this range. The Fact_corr i, a discrete set of numbers, can also be fitted (using the least square method) to make a continuous function. This will help to smooth the data, and it will provide a continuous Fact_corr(x) function figure whatever the x illumination level. The linearized corrected signal is then: Linearized_OutputDect(illumination) Fact_corr(illumination) OutputDect(illumination) (eq. 12) Once each CCD output is linearized, the final correction consists in matching all detector channels by setting Gain and Offset corrections with respect to the first (or one of the other) CCD outputs. This is an arbitrary choice. This final correction stage is exactly the same process as described earlier (See Correction for Linear CCD Outputs). Color Images For color images, the same method applies. Fortunately, due to the color Bayer filters spread throughout the whole CCD surface; all the green, blue and red pixels will have the same linear/non-linear behavior versus illumination: All pixels are going through the same output amplifier. The green pixels can be used to perform the linearity measurement and follow the process as previously presented in this document. Summary of Steps Required to Correct Seam Artifacts 1. Measure CCD output signal levels (including its signal path electronics) versus illumination, for each output. For color devices, select the green pixels, discarding the red and blue pixels. 2. Verify that measurements are stable and not temperature dependent as consistent with your design specification. 3. Measurements need to be performed for each device; factory tooling should to be set up to perform measurements of each device as explained in Step 1. 4. If the plots are sufficiently linear for your application, only offset and gain correction are required, store these numbers into camera memory and apply them after digitization. 5. If the plots are not sufficiently linear for your application, the outputs will need to be linearized prior to offset and gain correction being applied. All the figures need to be stored inside camera memory and applied in real time after digitization. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 USA Phone: 33 675 2175 or 8 344 386 Toll Free USA/Canada Fax: 33 675 2176 or 8 344 3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 8 282 9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 79 291 Japan Customer Focus Center Phone: 81 3 5817 15 6 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative AND9193/D