An Accelerated On-Wafer Test to Improve Long- Term Reliability of a 0.25 µm PHEMT Process Wayne Struble, Jason Barrett, Nishant Yamujala MACOM January-4-17 September 28-30 2016, Pensacola Beach, Florida 1
Motivation RF HTOL (High temperature operating life) is a key reliability metric for a semiconductor wafer process, especially for RF and Microwave Power Amplifier applications. Conventional testing techniques adequate for product qualification but not for process development. Timelines are aggressive in the process development stage. Need something faster. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 2
The 0.25 µm phemt process at MACOM A 0.25 µm AlGaAs/InGaAs HEMT with an optically defined gate electrode. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 3
In-Situ Output Power (dbm) Accelerated Stress Testing and Reliability Power droop 25.5 Initial Reliability Issues Device Walkout F=3.5GHz, Vds=8v, Idsq=87.5mA/mm, Igs=1mA/mm, Tj=140 o C Vgs held constant during RF HTOL 25.0 24.5 24.0 0.0 0.1 1.0 10.0 100.0 1000.0 Stress Time (Hours) www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 4
Drain Current (ma/mm) Gate Current (ma/mm) Accelerated Stress Testing and Reliability Other Reliability Issues Pinchoff Shift Breakdown Shift 250 200 PH6 400mm phemt Vds=5v Drain Current Pre and Post RF Stress ROOM TEMP DOWN POINT DATA 1.0E+00 1.0E-01 PH6 400mm phemt Breakdown Current Pre and Post RF Stress Vgs=-3v ROOM TEMP DOWN POINT DATA 10v shift in breakdown voltage 150 Ids (0 hours) Ids (20 hours) Ids (130 hours) 1.0E-02 1.0E-03 100 50-0.25v shift in pinchoff voltage 1.0E-04 1.0E-05 0 hours 138 hours 0-1.6-1.4-1.2-1.0-0.8-0.6-0.4-0.2 0.0 Gate Voltage (Volts) 1.0E-06 0.0 5.0 10.0 15.0 20.0 25.0 Drain-Gate Voltage (Volts) www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 5
Problems With Current Reliability Techniques Wafer needs to be diced and die need to be placed in sample boards. Samples are then tested in a RF HTOL system like the commercially available Accel RF System. If the reliability issues are known, process can be tweaked to try and fix the issues. Need techniques to give faster feedback to the fab so they can know if the fixes are working. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 6
The On-Wafer RF HTOL Method Power droop is measured under a worse-case RF HTOL scenario in terms of bias, load-line, junction temperature, and power compression. For the 0.25mm GaAs/AlGaAs power phemt process, the worsecase operating condition chosen was Vds=9v, max Pout load-line, 150 o C junction temperature, and forward gate current of 1mA/mm under RF drive (~3dB compressed, or hard saturation). Python is used to log the in-situ power level at regular intervals. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 7
Stand Setup www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 8
Test Methodology DC and RF Characterization RF Stress the Device for 24 hours or less Re-Perform DC and RF Characterization The DC characterization tests include DC-IV curves, pichoff and R-On measurements, Gate diode curves and Pin-Pout tests. The tests are performed at room temperature. All the pre and post stress device characterization tests written in Python. After initial testing, the temperature of the thermal check is raised to correspond to a certain junction temperature. The device is biased and RF input is applied till the device is pushed into compression and the forward gate current is at about 1mA/mm. The stress is started. Python is used to periodically log the output power, gate and drain current to a file. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 9
Output Power (dbm) & Gain (db) Power Added Efficiency (%) Accelerated Stress Testing and Reliability Results Room temperature Pout versus Pin down-point measurements (at fixed Vgs) after RF HTOL shows an initial INCREASE in output power! PH6 400mm phemt Pre and Post RF Stress (F=3.5GHz, Vds=8v, Idsq=87.5mA/mm, Igs=1mA/mm, Tj=140 o C) 27.5 80 25.0 ROOM TEMP DOWN POINT DATA 70 22.5 20.0 17.5 15.0 60 50 40 30 Pout (0 hours) Pout (20 hours) Pout (130 hours) Gain (0 hours) Gain (20 hours) Gain (130 hours) PAE (0 hours) PAE (20 hours) PAE (130 hours) 12.5 20 10.0 7.5 ~Pin for stress -8-6 -4-2 0 2 4 6 8 10 12 14 Input Power (dbm) 10 0 www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 10
Factors Affecting Power Droop Pinchoff shift Affects short term power droop in first 1-20 hours Breakdown shift affects short term power droop in first 1-20 hours Affects long term power slope after 20 hours? Device geometry affects long term power droop slope after 20 hours? www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 11
Sources of Issues Existing research confirms that hot holes are the underlying cause for the mechanism that caused the initial pinch-off shift of devices. The hypothesis is that hot holes are swept towards the gate and become lodged in the nitride in the region near the gate edge, referred to as the un-gated recess region, where their presence results in an increase of positive charge that enhances the surface of the semiconductor resulting in a more negative pinch-off voltage. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 12
Fixes Made To Address Issues Fix the etch damage by addressing the pre-gate metal deposition step. Thermal anneal step incorporated prior to gate metal deposition. Address the InGaP etch stop removal process. Finally, address the device geometry. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 13
Drain Current (ma/mm) Accelerated Stress Testing and Reliability Results of Applying the Fixes (Pincoff Shift) PH6 400mm phemt Vds=5v Drain Current Pre and Post RF Stress (with pre-nitride gate anneal) 250 200 ROOM TEMP DOWN POINT DATA 150 100 50 No Shift!! Ids (0 hours) Ids (68 hours) Ids (112 hours) 0-1.6-1.4-1.2-1.0-0.8-0.6-0.4-0.2 0.0 Gate Voltage (Volts) www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 14
Gate Current (ma/mm) Pout (dbm) Accelerated Stress Testing and Reliability Breakdown 1.0E+00 1.0E-01 1.0E-02 1.0E-03 1.0E-04 1.0E-05 Other Results of Applying the Fixes PH6 400mm phemt Vgs=-3v Breakdown Current Pre and Post RF Stress (with H 2 O 2 :HCl:H 2 O) ROOM TEMP DOWN POINT DATA 0 hours 68 hours -0.25v 112 shift hoursin pinchoff voltage Droop 30 28 26 24 22 20 18 16 14 12 Pout vs. Stress Time F=1GHz Vds=9v Idsq=87.5mA/mm Igs=1mA/mm Tjunc=150 o C 10v shift in breakdown voltage Pout for DUT 531702 Pout for DUT 531703 Pout for DUT 531705 Pout for DUT 531905 Pout for DUT 531903 Pout for DUT 531902 Pout for DUT 531901 1.0E-06 0.0 5.0 10.0 15.0 20.0 25.0 Drain-Gate Voltage (Volts) 10 0 100 200 300 400 500 600 700 800 900 1000 1100 Stress Time (hrs) www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 15
Motivation For An Even Faster Technique The technique outlined above tests only one device at a time. There can be variation across a wafer. Need to measure multiple devices across a wafer. Need technique that allows us to measure hundreds of devices. Process engineers can come up with 3-4 wafers in a lot, each of which has a different process variation. This allows us to check if the process fixes are truly working. The short-term stress test must mimic the on-wafer RF HTOL test in terms of affecting appropriate device walkout. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 16
The Short Term RF-Stress Technique Through trial and error, a new stress technique was discovered. Steps below: (1) Measure the parameters such as pinchoff voltage, on resistance, IV curves, breakdown curves, and gate diode IV curves at room temperature. (2) Set the drain voltage to 11.5 V and adjust the gate voltage till a drain current of about 50 ma is obtained. (3) Stress the device under RF drive of about -18.3 dbm for 10 seconds. This should drive the device into hard saturation. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 17
The Short Term RF Stress Technique Continued (4) Turn off the RF generator and readjust the gate voltage to obtain a drain current of 50 ma. (5) Repeat the third step. (6) Repeat steps 3 5, five times. (7) Re-measure the key DC parameters outlined in step1. (8) Move onto the next device on the wafer. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 18
More On The Technique The method is fully automated using Python. Once the wafer is aligned, and the wafer map provided, the program steps across the wafer and measures all the devices on it. The walkout characteristics are comparable to stressing the device according to the RF HTOL technique outlined. It was discovered that after the third RF power blast, the device walkout phenomenon stops. Five RF sweeps were still applied for devices that don t exhibit walkout after three sweeps. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 19
Results Same Walkout Affected RF HTOL New Short Term RF Test www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 20
Results Pinchoff Across Wafers www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 21
Results Breakdown Across Wafers www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 22
Conclusion Two techniques presented to quickly glean if reliability issues present in a process. The techniques presented increase rate of learning which can be used to fix any issues with a process. This technique is not meant to replace conventional RF HTOL techniques, but is meant to complement them. Ideal scenario involves using the techniques outlined in this paper to characterize and fix process issues, and then hand over the process to the reliability group for a more thorough qualification process. www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 23
Questions? www.ieee-astr.org September 28-30 2016, Pensacola Beach, Florida 24