Decoupling Technique for Reducing Sensitivity of Differential Pairs to Power-Supply-Induced Jitter

Decoupling Technique for Reducing Sensitivity of Differential Pairs to Power-Supply-Induced Jitter John McNeill Vladimir Zlatkovic David Bowler Lawrence M. DeVito ANALOG DEVICES

Application Presentation Overview Ring Oscillator VCO Problem: Supply influence on VCO frequency Stage delay Bias current Supply noise Coupling mechanisms: Low frequency vs. High Frequency Decoupling Technique Analysis Results Simulated Measured Summary

TDATA TCLK TRANSMIT END Application Serial data transmission clock recovery RECEIVE END CLOCK RECOVERY Vin RCLK RDATA Vin RCLK RDATA

PLL Clock Recovery Vin PHASE DETECTOR D Q RDATA RETIMED DATA Vin LOOP FILTER VOLTAGE CONTROLLED OSCILLATOR RCLK RECOVERED CLOCK RCLK RCLK "LATE" RCLK "EAY" VCO output is recovered clock Decision circuit samples Vin at clock transitions Low bit error rate requires low jitter VCO output

Ring Oscillator VCO VCO frequency expression: f VCO = Low jitter: Prevent undesired variation in delay t D Random noise (thermal noise) Interference: Power supply coupling 1 2" N " t D NUMBER OF STAGES STAGE DELAY

Applications Requiring Low Jitter VCO Microprocessor Clock Synthesis Multiply lower off-chip frequency to higher frequency clock on-chip Jitter reduces timing margin Oversampled data conversion Multiply sample-rate clock for oversampling Jitter produces artifacts in frequency domain Require low jitter clock in mixed signal IC environment

Ring VCO: Delay Stage Examples VCC VDD + VO - + VI - Q2 Q3 + VO - + VI - M2 M3 IEE ISS VB Q1 VB M1 VEE VSS Bipolar CMOS Problem: Differential pair delay influenced by bias current I EE, I SS

Delay Dependence on Bias Current SUPPLY + NOISE DELAY STAGE VCC f T Vn + VI - Q2 Q3 IEE Q1 VB VEE Δ Supply voltage (V n ) Δ Bias current I EE Δ Transistor f T Δ Differential pair delay I BIAS

Mechanisms of Bias Current Variation Q1 collector: SUPPLY + NOISE PREVIOUS STAGE DELAY STAGE derived from V CC Q1 base, emitter: VCC referenced to V EE Bias device Q1 Vn Q2 Q3 sees all of supply IEE + in variation v n Need to minimize resulting bias VEE VB Q1 current variation i n

Bias Current Variation: Low Frequency Bipolar: Base with modulation V CE I C CMOS: Channel length modulation V DS I D Solution: Cascode Increases output impedance Good supply rejection at DC, low frequencies SUPPLY + NOISE DELAY STAGE Vn VCC + VI - VCASC VB VEE Q4 Q1 Q2 Q3 IEE

Bias Current Variation: High Frequency Capacitive coupling: SUPPLY + NOISE PREVIOUS STAGE DELAY STAGE Bipolar: C jc, C js VCC CMOS: C gd, C db Vn Q2 Q3 Both see all of supply variation v n VEE Cjc VB IEE + in Q1 Cjs

Analysis: High Frequency Supply noise to bias variation transfer function " % ' # sr e C s +1& i n 1 = sc s $ v n Cs Vn re in Cjc VB Q2 Q3 Q1 Cjs r e small signal resistance "looking into" Q1, Q2 emitters i n v n C s = C js + C jc f

Process: 5-GHz-f T D.I. f OSC = 155 MHz V CC = 5V v n = 200mV p-p I EE = 100µA Simulated Results: Current i n [µa p-p] 10 Maximum p-p variation: 30µA 1 10 100 1000 30% of bias I EE! v n FREQUENCY [MHz]

Simulated Results: Jitter P-P JITTER (% UNIT INTERVAL) 1 % ORIGINAL WITH DECOUPLING NETWORK 0.1 % 100MHz 1GHz RIPPLE FREQUENCY Figure 5.13. Exceeds system specification: 1% U.I. jitter

Bias Current Variation: High Frequency Not fixed by cascode! SUPPLY + NOISE PREVIOUS STAGE DELAY STAGE Just moves problem to C jc, C js of cascoding device VCC Vn Q2 Q3 IEE + in Full supply noise v n must appear across some capacitance! VEE VCASC VB Cjc Q4 Q1 Cjs

Decoupling Technique Add RC network in series with bias current VCC Provide path for i n around differential pair Same voltage headroom cost as cascode + VI - Q1 Q2 RBP Q3 IEE + in CBP VB VEE

Analysis Supply noise v n to bias variation i n transfer function " i n 1 = sc s $ v n # ( )( C s +C BP ) +1 s r e + R BP % ' & Vn CBP in re RBP Cs Improved by factor " r e %" C s % $ ' $ ' # r e + R BP &# C s +C BP & i n v n Can improve with R BP or C BP Allows optimization of headroom, area tradeoff f

R BP = 10 kω C BP = 2pF I EE = 100µA Simulated Results: Current i n [µa p-p] Maximum p-p variation: 1.5µA 10 Improved by 20X 1 10 100 1000 v n FREQUENCY [MHz]

Simulated Results: Jitter P-P JITTER (% UNIT INTERVAL) 1 % ORIGINAL WITH DECOUPLING NETWORK 0.1 % 100MHz 1GHz RIPPLE FREQUENCY Figure 5.13. Within system specification: 1% U.I. jitter

Measured Results: Test Configuration DATA SOURCE D.U.T. TCLK Vtrig TRIG TDATA RCLK RDATA Vin VERT VCC VEE TEK 11801C Vn Inject supply noise on V EE

Measured Results: Example With Decoupling Network σ = 18ps rms Decoupling Network Removed σ = 119ps rms

σ [ps rms] Measured Results 300 200 Decoupling Network Removed 100 0 1 10 100 1000 With Decoupling Network v n FREQUENCY [MHz] f OSC = 155MHz

Extension: g m -C Quadrature CCO Analogous requirement: Supply immunity of oscillator phase Tewksbury et. al., "A 480MHz variable rate QPSK demodulator ", ISSCC97, pp. 86-87 IEEE

Summary Decoupling network reduces sensitivity of differential stage delay to supply variation Need to address both low frequency and high frequency coupling paths RC network improves supply noise immunity of bias current Useful in other mixed signal applications

Acknowledgments Analog Devices Graduate Fellowship Evaluation support (Bob Surette) National Science Foundation awards MIP-9701408 (CAREER) CDA-9617333 (Instrumentation)