DESIGN OF LOW-VOLTAGE HIGH-GAIN CURRENT-MODE OPERATIONAL AMPLIFIER Thesis Submitted in partial fulfillment of the requirements for the deree of Master of Technoloy (VLSI Desin & CAD) Submitted by Pankaj Kumar Ren. No. 6008603 Under the supervision of Mr. Mohd. Iliyas Project Faculty, ECED Thapar University, Patiala Department of Electronics & Communication Enineerin THAPAR UNIVERSITY (Formerly Thapar Institute of Enineerin & Technoloy) PATIALA - 47004 INDIA 00
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To my parents, for their never-endin support and the sense of security they have iven when I wanted it most; my brothers for encourain me and convincin me to believe in myself and for always believin in me even when I did not; little kids Monalisa and Aditya who will always be dear to me. They have waited so lon for this moment to come true; I am lad that their waitin has finally been rewarded. iv
ABSTRACT In this thesis a hih-ain current-mode operational amplifier has been desined which is current-mode counterpart of traditional voltae-mode operational amplifier. It has been implemented usin a transimpedance input stae followed by a transconductance output stae. Neative feedback around the hih-ain current operational amplifier (COA) produces an accurate closed-loop current ain insensitive to process, supply and temperature variations. An analysis of the COA is presented alon with possible applications. The desin has been implemented on UMC 0.8 µm CMOS n-well process. The current operational amplifier exhibits an open-loop differential ain of 65.38 db with the unity ain frequency of 353.60 MHz and a settlin time of 5.90 ns. The applications of the COA include the implementation of instrumentation amplifier, current comparator with hysteresis, yrator, and differential switched-current filter. v
TABLE OF CONTENTS ACKNOWLEDGEMENTS ABSTRACT TABLE OF CONTENTS LIST OF FIGURES LIST OF TABLES LIST OF SYMBOLS NOMENCLATURE iii v vi ix xii xiii xv CHAPTER PAGE INTRODUCTION. Motivation for Current-Mode Circuit desin. Desin Specifications.3 Applications 3.4 Oranization of Thesis work 4 LITERATURE SURVEY 5. Ideal Current-Mode Circuits 6. Characteristics of Current-Mode Circuits 8.. Input and Output Impedances 8.. Bandwidth 9..3 Slew Rate..4 Propaation Delay..5 Supply Voltae Sensitivity 3..6 Electrostatic dischare 5.3 Desin Techniques for Current-Mode Circuits 6 vi
.3. Basic Current Amplifiers 6.3. Output Impedance Boostin Techniques 8.3.. Basic Cascodes 9.3.. Reulated and Multi-Reulated Cascodes.3..3 Pseudo-Cascodes.3..4 Low-Voltae Cascodes 3.3.3 Input-Impedance Reduction Techniques 4.3.3. Input Capacitance Reduction 5.3.3. Active Feedback 5.3.3.3 Bootstrappin 6.3.4 Mismatch Compensation Techniques 7.3.5 Power Reduction Techniques 3.3.6 Bandwidth Enhancement Techniques 33.3.6. Resistor Series Peakin 33.3.6. Inductor Series Peakin 35.3.6.3 Current Feedback 39.3.7 Dynamic Rane Improvement Techniques 43 3 DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER 46 3. Introduction 46 3. Current-mode operational amplifier 48 3.. Open-loop ain, common mode rejection ratio and input offset current 50 3.. Frequency response, ain-bandwidth and stability 5 3..3 Input and output impedance 5 3..4 Input common mode rane 53 3..5 Power supply rejection ratio 53 3..6 Noise performance 53 3.3 Closed-loop current operational amplifier 54 3.4 COA desin considerations 55 3.5 Aspect ratio of the transistors in the desin 57 3.6 Physical layout desin of current operational amplifier 58 vii
4 SIMULATIONS AND RESULTS 6 4. Test results 6 4.. Current ain, 3-db frequency, unity ain frequency and phase marin 63 4.. Transient results 65 4..3 Common mode rejection ratio 69 4..4 Power supply rejection ratio 7 4..5 Slew rate and % settlin time 74 4. Summary of results 77 5 CONCLUSIONS AND FUTURE SCOPE OF THE WORK 79 5. Conclusions 79 5. Future scope of the work 79 REFERENCES 8 APPENDIX A : SPICE BSIM3v3 VERSION 3. MOS MODEL PARAMETERS 83 viii
LIST OF FIGURES Fiure. Current Conveyers 6 Fiure. CCI ± Current Conveyer 6 Fiure.3 CCI ± Current Conveyer 6 Fiure.4 Loadin effect of voltae-mode and current-mode circuits 9 Fiure.5 Bandwidth comparison of common-source, common-ate, common-drain and current mirrors 9 Fiure.6 Slew rate comparison of different amplifiers Fiure.7 Variations of node voltae and branch current 3 Fiure.8 Supply voltae variation of voltae-mode circuit 4 Fiure.9 Supply voltae variation of current-mode circuit 5 Fiure.0 ESD sensitivity 5 Fiure. Basic current amplifiers 7 Fiure. Different types of cascode Current Mirrors 9 Fiure.3 Reulated cascode current mirror Fiure.4 Pseudo cascode current mirror 3 Fiure.5 Low-voltae cascode current mirrors 4 Fiure.6 Current amplifiers with input active feedback 5 Fiure.7 Bootstrap current amplifier 7 Fiure.8 Dimension mismatch of multi-finer transistor 9 Fiure.9 Balancin network for mismatch compensation 30 Fiure.0 Simulated output without balancin network 3 Fiure. Simulated output with balancin network 3 Fiure. Current branchin 3 Fiure.3 Simulated output of current branchin 3 Fiure.4 Current amplifier with resistor series peakin 34 Fiure.5 Simulated output with resistor series peakin 34 Fiure.6 Current amplifier with inductor series peakin 36 Fiure.7 Simulated output with inductor series peakin 37 Fiure.8 Layout of inductor 37 Fiure.9 Lumped model of spiral inductor 38 Fiure.30 Simulate effect of series resistance of series peakin inductors 38 ix
Fiure.3 Simulate effect of parasitic capacitance of series peakin inductors 39 Fiure.3 Current Amplifier with both current-current feedback and inductor serie peakin 40 Fiure.33 Simulated output of current amplifier with both current-current feedback and inductor series peakin 40 Fiure.34 Current amplifier with both current-current feedback and resistor series peakin 4 Fiure.35 Simulated output of current amplifier with both current-current feedback and resistor series peakin 4 Fiure.36 Basic class AB amplifiers 43 Fiure.37 Low-voltae class AB Current amplifiers 43 Fiure.38 Cascode class AB current amplifiers 44 Fiure.39 Bootstrapped class AB current amplifiers 44 Fiure 3. Interreciprocal network of VOA to COA 47 Fiure 3. Transistor diaram of current operational amplifier 49 Fiure 3.3 Detailed transistor diaram of current operational amplifier 49 Fiure 3.4 Basic feedback controlled current amplifiers 54 Fiure 3.5 Low-voltae current mirror 55 Fiure 3.6 Layout of current operational amplifier 59 Fiure 3.7 Extracted view of the layout 60 Fiure 4. Schematic for the frequency response of the open-loop current operational amplifier 63 Fiure 4. Pre-layout frequency response of the current operational amplifier at typical corner 64 Fiure 4.3 Post-layout frequency response of the current operational amplifier at typical corner 64 Fiure 4.4 Schematic for transient analysis of the open loop current operational amplifier 66 Fiure 4.5 Schematic for transient analysis of current operational amplifier confiured as unity ain buffer 66 Fiure 4.6 Pre-layout transient response of current operational amplifier in open loop confiuration at typical corner 67 x
Fiure 4.7 Pre-layout transient response of current operational amplifier in unity ain confiuration at typical corner 67 Fiure 4.8 Post-layout transient response of current operational amplifier in open-loop confiuration at typical corner 68 Fiure 4.9 Post-layout transient response of current operational amplifier in unity ain confiuration at typical corner 68 Fiure 4.0 Schematic for measurin common mode ain 69 Fiure 4. Pre-layout CMRR curve at typical corner 69 Fiure 4. Post-layout CMRR curve at typical corner 70 Fiure 4.3 Schematic for measurin (a) PSRR,vdd (0) and (b) PSRR,vss (0) 7 Fiure 4.4 Pre-layout PSRR, vdd (0) curve at typical corner 7 Fiure 4.5 Pre-layout PSRR,vss (0) curve at typical corner 73 Fiure 4.6 Post-layout PSRR,vdd (0) curve at typical corner 73 Fiure 4.7 Post-layout PSRR,vss (0) curve at typical corner 74 Fiure 4.8 Schematic for measurin slew rate and settlin time 74 Fiure 4.9 Pre-layout slew rate and settlin time at typical corner 75 Fiure 4.0 Post-layout slew rate and settlin time at typical corner 75 xi
LIST OF TABLES Table. Specifications for the desin 3 Table 3. Aspect ratios of transistors used in the desin 57 Table 4. load resistance and compensatin capacitance 6 Table 4. Pre-layout AC results at different process corners of simulations 63 Table 4.3 Post-layout AC results at different process corners of simulations 65 Table 4.4 Post-layout AC results at different temperatures at typical corner 65 Table 4.5 Pre-layout CMRR values at different process corners of simulations 70 Table 4.6 Post-layout CMRR values at different process corners of simulations 70 Table 4.7 Post-layout CMRR values at different temperatures at typical corner 70 Table 4.8 Pre-layout PSRR values at different process corners of simulations 7 Table 4.9 Post-layout PSRR values at different process corners of simulations 7 Table 4.0 Post-layout PSRR values at different Temperatures 7 Table 4. Pre-layout slew rate and settlin time at different process corners of simulations 76 Table 4. Post-layout Slew rate and Settlin time at different process corners of simulations 76 Table 4.3 Post-layout Slew rate and Settlin time at different temperatures at typical corner 76 Table 4.4 Pre-layout simulation results at different corners 77 Table 4.5 Post-layout simulation results at different corners 77 Table 4.6 Post-layout simulation results at typical corner: Effect of temperature variation 78 xii
LIST OF SYMBOLS V DD Supply Voltae C s Gate to Source Capacitance C d Gate to Drain Capacitance C db Drain to Substrate capacitance mi Transconductance of MOSFET r oi Output Resistance oi Output Conductance i o Output Current i in Input Current v o Output Voltae v in Input Voltae z o Output Impedance z in Input Impedance ω p Pole Frequency ω in Input Pole Frequency ω o Output Pole Frequency R s Source Resistance C in Input Capacitance J i Strenth of Current Source io S V Supply Voltae Sensitivity DD xiii
W L s Width of MOSFET Lenth of MOSFET Complex Frequency xiv
NOMENCLATURE VOA COA CMRR PSRR TT or tt FF or ff SS or ss SF or snfp FS or fnsp Voltae operational amplifier Current operational amplifier Common mode rejection ratio Power supply rejection ratio Typical NMOS Typical PMOS Fast NMOS and fast PMOS Slow NMOS and slow PMOS Slow NMOS and fast PMOS Fast NMOS and slow PMOS xv
CHAPTER. INTRODUCTION CHAPTER INTRODUCTION Since the introduction of Interated Circuits, the operational amplifier has served as the basic buildin block in analo circuit desin. Voltae-mode operational amplifier circuits have limited bandwidth at hih closed-loop ains due to the constant ain-bandwidth product. Furthermore, the limited slew rate of the operational amplifier affects the laresinal, hih frequency operation. For wide bandwidth, low-power consumption and lowvoltae operation are needed simultaneously and the Voltae-Mode Operational amplifier easily becomes too complex. Therefore, there is a rowin need for new, low-voltae analo circuit techniques.. MOTIVATION FOR CURRENT-MODE CIRCUIT DESIGN One procedure for findin alternative, preferably simpler, circuit realizations is to use current sinals rather than voltae sinals for sinal processin [, ]. MOS transistors in particular are more suitable for processin currents rather than voltaes because the output sinal is current both in common-source and common-ate amplifier confiurations and common-drain amplifier confiuration is almost useless at low supply voltaes because of the bulk-effect present in typical CMOS processes. Moreover, MOS current mirrors are more accurate and less sensitive to process variation than bipolar current mirrors because with the latter the base currents limit the accuracy. Therefore, at the very least, MOS transistor circuits should be simplified by usin current sinals in preference to voltae sinals. For this reason, interated current-mode system realizations are closer to the transistor level than the conventional voltae-mode realizations []. When sinals are widely distributed as voltaes, the parasitic capacitances are chared and dischared with the full voltae swin, which limits the speed and increases the power consumption of voltae-mode circuits. Current-mode circuits cannot avoid - -
CHAPTER. INTRODUCTION nodes with hih voltae swin either but these are usually local nodes with less parasitic capacitances [3]. Therefore, it is possible to reach hiher speed and lower dynamic power consumption with current-mode circuit Techniques. When the sinal is conveyed as a current, the voltaes in MOS transistor circuits are proportional to the square root of the sinal, if saturation reion operation is assumed for the devices. Similarly, in bipolar transistor circuits the voltaes are proportional to the loarithm of the sinal. Therefore, a compression of voltae sinal swin and a reduction of supply voltae are possible. This feature is utilized for example in lo domain filters, switched current filters, and in non-linear current-mode circuits in eneral [3]. Unfortunately, as a consequence of the device mismatches this non-linear operation may enerate an excessive amount of distortion for applications with hih linearity requirements. Thus, in certain current-mode circuits, linearization techniques are utilized to reduce the nonlinearity of the transistor transconductance, in which case the voltae sinal swin is not reduced. However, new solutions invariably entail new problems. The compression of the voltae sinal swin, for example, increases sensitivity to mismatches. Similarly, a lare amount of current-mode circuits require advanced complementary bipolar interation processes utilizin vertical npn- and pnp- transistors with a hih unity ain frequency, circuits which need excessively hih supply voltaes in order to be useful in most battery operated applications. Furthermore, some current-mode techniques such as the current feedback are very old and are used as enhanced voltaemode sinal processin buildin blocks rather than as true current-mode sinal processin buildin blocks. At radio frequencies, current-mode circuit techniques are limited to on chip sinal processin in interated circuits as off chip impedance levels are fixed, typically 50 Ω. However, the aressive scalin of interation technoloies ensures that current-mode circuit techniques will remain useful in the future [3].. DESIGN SPECIFICATIONS In this work, a CMOS current operational amplifier (COA) with fully differential input and differential output has been desined and implemented from a differential current mirror input transimpedance stae followed by a differential output transconductance ain stae. This confiuration is the current-mode counterpart of the traditional voltae - -
CHAPTER. INTRODUCTION operational amplifier (VOA). table. The required specifications are iven in the followin Table. Specifications for the desin Power supply ±.5 V Open-loop ain > 60 db 3 db frequency > 450 khz Unity ain frequency > 300 MHz Compensation capacitance 5 pf Phase marin > 55 0 CMRR > 40 db PSRR, vdd(0) > 50 dbω PSRR, vss(0) > 50 dbω % settlin time < 5 ns Slew rate 5 µa/ns.3 APPLICATIONS The current-mode operational amplifier has been desined to measure beam current of MC50 cyclotron in closed-loop confiuration. MC50 cyclotron is a variable enery isochronous cyclotron for the acceleration (up to 50 MeV) of liht particles, which can be used in the fields of nuclear medicine, physics, bioloy and enineerin. It has been used for neutron irradiation, radioisotope production, cyclotron application research, and preventive maintenance. Operation of MC50 cyclotron is very important because it has produced many radioisotopes for medical uses and developed new nuclear isotopes. In the result, MC50 has contributed to the neutron radioraphy, development of cyclotron application researches and the nuclear science researches. It has a limited capability in proton beam currents (maximum current 60 µa) for the mass production. The applications of the COA also include the implementation of instrumentation amplifier, current comparator with hysteresis, yrator, and differential switched-current filter. - 3 -
CHAPTER. INTRODUCTION.4 ORGANIZATION OF THESIS WORK The thesis is oranized as follows: CHAPTER : INTRODUCTION. This chapter ives an idea of need for current-mode circuits, the specifications of the desin and its applications. CHAPTER : LITERATURE SURVEY. The topic covers the comparative study of current-mode and voltae-mode circuits with respect to input and output impedance, slew rate, power supply rejection ratio, bandwidth, propaation delay and electrostatic dischare etc. It also covers various current-mode circuit desin techniques. CHAPTER 3: DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER. It covers the mathematical analysis of the circuit and its desin considerations. The aspect ratios of the transistors of the desin and its layout are also iven in the chapter. CHAPTER 4: SIMULATIONS AND RESULTS. A comparison between pre-layout and post-layout results have been discussed. The effect of temperature on different parameters has also been discussed. Comparison has been done at all process corners of simulations. CHAPTER 5: CONCLUSIONS AND FUTURE SCOPE OF THE WORK. A brief conclusion and possible improvements have been discussed in this chapter. - 4 -
CHAPTER. LITERATURE SURVEY CHAPTER LITERATURE SURVEY The information processed by lumped electric networks can be represented by either the nodal voltaes or branch currents of the networks. The former are referred to as voltaemode circuits whereas the latter are known as current-mode circuits. Toether, they provide a complete characterization of the behavior of the networks. Voltae-mode circuits have received a much broader attention and found a much wider rane of applications as compared with their current-mode counterparts despite the fact that the concept of ideal current-mode circuits, similar to that of ideal voltae-mode circuits, emered approximately 40 years ao [4,5]. This is reflected by a handful monoraphs on current-mode circuits but countless texts on voltae-mode circuits. The reasons for such popularity that voltae-mode circuits have been enjoyin can be summarized as follows: (i) The nodal voltae of electric networks can be measured conveniently usin voltmeters without modifyin the topoloy and affectin the operation of the networks. On the contrary, the measurement of the branch current of the networks is less convenient and often requires a chane of the confiuration of the networks or additional circuitry. (ii) The infinite impedance lookin into the ate of MOS transistors makes these devices an ideal choice for the realization of voltae-mode circuits, especially in cascade confiurations, such as multi-stae voltae amplifiers. (iii) The ease to obtain a hih voltae ain of voltae-mode circuits usin techniques such as cascodes and reulated cascodes. (iv) Hih supply voltaes available in the past such that low-voltae desin was not of a critical concern. (v) Switchin noise was not a critical issue with the presence of a hih supply voltae. (vi) Low speed requirements permit the chare and dischare of nodal capacitors over a lon period of time. The aressive reduction in the supply voltae and the moderate reduction in the device threshold voltae of CMOS technoloy have reatly affected the performance of CMOS voltae-mode circuits, typically reflected by a reduced dynamic rane, an - 5 -
CHAPTER. LITERATURE SURVEY increased propaation delay, and reduced low noise marins. The impact of supply voltae reduction on the performance of current-mode circuits, however, is less severe as compared with that of voltae-mode circuits. This is because the desin emphasis of current-mode circuits is on branch currents rather than nodal voltaes. The usefulness of CMOS current-mode circuits in combatin the difficulties arisin from the reduction of the supply voltae and the increase in the operation speed has received an increasin attention both from industry and academia recently. The different desin focuses of voltae-mode and current-mode circuits, arisin from the intrinsic characteristics of nodal voltaes and branch currents, result in distinct desin principles. This chapter provides a brief comparison of the characteristics of voltae-mode and current-mode circuits based on input and output impedance, bandwidth, slew rate, propaation delay, supply voltae sensitivity, electrostatic dischare etc. Various currentmode circuit desin techniques have also been discussed.. IDEAL CURRENT-MODE CIRCUITS An ideal voltae-mode circuit possesses infinite input impedance, zero output impedance, and a constant voltae ain. It can be best represented by an ideal operational amplifier [6]. The infinite input impedance and a zero output impedance of operational amplifiers not only enable a convenient cascade of operational amplifiers without a loadin effect, they also ensure that the characteristics of these circuits are determined by the external elements only and are independent of the characteristics of the operational amplifiers. Fiure. Current conveyors. iy 0 = vx i z 0 0 ± 0 v 0 i 0 v y x z i v i y x z 0 = 0 0 0 ± 0 v 0 i 0 v y x z Fiure. CCI± Current conveyers. Fiure.3 CCII± Current conveyers. - 6 -
CHAPTER. LITERATURE SURVEY Unlike ideal voltae-mode circuits, an ideal current-mode circuit has the characteristics of zero input impedance, infinite output impedance, and a constant current ain. Because current amplification will result in a hih level of static power consumption, the current ain of ideal current-mode circuits is set to unity historically. The first ideal current-mode circuits are the first eneration current conveyors, denoted by CCI±, where the polarities specify whether the direction of the output current is the same as that of the current flowin into node x or not [5]. As shown in Fiure., the current conveyor has three terminals: the current input terminal x, the control terminal y and the output terminal z, and is characterized by the equations iven in Fiure.. The node y is the control node who s current and voltae are identical to those of the input node x. The impedance lookin into nodes x and y is zero ideally. Node z is the output node with infinite output impedance. The application of CCI± becomes difficult because both nodes x and y have zero input impedance ideally in order to sink currents. The control node y needs to take a control current rather than a control voltae, which is usually difficult to obtain in practical desins. To alleviate this problem, the second eneration current conveyors, denoted by CCII±, where the control node y is chaned from a current control node to a voltae control node, were proposed [5]. The behavior of CCII± is characterized by the equation iven in Fiure.3. The voltae control node y has infinite input impedance ideally. The current control node x, on the other hand, has zero input impedance ideally, enablin a current to flow into the node without any resistance. Because the output of the conveyer is a current, the load of the conveyer must be of a low impedance, v z = 0 holds ideally. Similar to operational amplifiers that have numerous practical implementations, current conveyors can also be realized in a number of ways and new CCII± with an emphasis on speed, power consumption, and low supply voltae are emerin []. In addition, the applications of CCII± bear a stron resemblance to those of operational amplifiers where the characteristics of systems employin CCII± are determined by the passive elements external to CCII± only. CCII± have found a broad spectrum of applications such as active filters, impedance conversion, oscillators, and instrumentation amplifiers, to name a few. - 7 -
CHAPTER. LITERATURE SURVEY. CHARACTERISTICS OF CURRENT-MODE CIRCUITS In this section, comparison between voltae-mode and current-mode circuit with respect to input/output impedance, bandwidth, slew rate, propaation delay, power supply sensitivity etc. have been discussed... INPUT AND OUTPUT IMPEDANCES It was pointed out earlier that a voltae-mode circuit is featured by lare input impedance and low output impedance. On the contrary, a current-mode circuit possesses low input impedance and hih output impedance. The loadin effect arisin from the finite output impedance of current-mode circuits or equivalently the non-zero input impedance can be studied usin Fiure.4 where the input source is represented by its Norton equivalent. The load current is iven by i in o = io io z, (.) in zo + z o z where z o and z in are the output impedance of the drivin stae and the input impedance of the driven stae, respectively. Note that z << z was assumed in simplifyin (.). To in o minimize the loadin effect, z << z is required for current-mode circuits. Similarly, in o when the input is represented by its Thevenin equivalent, the loadin effect of voltae mode circuits can be studied usin Fiure.4 with the load voltae = z vo. (.) + z o v o ( ) zo zin in To minimize the loadin effect, z >> z is required for voltae-mode circuits [6]. in o - 8 -
CHAPTER. LITERATURE SURVEY Fiure.4 Loadin effect in current-mode circuits and voltae-mode circuits... BANDWIDTH The bandwidth of voltae-mode and current-mode circuits can be best compared usin the buildin blocks of voltae/current mode circuits shown in Fiure.5. (a) (b) (c) (d) Fiure.5 Bandwidth comparison of voltae-mode and current-mode circuits, (a) Basic current mirror, (b) Common-source amplifier, (c) Common-ate amplifier, (d) Source follower. Because a well desined current-mode circuit has lare output impedance and small input impedance, the load impedance z L 0 holds. As a result, M of the basic current mirror is not subject to Miller effect. The only pole of the basic current mirror is at the ate of M ~ with the pole frequency iven by - 9 -
CHAPTER. LITERATURE SURVEY m ω p. (.3) Cs + Cs + Cd Due to the existence of the floatin ate-drain capacitor C d, the common-source confiuration is subject to Miller effect with Miller capacitances C = C ( + r ) at the m d m o ate and C m = Cd ( + ) at the drain, where r o and m are the output impedance and r m o transconductance of the transistor, respectively. The pole at the input called Miller pole, is iven by ω in =, (.4) R ( C + C ( + r )) s s d m o where R s is the resistance of the source. The output pole is estimated from ω o, (.5) r ( C + C ) o d in where C in is the input capacitance of the load stae. The common-ate confiuration is not subject to Miller effect due to the absence of floatin capacitors. The pole at the input is iven by ω in, (.6) R C s s and the pole at the output is computed from ω o. (.7) r ( C + C ) o d in The source follower is also free of Miller effect simply because its small sinal voltae ain is approximately unity. The Miller capacitances at the ate and source are iven by C m C m 0. The pole at the input is iven by ω in, (.8) R C s d and the dominant pole at the output is iven by - 0 -
CHAPTER. LITERATURE SURVEY ω o. (.9) r C o in For practical applications, C in and r o are often lare; the dominant pole of the common-source, common-ate, and source follower amplifiers is usually at the output node. The pole frequency of the basic current mirror is therefore smaller as compared with the pole frequency of the basic voltae-mode amplifiers [6]...3 SLEW RATE The slew rate of voltae-mode and current-mode circuits is compared usin the commonsource confiuration and the basic current mirror shown in Fiure.6. When a square waveform current is applied to the basic current mirror, because M is in the saturation, i DS is independent of v DS when the channel lenth modulation is nelected. The rate of the chane of the output current depends upon how fast C s~ = Cs + Cs is chared or equivalently how fast the ate voltae of M ~ rises. Because dvgs W C s + ~ µ ~ ncox ( vgs VT ) = J + i, (.0) in dt L v GS~ increases with i in. For fixed biasin currents, the larer the amplitude of the input, the hiher the slew rate of the output current. For voltae mode circuits, the slew rate is usually determined by the output stae because of the lare width of the transistors in the output stae and the lare capacitance of the load. Consider the common-source amplifier, when a sufficiently low voltae V min is applied to the input, the transistor switches off and C o is chared by J only, we have dvo dt rise,max = J C o. (.) When V in = V max, C o is dischared via the transistor with the slew rate dv o = dt R C fall,max on o, (.) where R on is the channel resistance of the transistor in the triode reion. The precedin results reveal that the slew rate of common-source amplifier is set by the biasin current, - -
CHAPTER. LITERATURE SURVEY the width of the transistor, and the output capacitance. It is independent of the amplitude of the input voltae. A similar conclusion can be drawn for the voltae mode differential pair confiuration [6]. (a) (b) (c) Fiure.6 Slew rate comparisons of voltae-mode and current-mode circuits, (a) Basic current mirror, (b) Common-source amplifier, (c) Basic differential pair...4 PROPAGATION DELAY For diital circuits, the averae propaation delay is a widely used fiure-of-merit depictin the transient behavior of the circuits. It is directly related to the swin of the sinal [6]. Nelectin both the resistance and inductance, the averae risin (fallin) time of the voltae of a node, denoted by t, is determined from t Cn( vn ) = i( t) dt = Iav t, (.3) 0 where I av is the averae current charin/discharin the node, C n is the capacitance of the node, i(t) is the net current flowin into/out the node, and v n is the voltae swin of the node. Eq. (.3) reveals that a small propaation delay can be achieved by either minimizin the swin of the voltae of the node or maximizin the current charin and discharin the capacitance of the node. For voltae mode circuits, v n is constrained by the sinal to noise ratio requirements and must be kept sufficiently lare, resultin in a slow transient response. - -
CHAPTER. LITERATURE SURVEY Unlike voltae-mode circuits, the information carriers of current-mode circuits are branch currents. The variation of nodal voltaes can be kept small as lon as the current of the branches associated with the nodes is lare. Consider Fiure.7, from B B in, b = b = v = z ( i i ), (.4) n n b o, b where z n is the impedance of the node, B and B are the number of input and output branches connected to the node, respectively, we conclude that for a iven v n, a lare current variation can be obtained as lon as z n is kept small. The small nodal voltae variation of current-mode circuits lowers the amount of time needed to chare/dischare C n, resultin in a faster transient response. This is one of the key advantaes of currentmode circuits [6]. Fiure.7 Variation of nodal voltaes and branch currents of current-mode circuits...5 SUPPLY VOLTAGE SENSITIVITY The effect of V DD and round fluctuations on the output voltae (current) of CMOS circuits is of a critical concern in mixed-mode circuits because both analo and diital circuits often share the same supply voltae and round. Supply voltae sensitivity, defined as v Sv o DD vo =, (.5) V DD is a measure of the effect of the variation of the supply voltae on the response of the circuits. Assume the supply voltae is chaned from V DD to V DD + V DD, where V DD is a - 3 -
CHAPTER. LITERATURE SURVEY random variable with zero mean. For practical circuits, V DD << V DD holds and the smallsinal analysis approach can be employed to analyze the effect of V DD on the response of the circuits. Consider the common-source amplifier shown in Fiure.8(a). M is biased in the saturation and (a) (b) Fiure.8 Supply voltae sensitivity analysis of voltae-mode circuits, (a) Common- source amplifier, (b) Small-sinal equivalent circuit. behaves as a current source. The small-sinal equivalent circuit of the amplifier for supply voltae sensitivity analysis with junction capacitances nelected is shown in Fiure.8(b). At low frequencies where C s and C d are nelected, we have v SV o =. (.6) DD m ( ro ro ) m o + o The above result shows that V DD is directly amplified with a lare voltae ain. It is worth notin that Fiure.8(a) is the common-ate amplifier with v in the biasin voltae of M, which behaves as a current source, and V DD the input of the common-ate confiured M. Now let us consider the circuit shown in Fiure.9. The load is a current mirror with the source current provided by an ideal current source J. Usin a small-sinal analysis, it can be shown that S o =. (.7) DD i V o - 4 -
CHAPTER. LITERATURE SURVEY As compared with (.6), because o << m the current-mode circuit is less sensitive to the fluctuation of the supply voltae. Also seen is that the effect of V DD on v o is mainly due to the finite output impedance r o of the load current mirror [6]. (a) (b) Fiure.9 Supply voltae sensitivity analysis of current-mode circuits, (a) Current mirror amplifier, (b) Small-sinal equivalent circuit...6 ELECTROSTATIC DISCHARGE A lare number of ESD (electrostatic dischare) induced damaes of MOSFETs is due to the breakdown of the ate oxide insulator, especially when the thickness of the ate oxide t ox is scaled down aressively in deep sub-micron CMOS technoloies. (a) (b) Fiure.0 ESD sensitivity, (a) Voltae-mode circuits, (b) Current-mode circuits. - 5 -
CHAPTER. LITERATURE SURVEY Voltae-mode circuits are particularly vulnerable to ESD strikes as the input node of these circuits is usually the ate of MOSFETS, a hih impedance node [6]. No low impedance paths from the input pads to the round exist to dischare electrostatic chare accumulated at the pads, as shown in Fiure.0(a). On the contrary, the low impedance characteristics of the input pads of current-mode circuits prevent the accumulation of static chare at the pads, as shown in Fiure.0(b)..3 DESIGN TECHNIQUES FOR CURRENT-MODE CIRCUITS The rapid down scale of the feature size of MOS devices, the aressive reduction in the supply voltae, and the moderate reduction in the threshold voltae of modern CMOS technoloies have reatly affected the performance of CMOS current-mode circuits, reflected by a small dynamic rane, a reduced effective ate source voltae, a low device output impedance, and an increased level of device mismatches. This section examines the desin techniques that improve the performance of low-voltae CMOS current-mode circuits..3. BASIC CURRENT AMPLIFIERS The schematic of basic CMOS current amplifiers is shown in Fiure.(a). Because a well-desined current-mode circuit possesses small input impedance and lare output impedance, it is reasonable to assume that the load impedance is sufficiently small. As a result, M is not subject to Miller effect. Under a perfect matchin condition and nelectin the channel lenth modulation, the current transfer function is iven by where m A = and m Io( s) A, (.8) Iin( s) s + ω b m ω b. (.9) C + C + C s s d The input impedance of the basic current amplifier is iven by - 6 -
CHAPTER. LITERATURE SURVEY z in ( s) = ( s ω m + b ). (.0) The input impedance can be lowered by either increasin the width of M or increasin the biasin current. The former lowers the bandwidth whereas the latter increases the static power consumption. The output impedance is iven by zo r o approximately. The output impedance of MOSFETs in deep sub-micron CMOS technoloies is small. The finite output impedance of MOSFETs ives rise to a chane of the output current I o when the output voltae v o varies. Because io = m vs + ovo and i in ( m + o ) vs A io = iin + o o + m v o =, we have A( Ai in + o m ) i v. o o in + v o o (.) The second term on the riht hand side of (.) is the output error current. (a) (b) (c) Fiure. (a) Basic current amplifier, (b) Noise source in basic current amplifier, (c) input-referred noise voltae and noise current enerators of basic current amplifier. The noise equivalent circuit of the basic current amplifier is shown in Fiure.(b, c). The equivalent channel noise of M and M denoted by i n and i n respectively, consists of (i) the thermal noise of the channel and (ii) the thermal noise of the ate resistance that - 7 -
CHAPTER. LITERATURE SURVEY is referred to the channel. Because circuits of our interests operate at hih frequencies, the flicker noise of MOS transistors, which has a typical corner frequency of a few MHz, is nelected. As a result, i n, =, m, ) m, 4kT ( γ + R f, (.) where R is the ate series resistance, γ. 5 for deep sub-micron devices, T is the temperature in Kelvin, and k is Boltzmann constant. For a typical 0.8μm CMOS technoloy, the sheet resistance of silicided polysilicon (ate) is approximately 8Ω. If the dimension of the ate of a NMOS transistor is W = 00 µm and L = 0.8 µm with onefiner layout, then R 4.44 kω. Assume m = 5 ma/v, we have R m =.. Clearly in this case the noise of the NMOS transistor is dominated by the thermal noise of the ate series resistance. To reduce the thermal noise of the ate series resistance, the multifiner layout approach becomes mandatory [6, 7]. Consider that 4 finers are used for the transistor, we have W = 5 µm for each finer. Because these finers are connected in parallel, R. kω and R m 5.5 which is comparable to the value of γ. Usin conventional approaches for noise analysis, we can show that the power of the inputreferred noise voltae and current enerators respectively, are iven by v n = m in ( A ) i in =. (.3) A n in + where v n and n i are the mean square values of input referred voltae and current..3. OUTPUT IMPEDANCE BOOSTING TECHNIQUES Different techniques for improvin output impedance have been discussed in this section. These techniques include Basic cascode, Self-biased cascode, Wilson Current Mirror and improved Wilson Current Mirror. - 8 -
CHAPTER. LITERATURE SURVEY.3.. BASIC CASCODES It was pointed out in the precedin section that the output error current of the basic current amplifiers can be minimized by maximizin the output impedance. Cascode confiuration shown in Fiure.(a) employs a neative voltae-current feedback to sustain the output current in the presence of a varyin output voltae. The output impedance of the cascode current amplifier can be obtained from its small sinal equivalent circuit zo ( m3 ro 3) ro. (a) (b) (c) (d) Fiure. (a) Cascode current amplifier with an external biasin voltae V b, (b) Self- biased cascode current amplifier, (c) Wilson current amplifier, (d) Improved Wilson Current amplifier. Let us examine the reduction in the output error current from the cascode. Writin KCL at the drain of M yields v v v o3 o m in =. (.4) o + o3 + m3 Further i = ) v, i = v + v ), in ( + m o in o ( m3 o3 o v And assume >>, we have m o v. (.5) o i o Aiin + ( ) m3ro 3 o A comparison of (.) and (.5) reveals that the output current error of the cascode current amplifier is m3 r 03 times lower than that of the basic current amplifier [6]. The - 9 -
CHAPTER. LITERATURE SURVEY cascode current amplifiers also possess lare bandwidth. This is because M are nearly m3 free of Miller effect. The Miller capacitances of M are iven by C m = Cd ( + ) at m the ate and C m = Cd ( + ) at the drain. M 3 is common-ate confiured and is not m3 subject to Miller effect. From the current transfer function m Io( s) = I ( s) in m m C s ( s m C s3 m3 C ) + s( s m C + s3 m3 ) +, (.6) we obtain the poles of the system p, = C C + C + C m m3 s s3 s s3 scs3 m m3 m m3 C = C m s m3 s3. (.7) The bandwidth of the cascode current amplifier is the same as that of the basic current amplifier. The biasin voltae can be obtained from the cascode itself, as shown in Fiure.(b). The minimum supply voltae of the self-biased cascode current amplifier of Fiure.(b) is V T + V sat increased from V T + V sat of the externally biased cascode current amplifier of Fiure.(a). Wilson current amplifier shown in Fiure.(c) is another variation of cascode current amplifiers. The input impedance at low frequencies m is iven by z in = +. The output impedance of Wilson current amplifier is m m m3 m 3 iven by ( m z ) o ro 3ro, the same output impedance as that of the basic cascode m current amplifier. The current ain of Wilson current amplifier is iven by Cs s + Io( s) mm3 m =. (.8) Iin( s) Cs Cs3 m + m3 m m3 s + s( ) + C C C s s s3-0 -
CHAPTER. LITERATURE SURVEY The current ain in the dc steady state is the same as that of the basic cascode current amplifier. The zero is located at frequency z = C m s and the complex conjuate poles are m iven by p, = ( + j) when M ~3 are identical, resultin in 3 C ~ m m, C s s ( Cs + Cs) Cs3 =. Its bandwidth is the same as that of the basic current amplifier. Difficulties exist in obtainin an appropriate dc operatin point of Wilson current amplifier because of the constraint V DS > V T. This difficulty can be removed by addin another transistor in the input branch, as shown in Fiure.(d) [6]. Both the input and output impedances of the improved Wilson current amplifier can be obtained followin a similar approach as that for Wilson current amplifier and the results are iven m by z in = + and z o = ( m ro ) ro 4. m m m4.3.. REGULATED AND MULTI-REGULATED CASCODES To further increase the output impedance, a neative voltae-voltae feedback amplifier can be employed, as shown in Fiure.3(a). The amplifier stabilizes the output current I o when V o varies. The circuit can be implemented in various ways. Fiure.3(b) is an implementation usin a common-source amplifier. (a) (b) (c) Fiure.3 (a, b) Reulated cascode current amplifiers, (c) Multi-reulated cascade current amplifiers. - -
CHAPTER. LITERATURE SURVEY The output impedance of the reulated cascode current amplifier of Fiure.3(a) can be derived from its small sinal equivalent circuit r o v = = ro ro 4 + + ro 3m3m4 + m3 i T ro ro 4 A, (.9) ( m4 ro 4) ro where A = m3 r o3 the voltae ain of the auxiliary amplifier. The output impedance can be further increased by boostin the voltae ain of the auxiliary amplifier. One approach is shown in Fiure.3(c) where the feedback network itself is now a cascode amplifier. Replacin the term associated with the common source auxiliary amplifier in (.9) with the ain of the cascode amplifier iven by A = r )( r ), we obtain the output impedance of the multi-reulated cascode v ( m3 o3 m5 o5 current amplifier r =. (.30) o [( m3 ro 3)( m5ro 5)]( m4ro 4) ro It should be noted that the minimum supply voltae of the reulated and multi-reulated cascode current amplifiers is iven by V T +V sat, whereas that of the basic cascode current amplifiers is only V T + V sat [6]..3..3 PSEUDO-CASCODES Reulated and multi-reulated cascodes increase the output impedance, however, at the cost of a hiher supply voltae. This is because in order to have lare output impedance, the biasin current source J in the output branch of the reulated and multi-reulated cascode current amplifiers must also be cascode confiured. To keep the supply voltae low and at the same time to ensure lare output impedance, the pseudo-cascode technique shown in Fiure.4 is used. Note that in this case, J need not to be implemented in cascode. The minimum supply voltae of the output branch is only V T + V sat. It can be shown that the output impedance of the pseudo-cascode current amplifiers is iven by zo ( m3 ro 3) ro. The added common ate stae has no neative effect on the bandwidth. Pseudo-cascodes are self-biased, makin them attractive for low-power applications [6]. - -
CHAPTER. LITERATURE SURVEY (a) (b) Fiure.4 Pseudo-cascode current amplifiers..3..4 LOW-VOLTAGE CASCODES Because V T is usually much larer than V sat, the cascode current amplifier of Fiure.(b) can be modified to Fiure.5(a) to lower the supply voltae requirement while preservin the properties of the cascode current amplifiers. The minimum supply voltae of the low-voltae cascade current amplifier is iven by V DD,min = V T + V sat. The input impedance at low frequencies is iven by / m, which is the same as that of the basic current amplifier. The output branch is the same as the basic cascode current amplifier with zo ( m4 ro 4) ro. To derive the current ain and bandwidth, writin KCL at the ate and drain of M, the drain of M, and notin that I in = sc sv + m V 3( 0 ) and I = 0 ) we arrive at o Io( s) = I ( s) in m m m4( V3 s C s3 m C s C s m3 s3 m3 + C + s s m + (.3) The two poles are at - 3 -
CHAPTER. LITERATURE SURVEY p, m3 C m s3 = [ ± 4( )( )] (.3) C C s3 m3 s If all transistors are of the same size, we arrive at C s C s 3 and m m3. As a result, the poles become m p, = ( ± j) C s It is evident that the low-voltae cascode current amplifier has the same bandwidth as that of the basic cascode current amplifier. (a) (b) (c) Fiure.5 (a) Low-voltae cascode current amplifier, (b) Low input capacitance current amplifier, (c) Low input-impedance current amplifier..3.3 INPUT-IMPEDANCE REDUCTION TECHNIQUES Equally important as lare output-impedance for current-mode circuits is small inputimpedance. This is because low input-impedance reduces the loadin induced current error. Also, in applications such as data links over wire channels, a low input-impedance of the receivers is critical to increase the pole frequency at the input as the channels often have a lare capacitance. This section investiates the techniques that reduce the inputimpedance of current-mode circuits. - 4 -
CHAPTER. LITERATURE SURVEY.3.3. INPUT-CAPACITANCE REDUCTION The capacitance seen from the input of the basic current amplifier is approximately C C + C in s s. To lower the input-capacitance, a source-follower can be employed at the input to isolate the ate capacitance C s +C s from the input node, as shown in Fiure.5(b). Because the Miller capacitances of M3 are approximately zero, C in 0 holds. The input-impedance at low frequencies is iven by zin. The current ain at m i low frequencies is iven by i o in m =, the same as that of the basic current amplifier [6]. m.3.3. ACTIVE FEEDBACK The use of input active feedback to lower the input-impedance is shown in Fiure.6. It is trivial to show that the input impedance of Fiure.6(a) at low frequencies is iven by z in = where A is the voltae ain of the auxiliary amplifier. A m (a) (b) (c) Fiure.6 (a, b) Current amplifiers with input active feedback, (c) Current amplifiers with input active feedback and reulated cascode output. The auxiliary amplifier can be implemented in various ways provided that these implementations offer lare bandwidth. In Fiure.6(b), a common-ate confiuration - 5 -
CHAPTER. LITERATURE SURVEY is employed to take the advantae of their immunity from Miller effect. Note that due to the close interaction with the feedback network, the input-impedance of the current amplifier of Fiure.6(b) increases rapidly at hih frequencies when the effect of C s, C d and parasitic junction capacitances are accounted for. Both the active input feedback and reulated cascode can be employed simultaneously to lower the input-impedance and boost the output-impedance, as shown in Fiure.6(c). It is readily to verify that the input-impedance and output-impedance of the active input reulated cascode current amplifier are iven by z = A. o ( m3 ro 3) ro zin and A The current amplifier shown in Fiure.5(c) is another approach to implement the active feedback at the input. M 3 introduces a neative feedback to stabilize the input voltae, lowerin the input-impedance. The input-impedance is iven by z in = ( m m3 ro 3). Note that the minimum supply voltae requirement of the current amplifier is V T + Vsat the same as that of the basic current amplifier. m.3.3.3 BOOTSTRAPPING Basic cascode and reulated-cascode current amplifiers are not particularly attractive for low-voltae desin because in order to have lare output-impedance, the biasin current source J in the output branch must also be cascode confiured. To achieve a low inputimpedance, a lare output-impedance, and at the same time to keep the supply voltae low, bootstrapped current amplifiers are used. The basic confiuration of bootstrapped current amplifiers is shown in Fiure.7(a). The auxiliary amplifier is employed to enable the input and output voltaes to track each other. In addition, it lowers the inputimpedance and boosts the output-impedance. The small-sinal equivalent circuit of the bootstrapped current amplifier at low frequencies is shown in Fiure.7(b). The outputimpedance is obtained v o + Am zo = = (.33) i + A( ) T o o m o m o - 6 -
CHAPTER. LITERATURE SURVEY Assumin M and M are identical and v DS = vds. This leads to mo = mo. Further because m >> o, (.33) is simplified to z A (.34) o ( m ro ) ro Eq. (.34) shows that the output-impedance of the bootstrapped current amplifier is comparable to that of the reulated cascode current amplifier. It should be noted that J must also be bootstrap confiured in order to have lare output-impedance. The inputimpedance can be obtained in a similar manner and is iven by zin. A m (a) (b) Fiure.7 (a) Bootstrapped current amplifiers, (b) Small-sinal equivalent circuit..3.4 MISMATCH COMPENSATION TECHNIQUES The basic current amplifiers suffer from device mismatches, mainly W/L-mismatch, V T - mismatch, v DS -mismatch, and v GS -mismatches. W/L-mismatch is due to the variation of fabrication processes. The dimension mismatch of transistors with multi-finer confiuration differs from that of transistors with sinle-finer confiuration, as shown in Fiure.8. In a -finer confiuration case, W = ( W + W ) whereas in the onefiner confiuration W = W + W ). For amplifiers with a current ain of A, we have ( - 7 -
CHAPTER. LITERATURE SURVEY W L W = A L W L v s V T v DS Because i + λ D = id W vs V T v + λ DS L We arrive at i D ( + W / L) id W +. (.35) L (.36) = δ (.37) whereδ W / L ( W / L) =.The second term in (.37) is the output offset current due to W/L- W / L mismatch. The v GS -mismatch is mainly due to unbalanced interconnects connectin the ate and source of the input and output transistors. Let v Nelectin the second-order term in (.36), we arrive at GS = vgs, vgs = vgs + vgs. i = δ, (.38) D ( + vgs) id where v v GS δ GS. Note that since the effective ate voltae GS T vgs VT v V is usually small, δvgs contributes sinificantly to the overall output offset current. V T -mismatch is process induced and can be analyzed in a similar way as v GS -mismatch. i D ( + δv ) i T D =, (.39) where δ V T VT v V GS T. For the same reason as that for v GS -mismatch, V T -mismatch is critical. In a similar manner as that of v GS- mismatch, one can analyze the effect of v DS - mismatch i = δ, (.40) D ( + vds) id whereδv λ v DS vds. + λvds - 8 -
CHAPTER. LITERATURE SURVEY (a) (b) Fiure.8 Dimension mismatches of multi-finer transistors, (a) One finer layout (b) two finer layout [6]. For practical circuits, since v << V v << V, we have vgs << VGS s GS, ds DS and vds << V DS, subsequently vgs VGS V V GS T δ v, GS δ VT, VGS VT VGS VT and vds VDS. This leads to δv λ V DS vds. Because id = iin + J + λvds current of the current amplifier with mismatches considered is iven by the output i = A( + δ )( i J) o in + = A( i + J) + δ A( i J), (.4) in in + where the mismatch coefficient in the worst case is obtained from δ = δ / + δ + δ + δ. (.4) W L VGS VT VDS The second term on the riht hand side of (.4) is the mismatch induced output offset current and is denoted by i os. It consists of two components: the sinal dependent componenti δ os = Aiin and the bias dependent component i os = AJ δ. i os can be removed by employin a two phase clock that samples and holds the offset current in one clock phase and substrates the held offset current from the output current of the current amplifiers in the followin clock phase. Because i os is time-invariant, it can also be compensated effectively usin the balancin network shown in Fiure.9. To simplify analysis, we assume that all NMOS - 9 -
CHAPTER. LITERATURE SURVEY current mirrors have the same mismatch coefficient δ n and all PMOS current mirrors have the same mismatch coefficientδ p. Makin use of (.4) i = A( iin + J) + δ na ( iin ), (.43) D + J and id 4 = A[ A ( iin + J ) δ n A ( iin + J )] + δ p A[ A ( iin + J ) + δ n A ( iin + J )] A A i + A A J + A A i + A A δ J + A A δ i A A δ J, (.44) in δ n in n p in + p where nd-order terms were nelected. In a similar manner it can be shown that i A A J + A A J A A δ J. (.45) D5 δ p + n The subtraction of (.45) from (.44) yields i o = A Aiin + A A( δ n + δ p) iin. (.46) It is seen from (.46) that the output offset current is reduced from A ) A ( δ n + δ p) J + A A ( δ n + δ p iin without the balancin network to A A δ n + δ p) iin it. Fiure.0 and. compare the simulation results of the output current with and without the balancin network. It should be noted that the balancin network approach consumes additional power and silicon area. ( with Fiure.9 Balancin network for mismatch compensation of current amplifiers. - 30 -
CHAPTER. LITERATURE SURVEY Fiure.0 Simulated output current without the balancin network [6]. Fiure. Simulated output current with the balancin network [6]..3.5 POWER REDUCTION TECHNIQUES One of the drawbacks of current mirror amplifiers is their hih static power consumption, arisin mainly from the lare biasin current of the output branch. Consider the two-stae current amplifier shown in Fiure. with J c = 0. The output current is iven by io A Ai in = and the biasin current of the output branch is iven by j = A A J. Since the purpose of the second stae is to amplify i d, not I D, this suests that I D3 should be kept small. To achieve this, the dc current source J c = A c J, as shown in Fiure., is added. - 3 -
CHAPTER. LITERATURE SURVEY Fiure. Current-branchin. i The channel current of M is iven by id = A( iin + J) and that of M 3 is iven by D3 Ai in + A AC ) = ( J. If we impose A - A c = and J = A J, the output current is iven by i o = A A i in. In addition to the power consumption reduction, the chip area is also reduced due to smaller M 3 and M 4. This is echoed with an increase in the bandwidth, as is evident in Fiure.3. Fiure.3 Simulated bandwidth of amplifier with current-branchin [6]. - 3 -
CHAPTER. LITERATURE SURVEY.3.6 BANDWIDTH ENHANCEMENT TECHNIQUES Resistor series peakin, inductor series peakin, and current feedback are three effective means to improve the bandwidth of current-mode circuits. This section examines these techniques..3.6. RESISTOR SERIES PEAKING A resistor can be added between the ates of the input and output transistors of the basic current amplifier, as shown in Fiure.4, to introduce a zero to the system. The current transfer function is iven by src + m s H ( s) =. (.47) RCs Cs Cs + C m s s + s + m The two poles are at C s + CGS 4RCsC sm p, = ± ( ), (.48) RCs C s ( Cs + Cs) m and the zero is at z =. Dependin upon the value of the peakin resistor R, the RC s locations of both the zero and poles of the system differ and the amplifier exhibits distinct characteristics. () Distinct real poles When R = m, the amplifier has two distinct neative real poles located at p m = and Cs p C m =. The pole p is identical to the zero iven s by z C m = and cancels out the zero. As a result, the transfer function is simplified s to m H ( s) =. (.49) m Cs s + m - 33 -
CHAPTER. LITERATURE SURVEY As compared with the bandwidth of the basic current amplifier, the resistor series peakin with two distinct real poles boosts the bandwidth to ω = C m s. Note that if C s >> C s, the bandwidth improvement from resistive series peakin with two distinct real poles is rather small. ( Cs + Cs) Cs () Identical real poles - When R =, the circuit has two 4 C C C m s s 4 m s identical neative real poles p m, =. The bandwidth becomes Cs + Cs m ω b =. Cs Fiure.4 Basic current amplifiers with resistor series peakin. (3) Complex conjuate poles - A further increase of R will lead to a pair of complex conjuate poles. An overshoot in the frequency-domain response and rinin in the timedomain response exist. A critical point is when C C m s R = amplifier has two complex s conjuate poles that are separated by π and has a maximally flat response, called Butterworth response, with the bandwidth iven byω = b C m s. In this case, the timedomain response of the amplifier to a unit step input has an overshoot of 4.3% - 34 -
CHAPTER. LITERATURE SURVEY approximately. Fiure.5 shows the dependence of the bandwidth of the current amplifier with the resistor series peakin on the resistance of the peakin resistor. Fiure.5 Simulated frequency response of current amplifier with resistor series peakin [6]..3.6. INDUCTOR SERIES PEAKING The thermal noise of the series peakin resistor increases the total noise of the amplifier. For low-noise applications, such as the front end of GB/s transceivers and optical preamplifiers, noiseless elements, such as inductors, are preferred over noisy resistors for bandwidth enhancement. It has been seen that inductor shunt peakin can increase the bandwidth of voltae-mode circuits by as much as 70% [6]. Inductor shunt peakin technique, however, is not particularly applicable to current-mode circuits due to the existence of biasin current sources between the devices formin the dominant poles and the supply voltae. The fact that the dominant pole of the basic current amplifier is located at the ates of M and M suests that an inductor can be placed between the ates of M and M, as shown in Fiure.6, to boost bandwidth. By assumin C s >> C s we obtain the current transfer function - 35 -
CHAPTER. LITERATURE SURVEY I I o in ( s) ( s) The two poles are located at = ( m m ) C s LC s + s C s m +. (.50) p, 4L m = ( ± ). (.5) L C m s Cs Under the condition L =, the amplifier has two identical real poles p 4 m m, =. Cs Its time response is critically damped with no rinin. The bandwidth in this case is iven by C m s ω = b. When L is increased to L = Cs m, the amplifier has two π complex conjuate poles that are separated by. In this case, the response of the amplifier has a maximally flat (Butterworth) pass band with the bandwidth iven by ω = b ( C m s ). Fiure.7 shows the frequency response of the current amplifier with inductor series peakin. The attenuation rate of the response in the stop band, which is approximately -40 db/decade, is hiher as compared with that of the amplifier with resistive series peakin. This is because the former increases the bandwidth by addin a pole whereas the latter enhances the bandwidth by introducin a zero. The peakin inductor does not affect the dc characteristics of the amplifier, a similar property as that of the resistor series peakin. Fiure.6 Current amplifier with Inductor series peakin. - 36 -
CHAPTER. LITERATURE SURVEY Fiure.7 Simulated frequency response of current amplifier with inductor series peakin [6]. Fiure.8 Typical layout of square shaped spiral inductors [6]. On-chip inductors are usually implemented in either planar or stacked spiral confiurations, as shown in Fiure.8. Spiral inductors have the characteristics of a low quality factor, a low inductance, and extremely area consumin. The ohmic loss of spiral inductors, mainly due to the skin-effect induced loss at hih frequencies, is usually depicted usin a series resistor R s. Its capacitive loss, arisin from the lare capacitance between the spirals and the substrate, is represented by two shunt capacitors C ox at the - 37 -
CHAPTER. LITERATURE SURVEY terminals of the inductor. The capacitive couplin between the upper and lower spirals at the under paths and frine capacitance between neihborin spirals is characterized by C s, as shown in the simple lumped model of on-chip spiral inductors in Fiure.9. Fiure.9 Simple lumped model of on chip spiral inductors. The series resistance of the inductor behaves as a series peakin resistor and improves the bandwidth, as shown in Fiure.30. The spiral substrate shunt capacitance, however, is directly added to the total capacitance of the ates of M ~ of the current amplifier, lowerin the bandwidth, as evident in Fiure.3. Fiure.30 Simulated effect of the series resistance of series peakin inductors on the frequency response of the current amplifier [6]. - 38 -
CHAPTER. LITERATURE SURVEY Fiure.3 Simulated effect of the parasitic capacitance of series peakin inductors on the frequency response of the current amplifier [6]..3.6.3 CURRENT FEEDBACK It is well known that neative current-current feedback increases the output impedance and lowers the input impedance. To sense the output current without affectin both the dc biasin condition and the supply voltae, the current feedback mechanism shown in Fiure.3 can be used. The transfer function of the amplifier is iven by H ( s) s LC m s. (.5) m m + mf + s m + L with two poles at p 4( m + mf ) ml, = ± ml Cs. (.53) m LC s - 39 -
CHAPTER. LITERATURE SURVEY Fiure.3 Current amplifier with both current-current feedback and inductor series peakin. Fiure.33 Simulated frequency response of current amplifiers with both current-current feedback and inductor series peakin, (a) Basic current amplifier, (b) Inductor series peakin only, (c) Current-current feedback, (d) Inductor series peakin and current-current feedback [6]. - 40 -
CHAPTER. LITERATURE SURVEY π C Complex conjuate poles that are apart occurs when s L = where ( + Af ) ( W L) ( W L) A = and f ( W L) f ( W L) =. In this case, the amplifier has a maximally flat response m with the bandwidthω = b ( + Af ) C m s. The value of the series peakin inductor that Cs ives a maximally flat response is reduced from L = without the current-current m Cs feed back to L = with the current-current feedback. A smaller inductor, ( + λf ) m subsequently, a smaller chip area and less parasitic effects, is needed when currentcurrent feedback is employed. Fiure.33 shows the frequency response of the current amplifier with both inductor series peakin and current-current feedback. Fiure.34 Current amplifier with both current-current feedback and resistor series peakin. In a similar manner, it can be show that the amplifier with both resistor series peakin and current-current feedback, as shown in Fiure.34, has the current transfer function + ( ) src m s H s =. (.54) ( +, ) + s s s f s + s + s, f + m RC C C C C C RC mf s mf s + s + + + m mf m mf - 4 -
CHAPTER. LITERATURE SURVEY Assumin R mf << and C s,f << C s, we have two poles C s + Cs 4RCsC sm( + Af ) p, ±. (.55) RCsC s ( Cs + Cs) When R = C s m C s + Af, the amplifier has a maximum plat response with its bandwidthω b ( + Af ) C m s. Also, the resistance value is reduced from R = m C C s s without the current-current feedback to R = C s m C s + Af with the current-current feedback. Fiure.35 shows the current ain of the amplifiers with the resistor series peakin and current-current feedback. Fiure.35 Simulated frequency response of current amplifiers with both current-current feedback and resistor series peakin, (a) Basic current amplifier, (b) Resistor series peakin, (c) Current-current feedback, (d) Resistor series peakin and current-current feedback [6]. - 4 -
CHAPTER. LITERATURE SURVEY.3.7 DYNAMIC RANGE IMPROVEMENT TECHNIQUES The application of class-a current amplifiers is limited by the small current swin because a lare current swin would require the quiescent point to be far away from the pinch-off, resultin in a lare drain-source voltae. Fiure.36 Basic class AB current amplifiers. Fiure.37 Low-voltae class AB current amplifiers. - 43 -
CHAPTER. LITERATURE SURVEY Fiure.38 Cascode class AB current amplifiers. Fiure.39 Bootstrapped Class AB current amplifiers. To accommodate hih-current applications, class AB confiurations that employ a pair of NMOS and PMOS current mirrors activated separately are effective, as shown in Fiure.36,.37,.38 and.39. Transistors M ~ provide a low input impedance. When a - 44 -
CHAPTER. LITERATURE SURVEY lare positive input current is applied at the input (the current flows into the channel), the voltae of the input node arises sufficiently hih such that the PMOS current mirror is disabled. The input current is sensed by the NMOS current mirror. Similarly, when a lare neative current is applied to the input (the current flows away from the channel), the low voltae at the input node forces M enter the cut-off mode and the current flowin out of the input node is sourced by the PMOS current mirror. It should, however, be noted that when the amplitude of the input current is small, both the NMOS and PMOS current mirrors are activated, ivin rise to static power consumption. The dc operatin point of the class AB current amplifier is set to such that V in = V DD / and the minimum supply voltae is iven by V = V V. The low-voltae class AB DD, min T + current amplifier shown in Fiure.37 lowers the minimum supply voltae to V T. The main drawback of this current amplifier is that the quiescent currents are stronly influenced by both the threshold and supply voltaes. To minimize the effect of a finite output impedance of the precedin class AB current amplifier, cascode confiuration can be employed at both the output staes, as shown in Fiure.38. The output impedance at low frequencies is iven by r o = ( m 3 ro 3) ro 8 ( m 4ro 4) ro 0. The bootstrapped cascode class AB current amplifier is shown in Fiure.39. The bootstrapped confiuration boosts the sat output impedance to r o = A( m3 ro 3) ro 6 A( m ro 4) ro 8. The added auxiliary differential amplifiers also minimize the output error current of current mirrors M 5~6 and M 7~8 due to v DS -mismatch. - 45 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER CHAPTER 3 DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER In this work, a CMOS current operational amplifier (COA) with fully differential input and differential output has been analyzed and implemented from a differential current mirror input transimpedance stae followed by a differential output transconductance ain stae. This confiuration is the current-mode counterpart of the traditional voltae operational amplifier (VOA). The simulation results of the COA are based upon the UMC 0.8 µm CMOS process with.5 V supply voltae. The desin exhibits an open-loop differential ain of 65.38 db with the ain-bandwidth product 353.60 MHz and a settlin time of 5.90 ns. The desin and optimization uidelines of the COA have been discussed and analyzed so that they can also be applied to the desin of hih performance COA. 3. INTRODUCTION In order to achieve hih performance analo circuits in CMOS technoloy, the past few years have seen a reat shift in analo circuit desin towards representin sinals with current instead of voltae. Current-mode sinal processin is receivin considerable attention due to its potential of two conceptual advantaes over the classical voltaemode approach: hiher frequency capabilities and hiher dynamic rane. Such currentmode circuits are no loner directly restricted by the supply voltae but associated with the impedance level chosen by the desiner [8]. The desin and operation principle of the current operational amplifier can be derived from that of the voltae operational amplifier by applyin the theory of adjoint networks to obtain the same transfer function. Followin this approach, the interreciprocal network can then be used to transform almost all voltae-mode continuous time active circuits to their current-mode equivalent networks, alon with the fully differential circuit structures used in hih frequency analo sinal processin, like switched filters which have a hiher rejection capability on block-feed throuh noises and power supply variations. - 46 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER In 968, Sedra and Smith introduced a current conveyor which they implemented usin a voltae operational amplifier, complementary MOSFETs, and current mirrors. Applyin the theory of adjoint networks, the current operational amplifier (COA) replaces the VOA with a floatin current controlled current source when convertin from a voltae-mode circuit confiuration to a current-mode confiuration [8]. (a) v o A v = = Ai = vi i i o i (b) (c) (d) A vd v = v o d = A id io = ( i i) o Fiure 3. Interreciprocal network of VOA to COA. The equivalent circuit of a voltae operational amplifier is shown in Fiure 3.(a). Accordin to the adjoint network theory, the voltae controlled voltae source is replaced by a current controlled current source and the input/output terminals are interchaned. - 47 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER The resultin equivalent block is a current operational amplifier and is shown in Fiure 3.(b). A fully differential VOA, shown in Fiure 3.(c), is transformed to the fully differential COA as shown in Fiure 3.(d). Due to a differential-input current-controlled floatin current source, the COA exhibits ideally infinite differential current ain, output impedance, zero common mode current ain and differential input impedance. Thus, the COA performs the current-mode counterpart of the conventional VOA. The transconductance stae is realized in many different ways, i.e. a differential output current conveyor usin multiple output current mirrors. In this work, a CMOS differential-input, differential-output current operational amplifier for an equally useful eneral sinal processin element is proposed and analyzed. It is confiured from an input transimpedance stae followed by a transconductance output stae. Section 3. shows the circuit confiuration and the performance analysis of the proposed COA. Section 3.3 presents the closed-loop operation of the proposed COA. Desin considerations of COA have been discussed in section 3.4. Aspect ratio of the transistors and the layout of the desin have been iven in section 3.5 and 3.6 respectively. 3. CURRENT-MODE OPERATIONAL AMPLIFIER (COA) The aim is to desin a current operational amplifier with a differential input and a differential output, where the two output terminals are hih impedance nodes with a current source/sink capability. This is a versatile amplification scheme with floatin input and output terminals, which provides maximum freedom to the desiner to compose practically any kind of application. Various current-mode buildin blocks have been proposed for active networks and analo computational applications. The applications of the COA include the implementation of instrumentation amplifier, current comparator with hysteresis, yrator, and differential switched-current filter [8]. In this work, the current operational amplifier is implemented usin a transimpedance input stae followed by a transconductance output stae. The circuit schematic of the COA is shown in Fiure 3.. An output stae providin the complementary output is the differential floatin - 48 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER Fiure 3. Transistor diaram of Current Operational Amplifier. Fiure 3.3 Detailed transistor diaram of Current Operational Amplifier. - 49 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER current source (FCS) described by Arbel and Goldminz. Essentially, this stae is just two matched CMOS inverters biased by a constant supply current and operated as an analo transconductance stae. 3.. OPEN-LOOP GAIN, COMMON MODE REJECTION RATIO (CMRR), INPUT OFFSET CURRENT Extendin the lare sinal analysis for the current operational amplifier in Fiure 3., calculatin the relation of the input node currents, i and i to the output node (A) current in the transimpedance stae, and the input node (A) current to the output node currents, i out and i out, in the transconductance stae (inorin the I SS and I SS bias current effect in Eq. (3.), we find i out = i out = [( λ I = [( I bias bias λ λ I + i ) λ ( I 3 bias bias + i λ + λλ3 ) ( i ) λ λ ] R 3 i A m4 + m6 i ) + ( λ λ λ )( 3 + i )] R A m4 + =offset + differential ain + common mode ain, (3.) where I bias, I bias are bias currents. λ = current mirror ratio function of M 0, to M,3 λ = current mirror ratio function of M 4,5 to M 6,7 λ 3 = current mirror ratio function of M 8,9 to M 0, m6 m m7 R = A, (3.) ds3 ds ds6 ds7 so I off equivalent input offset current I off = ( λ I λ λ I ), (3.3) bias 3 bias inorin I SS and I SS. A dm differential mode current ain is i = i out Adm d - 50 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER λ + λλ3 = R m 4 + m6 A. (3.4) i d differential mode current input i d = ( i ) i. (3.5) i c common mode current input i + = i i c. (3.6) A cm common mode current ain of stae V = RA. (3.7) A A cm = ( λ λλ3 ) i + i A cm common mode current ain of stae iout + iout = A = cm, (3.8) VA 4 RSS RSS where R SS, R SS are output resistances of the current sources I SS and I SS, respectively. A CM total common mode current ain [8] A CM = A cm A cm i = out + i i + i out RA = ( λ λλ3). (3.9) 4 RSS RSS We also find the common mode rejection ratio (defined as the differential ain divided by common ain) iven by ( λ + λλ3) CMRR = ( m 4 + ( λ λ λ ) 3 m6 )( R SS R SS ). (3.0) - 5 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER It is seen that an arbitrarily hih CMRR can be achieved throuh the use of a current source. The impedance R A is increased by employin a hih swin cascode current mirror. So, the current ain is therefore increased by tradin of power dissipation and chip area [9]. 3.. FREQUENCY RESPONSE, GAIN-BANDWIDTH AND STABILITY The confiuration shown in Fiure 3. has one hih impedance node A in the sinal path. It creates a dominant pole in the frequency response iven by f pd =, (3.) π R C A A Cs 4 Cs 6 C A = Cd + Cd 7 + Cd4 + Cd6 + +, (3.) where C A is the total parasite capacitance of node A, and is dominated by the ate source capacitances C s4 and C s6 of the transconductance stae. The first non-dominant pole is typically caused by the current mirror stae which contributes at anular frequencies of the order of m /C s. In addition, the parasite capacitances (C bd ) influence the dominant and the non-dominant poles that can be reduced by usin an optimized transistor layout style, e.. multi-finer structure for the ate. The ain-bandwidth product is λ + λλ3 GBW = ( m 4 + πc A m6 ). (3.3) In a voltae operational amplifier, the compensation capacitance separates the dominant and non-dominant poles to provide the desired unity ain phase marin, while in the current operational amplifier, additional capacitance could be added at node A [8]. 3..3 INPUT AND OUTPUT IMPEDANCE The input impedance is R in = +. (3.4) m m9-5 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER The output impedance of the COA is the conductance of the transconductance stae. It can be increased usin the reulated cascode scheme [8]. It is iven by [( ) ( )] + [( ) ( ] R. (3.5) out = ds4 ds6 ds5 ds7 ) 3..4 INPUT COMMON MODE RANGE (ICMR) For bias current, I bias = I bias = I, the equal positive and neative common mode ranes requires that (3.6) must be fulfilled [9]. V DD VTp I =. (3.6) / 4 [ ( ) ] / K n W L n + [ K p ( W L) p ] 3..5 POWER SUPPLY REJECTION RATIO (PSRR) The power supply rejection ratio is PSSR, vdd ( + + nodei scnodei ) ( nodei scnodei ) + + ds7 m7 ds6 + sc d 7 ds0 m0 ds + sc d0 (3.7) The PSRR,vss can be derived in the same manner. It is clear that the power supply rejection ratio for the COA has the dimension of a resistor [8]. 3..6 NOISE PERFORMANCE The RMS value of the equivalent input noise current of the COA is n5 m4 I ni = mn Vnx mp V + ny + ( Vn 4 + V x= 0,,,3,8,9,0, y= 4,5,6,7 RA ( m4 + m6 ) ) (3.8) - 53 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER 3.3 CLOSED-LOOP CURRENT OPERATIONAL AMPLIFIER Invokin duality, Fiure 3.4 shows examples to investiate the closed-loop operation of the current operational amplifier. As shown in Fiure 3.4, the closed-loop ain depends on the resistor ratio and not the open-loop ain characteristics. Neative feedback around the COA produces an accurate closed-loop current ain insensitive to temperature, power supply and process variations. (a) (b) i out = i v o = ( R R ) vi (b) (d) ( i out i ) + ( R R ) = ( iout iout) = R R Fiure 3.4 Basic feedback controlled current amplifiers in (a) unity current ain, (b) voltae ain, (c) non-invertin, (d) invertin confiurations. - 54 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER Thus, it has a constant ain-bandwidth independent of the open-loop current ain in a closed-loop confiuration. Consequently, this circuit confiuration is suitable for hih frequency applications. An open-loop COA can be used as a current comparator in which the resolution is determined by the bias current and the open-loop current ain [8,]. 3.4 CURRENT OPERATIONAL AMPLIFIER DESIGN CONSIDERATIONS In order to tailor the current operation amplifier to a particular application, a trade-off exists between circuit performances, the ain, the bandwidth, the noise, etc. These conditions often conflict with one another, and are also very sensitive to process variations. The procedures outlined in this section ive an indication of how to desin the COA efficiently to satisfy these performance requirements. Fiure 3.5 Low-Voltae Current Mirror. The low voltae cascode current mirror is shown in Fiure 3.5. We assume that the mirror transistors M and M have identical aspect ratio, i.e. A M = W /L = W /L where W, W, L, and L are the transistor channel widths and lenths for transistors M and M, respectively. Similarly, M 3 and M 4 are assumed to have the same aspect ratio, A C = W 3 /L 3 = W 3 /L 4. The aspect ratio A M may be different from the aspect ratio A C. In the analysis of the dynamic rane we use the standard Shichman-Hodes transistor model for the transistor in the saturation reion and we nelect the bulk-effect [0]. - 55 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER With the input current I in we find the ate-source voltaes: V V V V I in s = T + (3.9) KAM V I in s3 = T + (3.0) KAC I in ds = VBC Vs3 = VBC VT (3.) KAC Iin V ds3 = Vs VBC + ( + ) (3.) KA A A C M C where V T is the transistor threshold voltae, V BC is the cascode transistor ate voltae, and K is the transistor transconductance parameter. Requirin V s V T V ds for both M and M 3 results in: I K in ( A M + ) A C + V T V BC (3.3) V BC I in VT + (3.4) KAM Eq. (3.3) ensures saturation of M and determines the maximum value of I in, for a iven value of the cascode bias voltae V BC. We find K A A C M I in,max = AM ( VBC VT ) (3.5) + AC AM Eq. (3.4) ensures saturation of M 3 and determines the minimum value of I in. We find I K = AM (3.6) in, min ( VBC V T ) In a practical desin procedure (3.6) can be used to determine the maximum value of the bias voltae which will ensure saturation of M 3, even at the minimum value of input current, and (3.5) can then be used to determine values of A C and A M which will ensure saturation of M, even at the maximum value of input current. - 56 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER In the important special case of I in,min = 0 we find from (3.6) V V. From (3.5) we then find the followin desin constraint on A C and A M : BC T A A A I V C M in,max M + A A T K C M (3.7) Assumin as a typical case W = W 3 and L = L 3, i.e. identical aspect ratios for the mirror transistors and the cascode transistors, we find A W 8Iin,max = AC = (3.8) L V K M T In this case the effective ate-source voltae of the mirror transistors M and M is Iin VT Iin V s VT = = (3.9) KA I M in,max Obviously, in this case the minimum output voltae of the current mirror is V = out, min = VBC VT VT (3.30) 3.5 ASPECT RATIOS OF THE TRANSISTORS IN THE DESIGN Based on the procedure discussed in section 3.4 the aspect ratios of the transistors in Fiure 3. are calculated as follows: Table 3. Aspect ratios of Transistors used in the desin. Device Width/Lenth in (µm/µm) Device M 0 35/0.5 M 0 35/0.5 M 35/0.5 M 35/0.5 M 35/0.5 M 5/0.5 M 3 35/0.5 M 3 5/0.5 Width/Lenth in (µm/µm) M 4 5/0.5 M 4 66/0.5-57 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER Device Width/Lenth in (µm/µm) Device Width/Lenth in (µm/µm) M 5 5/0.5 M 5 66/0.5 M 6 5/0.5 M 6 45/0.5 M 7 5/0.5 M 7 45/0.5 M 8 35/0.5 M 8 50.98/0.5 M 9 35/0.5 M 9 83.75/0.5 3.6 PHYSICAL LAYOUT DESIGN OF CURRENT OPERATIONAL AMPLIFIER The physical layout desin of Current operational amplifier has been done in standard UMC 0.8 µm CMOS process technoloy. The VIRTUOSO layout editor tool by CADENCE was used for the desin of physical layout structure. The layout is shown in the Fiure 3.6. To verify that the layout fulfills all electrical and eometric rules a Desin Rule Check (DRC) proram is used. ASSURA tool was used for DRC checks. This tool marks any error in the desin and can also extracts (i.e. convert to a netlist) the layout so that it can be simulated. The extracted layout view is shown in the Fiure 3.7. Basic Desin Rules are summarized below: Metal to metal spacin 0.4 um Minimum contact size 0.4 um*0.4 um Poly to poly spacin 0.4 um Poly to metal spacin 0.8/0.00 um Contact overlap to p+ diffusion 0. um Metal width 0.4 um Poly extension beyond active 0. um Minimum contact spacin 0.6 um N well overlap p+ diffusion 0.43 um Diffusion contact to poly spacin 0.5 um Minimum p+ implant overlap p+ diffusion 0. um Poly width 0.8 um Minimum poly extension on to field reion 0. um Minimum poly ate to field ede spacin 0.8 um - 58 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER Fiure 3.6 Layout of Current Operational Amplifier. - 59 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER Fiure 3.7 Extracted View of the Layout. - 60 -
CHAPTER 3. DESIGN AND ANALYSIS OF CURRENT-MODE OPERATIONAL AMPLIFIER Poly contact to diffusion ede spacin Minimum poly overlap contact Minimum metal area Gate poly spacin over diffusion Minimum metal width Metal and metal overlap over via Minimum equal potential N-well spacin Minimum non equal potential.8 V N well spacin 0.8 um 0. um 0.764 um*um 0.34 um 0.8 um 0.08 um 0 um or >=0.9 um.5um - 6 -
CHAPTER 4. SIMULATIONS AND RESULTS CHAPTER 4 SIMULATIONS AND RESULTS In this chapter, schematic of the fully differential current-mode operational amplifier and extracted view (netlist) of its layout have been tested for various parameters of current operational amplifier. The simulations with schematic and extracted view of layout are also called the pre-layout and post-layout simulations respectively. VIRTUOSO schematic composer and layout editor tools were used for capturin schematic and layout drawin respectively. The circuit was simulated usin SPECTRE tool by CADENCE. The circuit desin is based upon the parameters of the UMC 0.8 µm CMOS process technoloy. The technoloy uses the SPICE BSIM3v3 Version 3. model parameters. 4. TEST RESULTS In this section, simulation results with schematic and extracted view of layout have been discussed. Finally with post-layout simulation at typical corner the desin provides a ain of 65.38 db with a common mode rejection ratio of 73.59 db. The 3 db frequency and unity ain frequency are 0.0 khz and 353.60 MHz respectively. Slew rate was obtained to be 37.7 µa/ns. Phase marin was found to be 0 53.60 makin desin relatively stable. The power dissipation was equal to 5.7 mw. The values of load resistance and compensatin capacitance are iven in the table below. Table 4. Load resistance and compensatin capacitance Pre-layout Post-layout Load Resistance, R L ( Ω ) Compensatin Capacitance, C c (pf) 3.5493 The value of capacitance in the Table 4. are different for the two simulations because the circuit layout has been optimized for reasonable phase marin. - 6 -
CHAPTER 4. SIMULATIONS AND RESULTS 4.. CURRENT-GAIN, 3-dB FREQUENCY, UNITY GAIN FREQUENCY AND PHASE MARGINE The differential ain, 3-dB frequency, unity ain frequency and phase marin are obtained from ain and phase plot. The circuit is shown in the Fiure 4.. The circuit is in open-loop confiuration and AC current sinal is applied at the input. The pre-layout and post-layout ain and Phase plots at typical corner are shown in the Fiure 4. and 4.3 respectively. Fiure 4. Schematic for the frequency response of the open-loop current operational amplifier. The AC results at different corners of simulations are iven below: Table 4. Pre-layout AC results at different process corners of simulations. Process Corners Specifications tt ff ss snfp fnsp Differential Gain (db) 64.50 6.5 66.54 6.67 66.85 3 db Frequency (khz) 6. 376.4 33.3 3.6 6.6 Unity Gain Frequency (MHz) 343.6 4. 75. 354. 330.6 Phase Marin(deree) 55.90 54.60 60.56 56.44 57.4-63 -
CHAPTER 4. SIMULATIONS AND RESULTS Fiure 4. Pre-layout frequency response of the current operational amplifier at typical corner. Fiure 4.3 Post-layout frequency response of the current operational amplifier at typical corner. - 64 -
CHAPTER 4. SIMULATIONS AND RESULTS Table 4.3 Post-layout AC results at different process corners of simulations Process Corners Specifications tt ff ss snfp fnsp Differential Gain (db) 65.38 63.57 66.46 6.75 68.0 3 db Frequency (khz) 0. 34. 5.83 338.68 6.6 Unity Gain Frequency (MHz) 353.6 445.8 88.4 36. 353.97 Phase Marin(deree) 53.60 50.40 56.43 5.99 53.89 The effect of temperature on these parameters is iven below in the followin table. Table 4.4 Post-layout AC results at different temperatures at typical corner Temperature Specifications -0 0 7 0 80 0 Differential Gain (db) 66.79 65.38 6.9 3 db Frequency (khz) 68. 0. 34.45 Unity Gain Frequency (MHz) 39.6 353.6 338. Phase Marin(deree) 58.90 53.60 50.78 The result shows that the desin has a very hih ain and there is very less effect of temperature variation on its ain. The hih ain can be used to obtain an accurate ain in closed-loop operation. 4.. TRANSIENT RESULTS The circuit for transient analysis is shown in Fiure 4.4 and 4.5. Since the ain of the amplifier is very hih hence the open-loop confiuration can be used as a current comparator in which the resolution is determined by the biasin current and the open-loop current ain. Hence transient simulations in open-loop and unity ain confiuration both are shown below in Fiure 4.6, 4.7, 4.8, and 4.9. - 65 -
CHAPTER 4. SIMULATIONS AND RESULTS Fiure 4.4 Schematic for transient analysis of the open-loop current operational amplifier. Fiure 4.5 Schematic for transient analysis of current operational amplifier confiured as unity ain buffer. - 66 -
CHAPTER 4. SIMULATIONS AND RESULTS Fiure 4.6 Pre-layout transient response of current operational amplifier in open loop confiuration at typical corner. Fiure 4.7 Pre-layout transient response of current operational amplifier in unity ain confiuration at typical corner. - 67 -
CHAPTER 4. SIMULATIONS AND RESULTS Fiure 4.8 Post-layout transient response of current operational amplifier in open-loop confiuration at typical corner. Fiure 4.9 Post-layout transient response of current operational amplifier in unity ain confiuration at typical corner. - 68 -