l Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 175 C Operating Temperature l Fast Switching G l Fully Avalanche Rated l Lead-Free Description Advanced HEXFET Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low onresistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. IRF530NSPbF IRF530NLPbF HEXFET Power MOSFET D S PD - 950 V DSS = 0V R DS(on) = 90mΩ I D = 17A The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF530NL) is available for low-profile applications. D 2 Pak IRF530NSPbF TO-262 IRF530NLPbF Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, @ V 17 I D @ T C = 0 C Continuous Drain Current, @ V 12 A I DM Pulsed Drain Current 60 P D @T A = 25 C Power Dissipation 3.8 W P D @T C = 25 C Power Dissipation 70 W Linear Derating Factor 0.47 W/ C Gate-to-Source Voltage ± 20 V I AR Avalanche Current 9.0 A E AR Repetitive Avalanche Energy 7.0 mj dv/dt Peak Diode Recovery dv/dt ƒ 7.4 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (1.6mm from case ) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 2.15 C/W R θja Junction-to-Ambient (PCB Mounted,steady-state)** 40 www.irf.com 1 03//04
Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 0 V = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.11 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 90 mω = V, I D = 9.0A (th) Gate Threshold Voltage 2.0 4.0 V V DS =, I D = 250µA g fs Forward Transconductance 12 S V DS = 50V, I D = 9.0A I DSS Drain-to-Source Leakage Current 25 V µa DS = 0V, = 0V 250 V DS = 80V, = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 0 = 20V na Gate-to-Source Reverse Leakage -0 = -20V Q g Total Gate Charge 37 I D = 9.0A Q gs Gate-to-Source Charge 7.2 nc V DS = 80V Q gd Gate-to-Drain ("Miller") Charge 11 = V, See Fig. 6 and 13 t d(on) Turn-On Delay Time 9.2 V DD = 50V t r Rise Time 22 I D = 9.0A ns t d(off) Turn-Off Delay Time 35 R G = 12Ω t f Fall Time 25 = V, See Fig. Between lead, L D Internal Drain Inductance 4 5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7 5 and center of die contact C iss Input Capacitance 920 = 0V C oss Output Capacitance 130 V DS = 25V C rss Reverse Transfer Capacitance 19 pf ƒ = 1.0MHz, See Fig. 5 E AS Single Pulse Avalanche Energy 340 93 mj I AS = 9.0A, L = 2.3mH Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 17 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 60 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 9.0A, = 0V t rr Reverse Recovery Time 93 140 ns T J = 25 C, I F = 9.0A Q rr Reverse Recovery Charge 320 480 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) D S Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11) Starting T J = 25 C, L = 2.3mH R G = 25Ω, I AS = 9.0A, =V (See Figure 12) ƒ I SD 9.0A, di/dt 4A/µs, V DD V (BR)DSS, T J 175 C Pulse width 400µs; duty cycle 2%. This is a typical value at device destruction and represents operation outside rated limits. This is a calculated value limited to T J = 175 C. Uses IRF530N data and test conditions. **When mounted on 1" square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994 2 www.irf.com
I D, Drain-to-Source Current (A) 0 VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, Drain-to-Source Current (A) 0 VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 1 T J = 25 C 0.1 1 0 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 175 C 1 0.1 1 0 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 0 T J = 25 C T J = 175 C V DS= 50V 20µs PULSE WIDTH 4.0 5.0 6.0 7.0 8.0, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.5 I D = 15A 3.0 2.5 2.0 1.5 1.0 0.5 = V 0.0-60 -40-20 0 20 40 60 80 0 120 140 160 180 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
I D, Drain-to-Source Current (A) IRF530NS/LPbF C, Capacitance (pf) 1600 VGS = 0V, f = 1MHz Ciss = Cgs Cgd, C ds SHORTED Crss = Cgd Coss = Cds Cgd 1200 C iss 800 C oss 400 C rss 0 1 0 V DS, Drain-to-Source Voltage (V), Gate-to-Source Voltage (V) 20 16 12 8 4 I = D 9.0A V DS = 80V V DS = 50V V DS = 20V FOR TEST CIRCUIT SEE FIGURE 13 0 0 20 30 40 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 0 1 T J = 175 C T J = 25 C = 0 V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 V SD,Source-to-Drain Voltage (V) 00 0 1 0.1 Tc = 25 C Tj = 175 C Single Pulse OPERATION IN THIS AREA LIMITED BY R DS (on) 0µsec 1msec msec 1 0 00 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
20 V DS R D I D, Drain Current (A) 16 12 8 4 0 25 50 75 0 125 150 175 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% R G Pulse Width 1 µs Duty Factor 0.1 % D U T Fig a Switching Time Test Circuit % t d(on) t r t d(off) t f Fig b Switching Time Waveforms - V DD Thermal Response (Z thjc ) 1 0.1 D = 0.50 0.20 0. 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 0.01 2. Peak T J = P DM x Z thjc TC 0.00001 0.0001 0.001 0.01 0.1 t 1, Rectangular Pulse Duration (sec) PDM t1 t2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
R G V DS 20V tp L D.U.T IAS 0.01Ω Fig 12a Unclamped Inductive Test Circuit tp 15V DRIVER - V DD A V (BR)DSS E AS, Single Pulse Avalanche Energy (mj) 200 160 120 80 40 TOP BOTTOM I D 3.7A 6.4A 9.0A 0 25 50 75 0 125 150 175 Starting T, Junction Temperature ( J C) Fig 12c Maximum Avalanche Energy Vs Drain Current I AS Fig 12b Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF Q GS Q GD D.U.T. V - DS V G 3mA Charge Fig 13a Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D U T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D U T - Device Under Test - V DD * Reverse Polarity of D U T for P-Channel Driver Gate Drive Period P.W. D = P.W. Period [ =V ] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Applied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** = 5 0V for Logic Level and 3V Drive Devices Fig 14 For N-channel HEXFET power MOSFETs www.irf.com 7
D 2 Pak Package Outline Dimensions are shown in millimeters (inches) D 2 Pak Part Marking Information (Lead-Free) T H IS IS AN IR F 530S WIT H LOT CODE 8024 AS S E MB LE D ON WW 02, 2000 IN THE ASSEMBLY LINE "L" N ote: "P " in as s embly line pos ition indicates "L ead-f ree" OR INT E R NAT IONAL R E CT IF IE R LOGO AS S E MB L Y LOT CODE F530S PART NUMBER DAT E CODE YE AR 0 = 2000 WEEK 02 LINE L IN T E R N AT ION AL RECTIFIER LOGO AS S E MB L Y LOT CODE F 530S PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 0 = 2000 WEEK 02 A = ASSEMBLY SITE CODE 8 www.irf.com
TO-262 Package Outline IGBT 1- GATE 2- COLLECTOR 3- EMITTER TO-262 Part Marking Information E XAMPLE : THIS IS AN IRL33L LOT CODE 1789 AS SEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" OR INTERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = ASSEMBLY SITE CODE www.irf.com 9
D 2 Pak Tape & Reel Infomation Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4. (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065).90 (.429).70 (.421) 11.60 (.457) 11.40 (.449) 16. (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information.03/04 www.irf.com