Features and Benefits Two matched Hall effect switches on a single substrate Sensor Hall element spacing approximately mm Superior temperature stability. to operation Integrated ESD diode from OUTPUT and VCC pins to GND High-sensitivity switchpoints Robust structure for EMC protection Solid-state reliability Package: pin SOIC (suffix L), and pin SIP (suffix K) Description The A is a dual output-channel, bipolar switch with each channel comprising a separate complete Hall-effect sensor circuit with dedicated Hall element and separate digital output for speed and direction signal processing capability. The independent Hall elements (E integrated with OUTPUTA, and E integrated with OUTPUTB) are photolithographically aligned to better than μm. Maintaining this accurate mechanical location between the two active Hall elements eliminates the major manufacturing hurdle encountered in fine-pitch detection applications. The A is a highly sensitive, temperature-stable magnetic sensing device, which is ideal for use in ring magnetbased speed and direction systems used in harsh automotive and industrial environments. The A contains two independent Hall effect switches, and has a monolithic IC that accurately locates the two Hall elements, E and E, approximately mm apart. The digital outputs are 9º out of phase so that the outputs are in quadrature, with the proper ring magnet design. This allows for easy processing of speed and direction signals. Extremely low-drift amplifiers guarantee symmetry between the switches to maintain signal Continued on the next page Not to scale Typical Application VOUTPUTB VOUTPUTA OUTPUTA V Supply VCC A OUTPUTB Ω GND. uf Using unregulated supply ADS-Rev.
Description (continued) quadrature. The patented chopper stabilization technique cancels offsets in each channel, and provides stable operation over the operating temperature and voltage ranges. An on-chip regulator allows the use of this device over a wide operating voltage range. Post-assembly factory programming provides sensitive switchpoints that are symmetrical between the two switches. The A is available in a plastic -pin SOIC surface mount package (L) and a plastic -pin SIP (K), both in two operating temperature ranges. Each package is available in a lead (Pb) free version with % matte tin plated leadframe. Selection Guide Part Number Packing * Mounting Ambient, T A AEK-T Bulk, pieces/bag AEKTN-T -in. reel, pieces/reel -pin SIP through hole AEL-T Bulk, pieces/bag AELTR-T -in. reel, pieces/reel -pin SOIC surface mount ºC to ºC ALK-T Bulk, 9 pieces/bag ALKTN-T -in. reel, pieces/reel -pin SIP through hole ALL-T Bulk, pieces/bag ALLTR-T -in. reel, pieces/reel -pin SOIC surface mount ºC to ºC * Contact Allegro for additional packing options. Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Supply Voltage V CC. V Reverse Battery Voltage V RCC V Output Off Voltage V OUTPUT V CC V Output Sink Current I OUTPUT(Sink) Internally Limited Magnetic Flux Density B Unlimited Range E to ºC Operating Ambient Temperature T A Range L to ºC Maximum Junction Temperature T J (max) ºC Storage Temperature T stg to ºC Northeast Cutoff, Box Worcester, Massachusetts - () -
Functional Block Diagram VCC Programmable Trim Regulator Bits Channel A Bits Hall Element E Dynamic Offset Cancellation Amp Sample and Hold Low- Pass Filter Output Drive OUTPUTA Channel B Bits Hall Element E Dynamic Offset Cancellation Amp Sample and Hold Low- Pass Filter Output Drive OUTPUTB GND Package K E E Package L E E Terminal List Table Pin Number Package K Package L Name Function VCC Connects power supply to on-chip voltage regulator OUTPUTA Output from E via fi rst Schmitt circuit OUTPUTB Output from E via second Schmitt circuit GND Terminal for ground connection - NC No connection Northeast Cutoff, Box Worcester, Massachusetts - () -
OPERATING CHARACTERISTICS Valid over operating temperature ranges unless otherwise noted; typical data applies to V CC = V, and T A = ºC Characteristic Symbol Test Conditions Min. Typ. Max Units ELECTRICAL CHARACTERISTICS Supply Voltage V CC Operating; T A C. Output Leakage Current I OUTPUT(OFF) Either output < μa Output Rise Time t r C LOAD = pf, R LOAD = Ω. μs Output Fall Time t f C LOAD = pf, R LOAD = Ω. μs Supply Current I CC(OFF) B < B RP(A),B < B RP(B).. ma I CC(ON) B > B OP(A),B > B OP(B).. ma Low Output Voltage V OUTPUT(ON) Both outputs; I OUTPUT(SINK) = ma; B > B OP(A), B > B OP(B) mv Output Sink Current I OUTPUT(SINK) ma Output Sink Current, Continuous I OUTPUT(SINK)C T J < T J(max),V OUTPUT = V ma Output Sink Current, Peak I OUTPUT(SINK)P t < seconds ma Chopping Frequency f C khz TRANSIENT PROTECTION CHARACTERISTICS Supply Zener Voltage V Z I CC = ma V Supply Zener Current I Z V S = V 9. ma Reverse-Battery Current I RCC V RCC =, T J < T J(max) ma Continued on the next page... Northeast Cutoff, Box Worcester, Massachusetts - () -
OPERATING CHARACTERISTICS (continued) Valid over operating temperature ranges unless otherwise noted; typical data applies to V CC = V, and T A = ºC Characteristic Symbol Test Conditions Min. Typ. Max Units MAGNETIC CHARACTERISTICS, K Package Operate Point: B > B OP B OP(A), B OP(B) G Release Point: B < B RP B RP(A), B RP(B) G Hysteresis: B OP(A) B RP(A), B OP(B) B RP(B) B HYS(A), B HYS(B) G Symmetry: Channel A, Channel B, B OP(A) + B RP(A), B OP(B) + B RP(B) SYM A, SYM B G Operate Symmetry: B OP(A) B OP(B) SYM AB(OP) G Release Symmetry: B RP(A) B RP(B) SYM AB(RP) G MAGNETIC CHARACTERISTICS, L Package Operate Point: B > B OP B OP(A), B OP(B) G Release Point: B < B RP B RP(A), B RP(B) G Hysteresis: B OP(A) B RP(A), B OP(B) B RP(B) B HYS(A), B HYS(B) G Symmetry: Channel A, Channel B, B OP(A) + B RP(A), B OP(B) + B RP(B) SYM A, SYM B G Operate Symmetry: B OP(A) B OP(B) SYM AB(OP) G Release Symmetry: B RP(A) B RP(B) SYM AB(RP) G When operating at maximum voltage, never exceed maximum junction temperature, T J(max). Refer to power derating curve charts. Device will survive the current level specifi ed, but operation within magnetic specifi cation cannot be guaranteed. Short circuit of the output to VCC is protected for the time duration specifi ed. Maximum specifi cation limit is equivalent to I CC(max) + ma. Magnetic fl ux density, B, is indicated as a negative value for north-polarity magnetic fi elds, and as a positive value for south-polarity magnetic fi elds. This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the fi eld is indicated by the absolute value of B, and the sign indicates the polarity of the fi eld (for example, a G fi eld and a G fi eld have equivalent strength, but opposite polarity). EMC Contact Allegro MicroSystems for EMC performance. Northeast Cutoff, Box Worcester, Massachusetts - () -
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance R θja Package L- pin, -layer PCB with copper limited to solder pads ºC/W Package K, -layer PCB with copper limited to solder pads ºC/W *Additional thermal data available on the Allegro Web site. Package L- pin, -layer PCB based on JEDEC standard ºC/W Power Derating Curve Maximum Allowable 9 9 Package L, -layer PCB (R θja = ºC/W) Package L, -layer PCB (R θja = ºC/W) Package K, -layer PCB (R θja = ºC/W) V CC(max) V CC(min) Temperature (ºC) Power Dissipation, PD (mw) 9 9 Power Dissipation versus Temperature Package L, -layer PCB (R θja =ºC/W) PackageL,-layer PCB (R θja = ºC/W) Package K, -layer PCB (R θja = ºC/W) Temperature, TA ( C) Northeast Cutoff, Box Worcester, Massachusetts - () -
Functional Description Chopper-Stabilized Technique When using Hall effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall device. This makes it difficult to process the signal and maintain an accurate, reliable output over the specified temperature and voltage range. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. The patented Allegro technique, dynamic quadrature offset cancellation, removes key sources of the output drift induced by thermal and mechanical stress. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetically induced signal in the frequency domain through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetically-induced signal to recover its original spectrum at the baseband level, while the dc offset becomes a high-frequency signal. Then, using a low-pass filter, the signal passes while the modulated dc offset is suppressed. The chopper stabilization technique uses a khz high-frequency clock. The Hall element chopping occurs on each clock edge, resulting in a khz chop frequency. This high-frequency operation allows for a greater sampling rate, which produces higher accuracy and faster signal processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stress. The disadvantage to this approach is that jitter, also known as repeatability, can be induced on the output signal. The sample-andhold process, used by the demodulator to store and recover the signal, can slightly degrade the signalto-noise ratio. This is because the process generates replicas of the noise spectrum at the baseband, causing a decrease in jitter performance. However, the improvement in switchpoint performance, resulting from the reduction of the effects of thermal and mechanical stress, outweighs the degradation in the signal-to-noise ratio. This technique produces devices that have an extremely stable quiescent Hall element output voltage, are immune to thermal stress, and have precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset and lownoise amplifiers in combination with high-density logic integration and sample-and-hold circuits. This process is illustrated in the following diagram. Regulator Amp Sample and Hold Low- Pass Filter Chopper stabilization circuit (dynamic quadrature offset cancellation) Northeast Cutoff, Box Worcester, Massachusetts - () -
Typical Applications Operation V+ V OUTPUT(OFF) V OUTPUT Switch to High Switch to Low V OUTPUT(ON)(sat) B RP B OP B+ B HYS Output voltage in relation to sensed magnetic fl ux density. Output on each channel independently follows the same pattern of transition through B OP followed by transition through B RP. Channel A Magnetic Field at Hall Element E Channel B Magnetic Field at Hall Element E Channel A Output Signal at OUTPUTA Channel B Output Signal at OUTPUTB Quadrature output signal confi guration. The outputs of the two output channels have a phase difference of 9º when used with a properly designed magnet that has an optimal pole pitch of twice the Hall element spacing of. mm. Northeast Cutoff, Box Worcester, Massachusetts - () -
Typical Applications Circuits This device requires minimal protection circuitry during operation with a low-voltage regulated line. The on-chip voltage regulator provides immunity to power supply variations between. and. Because the device has open-drain outputs, pull-up resistors must be included. If protection against coupled and injected noise is required, then a simple low-pass filter on the supply (RC) and a filtering capacitor on each of the outputs may also be needed, as shown in the unregulated supply diagram. For applications in which the device receives its power from unregulated sources, such as a car battery, full protection is generally required to protect the device against supply-side transients. Specifications for such transients vary for each application, so the design of the protection circuit should be optimized for each application. For example, the circuit shown in the unregulated supply diagram includes a Zener diode that offers high voltage load-dump protection and noise filtering by means of a series resistor and capacitor. In addition, it includes a series diode that protects against high-voltage reverse battery conditions. VOUTPUTB VOUTPUTA OUTPUTA V Supply VCC A OUTPUTB. uf GND Regulated supply VOUTPUTB VOUTPUTA OUTPUTA V Supply VCC A OUTPUTB Ω GND. uf Unregulated supply Northeast Cutoff, Box Worcester, Massachusetts - () - 9
Typical Thermal Performance The device must be operated below the maximum junction temperature of the device, T J(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating T J. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, R θja, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, R θjc, is relatively small component of R θja. Ambient air temperature, T A, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, P D ), can be estimated. The following formulas represent the fundamental relationships used to estimate T J, at P D. P D = V IN I IN () ΔT = P D R θja () T J = T A + ΔT () Example: Reliability for V CC at T A = C, package L, using minimum-k PCB Observe the worst-case ratings for the device, specifically: R θja = C/W, T J(max) = C, V CC(max) =, and I CC(max) = ma. Calculate the maximum allowable power level, P D(max). First, invert equation : ΔT max = T J(max) T A = C C = C This provides the allowable increase to T J resulting from internal power dissipation. Then, invert equation : P D(max) = ΔT max R θja = C C/W = mw Finally, invert equation with respect to voltage: V CC(est) = P D(max) I CC(max) = mw ma = The result indicates that, at T A, the application and device can dissipate adequate amounts of heat at voltages V CC(est). Compare V CC(est) to V CC(max). If V CC(est) V CC(max), then reliable operation between V CC(est) and V CC(max) requires enhanced R θja. If V CC(est) V CC(max), then operation between V CC(est) and V CC(max) is reliable under these conditions. For example, given common conditions such as: T A =, V CC = V, I CC = ma, and R θja = C/W, then: P D = V CC I CC = V ma = mw ΔT = P D R θja = mw C/W = C T J = T A + ΔT = + C = C A worst-case estimate, P D(max), represents the maximum allowable power level (V CC(max), I CC(max) ), without exceeding T J(max), at a selected R θja and T A. Northeast Cutoff, Box Worcester, Massachusetts - () -
Electrical Operating Characteristics, Package L I CC(off) I CC(off) Current (ma) - C C Current (ma) - I CC(on) I CC(on) Current (ma) - C C Current (ma) - Output Saturation Voltage V CC =, I sink = ma Vsat (mv) - Ch. A Ch. B Northeast Cutoff, Box Worcester, Massachusetts - () -
Magnetic Operating Characteristics, Package L Channel A, B OP and B RP Channel A, B OP and B RP Switchpoint (G) - - B OP B RP - C C Switchpoint (G) - - B OP B RP V - - - Channel B, B OP and B RP Channel B, B OP and B RP Switchpoint (G) - - B OP B RP - C C Switchpoint (G) - - B OP B RP V - - - Channels A and B, Hysteresis Channels A and B, Hysteresis B OP - B RP (G) - C C B OP - B RP (G) - V Additional magnetic characteristics on next page Northeast Cutoff, Box Worcester, Massachusetts - () -
Magnetic Operating Characteristics, Package L (continued) Ch. A - Ch. B (G) - - B OP Symmetry - C C Ch. A - Ch. B (G) - - B OP Symmetry V - - - B RP Symmetry B RP Symmetry Ch. A - Ch. B (G) - - - C C Ch. A - Ch. B (G) - - V - - - Additional magnetic characteristics on next page Northeast Cutoff, Box Worcester, Massachusetts - () -
Magnetic Operating Characteristics, Package L (continued) Channel A Symmetry Channel A Symmetry B OP + B RP (G) - - - C C B OP + B RP (G) - - V - - - Channel B Symmetry Channel B Symmetry B OP + B RP (G) - - - C C B OP + B RP (G) - - V - - - Northeast Cutoff, Box Worcester, Massachusetts - () -
Electrical Operating Characteristics, Package K I CC(off) I CC(off) Current (ma) - C C Current (ma) - I CC(on) I CC(on) Current (ma) - C C Current (ma) - Output Saturation Voltage V CC =, I sink = ma Vsat (mv) - Ch. A Ch. B Northeast Cutoff, Box Worcester, Massachusetts - () -
Magnetic Operating Characteristics, Package K Channel A, B OP and B RP Channel A, B OP and B RP Switchpoint (G) - - B OP B RP - C C Switchpoint (G) - - B OP B RP V - - - Channel B, B OP and B RP Channel B, B OP and B RP Switchpoint (G) - - B OP B RP - C C Switchpoint (G) - - B OP B RP V - - - Channels A and B, Hysteresis Channels A and B, Hysteresis B OP - B RP (G) - C C B OP - B RP (G) - V Additional magnetic characteristics on next page Northeast Cutoff, Box Worcester, Massachusetts - () -
Magnetic Operating Characteristics, Package K (continued) Ch. A - Ch. B (G) - - B OP Symmetry - C C Ch. A - Ch. B (G) - - B OP Symmetry V - - - B RP Symmetry B RP Symmetry Ch. A - Ch. B (G) - - - C C Ch. A - Ch. B (G) - - V - - - Additional magnetic characteristics on next page Northeast Cutoff, Box Worcester, Massachusetts - () -
Magnetic Operating Characteristics, Package K (continued) Channel A Symmetry Channel A Symmetry B OP + B RP (G) - - - C C B OP + B RP (G) - - V - - - Channel B Symmetry Channel B Symmetry B OP + B RP (G) - - - C C B OP + B RP (G) - - V - - - Northeast Cutoff, Box Worcester, Massachusetts - () -
Package K, -pin SIP.... D.9 NOM. D. NOM. C..9........ NOM D E B E. MIN. A.. NOM. MAX.. MAX..........9..... NOM Dimensions in inches Millimeters in brackets, for reference only Case dimensions exclusive of mold flash or gate burrs Mold flash. [.] MAX, gate burr. [.] MAX, dambar protrusion. [.] MAX Exact case and lead configuration at supplier discretion within limits shown A B C D Dambar removal protrusion (X) Ejector mark on opposite side Active Area Depth. [.] NOM Hall elements E, E (not to scale) Northeast Cutoff, Box Worcester, Massachusetts - () - 9
Package L, -pin SOIC..... [.] M B M..9..9 A D D.9. NOM..9 NOM B C º º.... D.9. NOM E E.... A.... D.. NOM.. X. [.] C SEATING PLANE C SEATING PLANE GAUGE PLANE.. X... [.] M C A B.........9.. REF.9 Preliminary dimensions, for reference only Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only (reference JEDEC MS- AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal # mark area B Reference pad layout (reference IPC SOICP-M); adjust as necessary to meet application process requirements B.9 REF.9 C D Active Area Depth. [.] Hall elements E, E (not to scale), U.S. Customary dimensions controlling. MAX.. REF. Northeast Cutoff, Box Worcester, Massachusetts - () -
The products described herein are manufactured under one or more of the following U.S. patents:,,9;,,;,,;,9,9;,,9;,,;,9,;,,9;,,9;,,9;,9,;,9,;,9,; and other patents pending. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright,, Northeast Cutoff, Box Worcester, Massachusetts - () -