Preliminary Data Sheet No. PD63 rev.p Features Floating channel designed for bootstrap operation Fully operational to +12V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from 12 to 2V Undervoltage lockout for both channels 3.3V logic compatible Separate logic supply range from 3.3V to 2V Logic and power ground ±5V offset CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Outputs in phase with inputs Also available LEAD-FREE (PbF) Description The IR2213(S) is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs, down to 3.3V logic. The output drivers feature a high IR2213(S) &(PbF) HIGH AND LOW SIDE DRIVER Product Summary V OFFSET I O +/- V OUT t on/off (typ.) Delay Matching Packages 14-Lead PDIP 12V max. 1.7A / 2A 12-2V 28 & 2 ns 3 ns 16-Lead SOIC (wide body) pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 12 volts. Typical Connection (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1
Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Units V B High Side Floating Supply Voltage -.3 12 V S High Side Floating Supply Offset Voltage V B - V B +.3 V HO High Side Floating Output Voltage V S -.3 V B +.3 V CC Low Side Fixed Supply Voltage -.3 V LO Low Side Output Voltage -.3 V CC +.3 V DD Logic Supply Voltage -.3 V SS + V SS Logic Supply Offset Voltage V CC - V CC +.3 V IN Logic Input Voltage (HIN, LIN & SD) V SS -.3 V DD +.3 dvs/dt Allowable Offset Supply Voltage Transient (Figure 2) 5 V/ns P D Package Power Dissipation @ T A + C (14 Lead PDIP) 1.6 (16 Lead SOIC) 1. W R THJA Thermal Resistance, Junction to Ambient (14 Lead PDIP) 75 C/W (16 Lead SOIC) 1 T J Junction Temperature 1 T S Storage Temperature - T L Lead Temperature (Soldering, 1 seconds) 3 V C Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at V differential. Symbol Definition Min. Units V B High Side Floating Supply Absolute Voltage V S + 12 V S + 2 V S High Side Floating Supply Offset Voltage Note 1 12 V HO High Side Floating Output Voltage V S V B V CC Low Side Fixed Supply Voltage 12 2 V LO Low Side Output Voltage VCC V DD Logic Supply Voltage V SS + 3 V SS + 2 V SS Logic Supply Offset Voltage -5 (Note 2) 5 V V IN Logic Input Voltage (HIN, LIN & SD) V SS V DD Note 1: Logic operational for V S of -5 to +12V. Logic state held for V S of -5V to -V BS. (Please refer to the Design Tip DT97-3 for more details). Note 2: When VDD<5V, the minimum VSS offset is limited to -VDD 2 www.irf.com
Dynamic Electrical Characteristics V BIAS (V CC, V BS, V DD ) = V, C L = 1 pf, T A = C and V SS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3. Symbol Definition Min. Units Test Conditions t on Turn-On Propagation Delay 28 V S = V t off Turn-Off Propagation Delay 2 V S = 12V t sd Shutdown Propagation Delay 23 V S = 12V ns t r Turn-On Rise Time t f Turn-Off Fall Time 17 MT Delay Matching, HS & LS Turn-On/Off 3 Static Electrical Characteristics V BIAS (V CC, V BS, V DD ) = V, T A = C and V SS = COM unless otherwise specified. The V IN, V TH and I IN parameters are referenced to V SS and are applicable to all three logic input leads: HIN, LIN and SD. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Definition Min. Units Test Conditions V IH Logic 1 Input Voltage 9.5 V IL Logic Input Voltage 6. V OH High Level Output Voltage, V BIAS - V O 1.2 V I O = A V OL Low Level Output Voltage, V O.1 I O = A I LK Offset Supply Leakage Current 5 V B = V S = 12V I QBS Quiescent V BS Supply Current 1 23 V IN = V or V DD I QCC Quiescent V CC Supply Current 18 34 V IN = V or V DD µa I QDD Quiescent V DD Supply Current 3 V IN = V or V DD I IN+ Logic 1 Input Bias Current 2 4 V IN = V DD I IN- Logic Input Bias Current 1. V IN = V V BSUV+ V BS Supply Undervoltage Positive Going 8.7 1.2 11.7 Threshold V BSUV- V BS Supply Undervoltage Negative Going 7.9 9.3 1.7 Threshold V CCUV+ V CC Supply Undervoltage Positive Going 8.7 1.2 11.7 V Threshold V CCUV- V CC Supply Undervoltage Negative Going 7.9 9.3 1.7 Threshold I O+ Output High Short Circuit Pulsed Current 1.7 2.` V O = V, V IN = V DD PW 1 µs A I O- Output Low Short Circuit Pulsed Current 2. 2.5 V O = V, V IN = V PW 1 µs www.irf.com 3
Functional Block Diagram Lead Definitions Symbol Description V DD Logic supply HIN Logic input for high side gate driver output (HO), in phase SD Logic input for shutdown LIN Logic input for low side gate driver output (LO), in phase V SS Logic ground V B High side floating supply HO High side gate drive output V S High side floating supply return V CC Low side supply LO Low side gate drive output COM Low side return Lead Assignments 14 Lead PDIP 16 Lead SOIC (Wide Body) IR2213 IR2213S Part Number 4 www.irf.com
HV =1 to 12V <5 V/ns Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit ( to 12V) Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition SD 5% tsd HO LO 9% Figure 5. Shutdown Waveform Definitions Figure 6. Delay Matching Waveform Definitions www.irf.com 5
1 1 8 8 Turn-On Rise Time (ns) 6 4 Turn-On Rise Time (ns) 6 4 2 2-5 - 5 75 1 1 Figure 1A. Turn-On Rise Time vs. Temperature 1 12 14 16 18 2 VBIAS Supply Voltage (V) Figure 1B. Turn-On Rise Time vs. Voltage 5 5 4 4 Turn-Off Fall Time (ns) 3 2 Turn-Off Fall Time (ns) 3 2 1 1-5 - 5 75 1 1 Figure 11A. Turn-Off Fall Time vs. Temperature 1 12 14 16 18 2 VBIAS Supply Voltage (V) Figure 11B. Turn-Off Fall Time vs. Voltage. Logic "1" Input Threshold (V) 12. 9. 6. 3. Min. Logic " 1" Input Threshold (V) 12 9 6 3. -5-5 75 1 1 Figure 12A. Logic 1 Input Threshold vs. Temperature 2 4 6 8 1 12 14 16 18 2 VDD Logic Supply Voltage (V) Figure 12B. Logic 1 Input Threshold vs. Voltage 6 www.irf.com
. 12. 12 Logic "" Input Threshold (V) 9. 6. 3. Logic "" Input Threshold (V) 9 6 3 Min.. -5-5 75 1 1 Figure 13A. Logic Input Threshold vs. Temperature 2 4 6 8 1 12 14 16 18 2 VDD Logic Supply Voltage (V) Figure 13B. Logic Input Threshold vs. Voltage 5. 5. 4. 4. High Level Output Voltage (V) 3. 2. 1. High Level Output Voltage (V) 3. 2. 1. M ax.. -5-5 75 1 1 Figure 14A. High Level Output vs. Temperature. 1 12 14 16 18 2 VBIAS Supply Voltage (V) Figure 14B. High Level Output vs. Voltage 1. 1..8.8 Low Level Output Voltage (V).6.4 Low Level Output Voltage (V).6.4.2.2 M ax.. -5-5 75 1 1 Figure A. Low Level Output vs. Temperature. 1 12 14 16 18 2 VBIAS Supply Voltage (V) Figure B. Low Level Output vs. Voltage www.irf.com 7
5 5 Offset Supply Leakage Current (µa) 4 3 2 1-5 - 5 75 1 1 Figure 16A. Offset Supply Current vs. Temperature Offset Supply Leakage Current (µa) 4 3 2 1 2 4 6 8 1 12 VB Boost Voltage (V) Figure 16B. Offset Supply Current vs. Voltage 5 5 4 4 VBS Supply Current (µa) 3 2 1 VBS Supply Current (µa) 3 2 1-5 - 5 75 1 1 Figure 17A. VBS Supply Current vs. Temperature 1 12 14 16 18 2 VBS Floating Supply Voltage (V) Figure 17B. VBS Supply Current vs. Voltage 6 6 5 5 VCC Supply Current (µa) 375 1 VCC Supply Current (µa) 375 1-5 - 5 75 1 1 Figure 18A. VCC Supply Current vs. Temperature 1 12 14 16 18 2 VCC Fixed Supply Voltage (V) Figure 18B. VCC Supply Current vs. Voltage 8 www.irf.com
VDD Supply Current (µa) 1 8 6 4 2-5 - 5 75 1 1 Figure 19A. VDD Supply Current vs. Temperature VDD Supply Current (µa) 6 5 4 3 max 2 1 typ. 2 4 6 8 1 12 14 16 18 2 VDD Logic Supply Voltage (V) Figure 19B. VDD Supply Current vs. VDD Voltage 1 6 Logic "1" Input Bias Current (µa) 8 6 4 2-5 - 5 75 1 1 Figure 2A. Logic 1 Input Current vs. Temperature Logic 1 Input Bias Current (µa) 5 4 3 2 1 max typ. 2 4 6 8 1 12 14 16 18 2 VDD Logic Supply Voltage (V) Figure 2B. Logic 1 Input Current vs. VDD Voltage Logic "" Input Bias Current (µa) 5. 4. 3. 2. 1.. -5-5 75 1 1 Figure 21A. Logic Input Current vs. Temperature Logic Input Bias Current (µa) 5 4 3 2 max 1 2 4 6 8 1 12 14 16 18 2 VDD Logic Supply Voltage (V) Figure 21B. Logic Input Current vs. VDD Voltage www.irf.com 9
. 2. VS Offset Supply Voltage (V) -3. -6. -9. -12. VSS Logic Supply Offset Voltage (V) 16. 12. 8. 4. -. 1 12 14 16 18 2 VBS Floating Supply Voltage (V). 1 12 14 16 18 2 VCC Fixed Supply Voltage (V) Figure 22. Maximum VS Negative Offset vs. VBS Supply Voltage Figure 23. Maximum VSS Positive Offset vs. VCC Supply Voltage Temperature ( o C) 3v 2v 1v v Temperature ( o C) 3v 2v 1v v.1 1 1 1.1 1 1 1 Figure 24. IR2213s vs. Frequency (IRFBC2) =33Ω, V CC =V Figure. IR2213s vs. Frequency (IRFBC3) =22Ω, V CC =V 1 www.irf.com
Temperature ( o C) 75.1 1 1 1 Figure 26. IR2213s vs. Frequency (IRFBC4) =Ω, V CC =V 3v 2v 1v v Temperature ( o C) 75 3v 2v 1v v.1 1 1 1 Figure 27. IR2213s vs. Frequency (IRFBC5) =1Ω, V CC =V Temperature ( o C) 3v 2v 1v v Temperature ( o C) 3v 2v 1v v.1 1 1 1.1 1 1 1 Figure 28. IR2213 vs. Frequency (IRFBC2) =33Ω, V CC =V Figure 29. IR2213 vs. Frequency (IRFBC3) =22Ω, V CC =V www.irf.com 11
75 75 Temperasture ( o C) 3v 2v 1v v Temperature ( o C) 3v 2v 1v v.1 1 1 1.1 1 1 1 Figure 3. IR2213 vs. Frequency (IRFBC4) =Ω, V CC =V Figure 31. IR213 vs. Frequency (IRFBC5) =1Ω, V CC =V 12 www.irf.com
Case outlines 14-Lead PDIP 1-61 1-32 3 (MS-1AC) 16-Lead SOIC (wide body) 1 6 1-314 3 (MS-13AA) www.irf.com 13
Tape & Reel 16-Lead SOIC LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLING DIMENSION IN MM E G CARRIER TAPE DIM ENSION FOR 16SOIC W Metric Im perial Code Min Max Min Max A 11.9 12.1.468.476 B 3.9 4.1.3.161 C.7 16.3.618.641 D 7.4 7.6.291.299 E 1.8 11..4.433 F 1.6 1.8.417.4 G 1.5 n/a.59 n/a H 1.5 1.6.59.62 F D E C B A G H REEL DIM ENSIONS FOR 16SOIC W Metric Im perial Code Min Max Min Max A 329.6 33. 12.976 13.1 B 2.95 21..824.844 C 12.8 13.2.53.519 D 1.95 2..767.96 E 98. 12. 3.858 4. F n/a 22.4 n/a.881 G 18.5 21.1.728.83 H 16.4 18.4.6.724 14 www.irf.com
LEADFREE PART MARKING INFORMATION Part number Date code IRxxxxxx YWW? IR logo Pin 1 Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP 2-2 ORDER INFORMATION Basic Part (Non-Lead Free) 14-Lead PDIP IR2213 order IR2213 16-Lead SOIC IR2213S order IR2213S 16-Lead SOIC Tape & Reel order IR2213STR Leadfree Part 14-Lead PDIP IR2213 order IR2213PbF 16-Lead SOIC IR2213S order IR2213SPbF 16-Lead SOIC Tape & Reel order IR2213STRPbF Thisproduct has been designed and qualified for the industrial market. Qualification Standards can be found on IR s Web Site http://www.irf.com Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 92 Tel: (31) 2-7 1/24/27 www.irf.com