Data Sheet No. PD7 Rev.A Features Floating channel designed for bootstrap operation Fully operational to +V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from to V Undervoltage lockout for both channels.v, V and V input logic compatible Cross-conduction prevention logic Matched propagation delay for both channels High side output in phase with IN input Logic and power ground +/- V offset. Internal ns dead-time Lower di/dt gate driver for better noise immunity Shut down input turns off both channels 8-Lead SOIC also available LEAD-FREE (PbF). Description The IR(S) are high voltage, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output IR(S) & (PbF) HALF-BRIDGE DRIVER Packages 8-Lead SOIC IR(S) (Also available LEAD-FREE (PbF)) ///8//9// Feature Comparison 8-Lead PDIP IR µ µ channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to.v logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to volts. Typical Connection (Refer to Lead Assignments for correct configuration). This/ These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. IR www.irf.com
IR(S) & (PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Max. Units V B High side floating absolute voltage -. V S High side floating supply offset voltage V B - V B +. V HO High side floating output voltage V S -. V B +. V V CC Low side and logic fixed supply voltage -. V LO Low side output voltage -. V CC +. V IN Logic input voltage (IN & SD) COM -. V CC +. dv S /dt Allowable offset supply voltage transient V/ns P D Rth JA Package power dissipation @ T A + C Thermal resistance, junction to ambient (8 Lead PDIP) (8 Lead PDIP). (8 Lead SOIC) (8 Lead SOIC). W C/W T J Junction temperature T S Storage temperature - T L Lead temperature (soldering, seconds) C Recommended Operating Conditions The input/output logic timing diagram is shown in figure. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at V differential. Symbol Definition Max. Units VB High side floating supply absolute voltage V S + V S + V S High side floating supply offset voltage Note V HO High side floating output voltage V S V B V CC Low side and logic fixed supply voltage V V LO Low side output voltage V CC V IN Logic input voltage (IN & SD) COM V CC T A Ambient temperature - C Note : Logic operational for V S of - to +V. Logic state held for V S of -V to -V BS. (Please refer to the Design Tip DT97- for more details). www.irf.com
IR(S) & (PbF) Dynamic Electrical Characteristics V BIAS (V CC, V BS ) = V, C L = pf, and T A = C unless otherwise specified. Symbol Definition Max. Units Test Conditions ton Turn-on propagation delay 7 9 V S = V toff Turn-off propagation delay 8 V S = V or V tsd Shut-down propagation delay 8 MT Delay matching, HS & LS turn-on/off nsec tr Turn-on rise time V S = V tf Turn-off fall time 8 V S = V DT Deadtime: LO turn-off to HO turn-on(dtlo-ho) & 8 HO turn-off to LO turn-on (DTHO-LO) MDT Deadtime matching = DTLO - HO - DTHO-LO Static Electrical Characteristics V BIAS (V CC, V BS ) = V and T A = C unless otherwise specified. The V IL, V IH and I IN parameters are referenced to COM and are applicable to the respective input leads: IN and SD. The V O, I O and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Definition Max. Units Test Conditions V IH Logic input voltage for HO & logic for LO.9 V CC = V to V V IL Logic input voltage for HO & logic for LO.8 V CC = V to V V SD,TH+ SD input positive going threshold.9 V CC = V to V V SD,TH- SD input negative going threshold.8 V V CC = V to V V OH High level output voltage, V BIAS - V O.8. I O = ma V OL Low level output voltage, V O.. I O = ma I LK Offset supply leakage current V B = V S = V µa I QBS Quiescent V BS supply current V IN = V or V I QCC Quiescent V CC supply current... ma V IN = V or V I IN+ Logic input bias current IN = V, SD = V µa I IN- Logic input bias current IN = V, SD = V V CCUV+ V CC and V BS supply undervoltage.. V BSUV+ positive going threshold V CCUV- V CC and V BS supply undervoltage.8.7 V BSUV- negative going threshold V V CCUVH Hysteresis.. V BSUVH I O+ Output high short circuit pulsed vurrent V O = V, PW µs ma I O- Output low short circuit pulsed current V O = V,PW µs www.irf.com
IR(S) & (PbF) Functional Block Diagrams VB UV DETECT R HO IN VSS/COM LEVEL SHIFT PULSE GENERATOR HV LEVEL SHIFTER PULSE FILTER R S Q VS DEADTIME VCC +V UV DETECT LO SD VSS/COM LEVEL SHIFT DELAY COM www.irf.com
IR(S) & (PbF) Lead Definitions Symbol Description IN SD V B HO V S V CC LO COM Logic input for high and low side gate driver outputs (HO and LO), in phase with HO Logic input for shutdown High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return Lead Assignments V CC V B 8 V CC V B 8 IN HO 7 IN HO 7 SD V S SD V S COM LO COM LO 8 Lead PDIP 8 Lead SOIC (Also available LEAD-FREE (PbF) IR IRS www.irf.com
IR(S) & (PbF) Figure. Input/Output Timing Diagram Figure. Switching Time Waveform Definitions Figure. Shutdown Waveform Definitions Figure. Deadtime Waveform Definitions www.irf.com
IR(S) & (PbF) Figure. Delay Matching Waveform Definitions Turn-on Propagation Delay (ns) 9 7 - - 7 Turn-on Propagation Delay (ns) 9 7 Figure A. Turn-on Propagation Delay Figure B. Turn-on Propagation Delay www.irf.com 7
IR(S) & (PbF) Turn-on Propagation Delay (ns) 9 7 9 Turn-off Propagation Delay (ns) - - 7 Input Voltage (V) Figure C. Turn-on Propagation Delay vs. Input Voltage Figure 7A. Turn-off Propagation Delay Turn-off Propagation Delay (ns) 7 Turn-off Propagation Delay (ns) 9 Input Voltage (V) Figure 7B. Turn-off Propagation Delay Figure 7C. Turn-off Propagation Delay vs. Input Voltage 8 www.irf.com
IR(S) & (PbF) Shut-down Propagation Delay (ns) - - 7 Shut-down Propagation Delay (ns) 7 Figure 8A. Shut-down Propagation Delay Figure 8B. Shut-down Propagation Delay Shut-down Propagation Delay (ns) 9 Turn-on Rise Time (ns) - - 7 Input Voltage (V) Figure 8C. Shut-down Propagation Delay vs. Input Voltage Figure 9A. Turn-on Rise Time www.irf.com 9
IR(S) & (PbF) 7 Turn-on Rise Time (ns) Turn-off Fall Time (ns) - - 7 Figure 9B. Turn-on Rise Time Figure A. Turn-off Fall Time Turn-off Fall Time (ns) Deadtime (ns) 8 - - 7 Figure B. Turn-off Fall Time Figure A. Deadtime www.irf.com
IR(S) & (PbF) 7 Deadtime (ns) 8 Deadtime ( s) RDT (KΩ) Figure B. Deadtime Figure C. Deadtime vs. RDT Logic "" Input Voltage (V) Logic "" Input Voltage (V) - - 7 Figure A. Logic "" Input Voltage Figure B. Logic "" Input Voltage www.irf.com
IR(S) & (PbF) Logic "" Input Voltage (V) Logic "" Input Voltage (V) - - 7 Figure A. Logic "" Input Voltage Figure B. Logic "" Input Voltage SD Input Positive Going Threshold (V - - 7 SD Input Positive Going Threshold (V Figure A. SD Input Positive Going Threshold vs. Tem perature Figure B. SD Input Positive Going Threshold www.irf.com
IR(S) & (PbF) SD Input Negative Going Threshold (V) - - 7 SD Input Negative Going Threshold (V Figure A. SD Input Negative Going Threshold Figure B. SD Input Negative Going Threshold High Level Output Voltage (V) - - 7 High Level Output Voltage (V) Figure A. High Level Output Voltage Figure B. High Level Output Voltage www.irf.com
IR(S) & (PbF).. Low Level Output Voltage (V).... - - 7 Low Level Output Voltage (V).... Figure 7A. Low Level Output Voltage Figure 7B. Low Level Output Voltage Offset Supply Leakage Current ( A) - - 7 Offset Supply Leakage Current (ma) Offset Figure 8A. Offset Supply Leakage Current Figure 8B. Offset Supply Leakage Current vs. Offset Supply Voltage www.irf.com
IR(S) & (PbF) Quiescent V BS Supply Current ( A) - - 7 Quiescent V BS Supply Current ( A) V BS Figure 9A. Quiescent V BS Supply Current Figure 9B. Quiescent V BS Supply Current vs. V BS Supply Voltage Quiescent V CC Supply Current (ma)... Max.... - - 7 Quiescent V CC Supply Current (ma)... V CC Figure A. Quiescent V CC Supply Current Figure B. Quiescent V CC Supply Current vs. V CC Supply Voltage www.irf.com
IR(S) & (PbF) Logic "" Input Bias Current ( A) - - 7 Logic "" Input Bias Current (ma) Figure A. Logic "" Input Bias Current Figure B. Logic "" Input Bias Current Logic "" Input Bias Current ( A) - - 7 Logic "" Input Bias Current (ma) Figure A. Logic "" Input Bias Current Figure B. Logic "" Input Bias Current www.irf.com
IR(S) & (PbF) V CC and V BS Undervoltage Threshold (+) (V) - - 7 V CC and V BS Undervoltage Threshold (-) (V) - - 7 Figure. V CC and V BS Undervoltage Threshold (+) Figure. V CC and V BS Undervoltage Threshold (-) Output Source Current (ma) Output Source Current (ma) - - 7 Figure A. Output Source Current Figure B. Output Source Current www.irf.com 7
IR(S) & (PbF) Output Sink Current (ma) - - 7 Output Sink Current (ma) Figure A. Output Sink Current Figure B. Output Sink Current Maximum V S Negative Offset (V) - - - -8 - - V BS Floating Figure 7. Maximum V S Negative Offset vs. V BS Floating Supply Voltage Temprature ( o C) 8 Frequency (KHz) Figure 8. IR vs. Frequency (IRFBC), R gate =Ω, V CC =V V 7V V 8 www.irf.com
IR(S) & (PbF) 8 V 7V V 8 V 7V V Frequency (KHz) Figure 9. IR vs. Frequency (IRFBC), R gate =Ω, V CC =V Frequency (KHz) Figure. IR vs. Frequency (IRFBC), R gate =Ω, V CC =V V 7V V 8 8 V 7V V Frequency (KHz) Figure. IR vs. Frequency (IRFPE), R gate =Ω, V CC =V Frequency (KHz) Figure. IRS vs. Frequency (IRFBC), R gate =Ω, V CC =V www.irf.com 9
IR(S) & (PbF) V 7V 8 V Frequency (KHz) Figure. IRS vs. Frequency (IRFBC), R gate =Ω, V CC =V 7V V 8 Frequency (KHz) Figure. IRS vs. Frequency (IRFBC), R gate =Ω, V CC =V V V 7V V Tempreture ( o C) 8 Frequency (KHz) Figure. IRS vs. Frequency (IRFPE), R gate =Ω, V CC =V www.irf.com
IR(S) & (PbF) Case Outlines 8 Lead PDIP - - (MS-AB) A E X D 8 7 e B H. [.] A. [.] X.7 [.] FOOTPRINT 8X.7 [.8] 8X.78 [.7] DIM INC HES MILLIMETERS MIN MAX MIN MAX A A...88.98...7. b.... c.7.98.9. D E.89.97.98.7.8.8.. e. BASIC.7 BASIC e. BASIC. BASIC H K L y.8.99...9. 8.8.....7 8 e A C y K x 8X b A. [.] C A B. [.] 8X L 7 8X c NOTES:. DIMENSIONING & TOLERANCING PER ASME Y.M-99.. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].. OUTLINE CONFORMS TO JEDEC OUTLINE MS-AA. 8 Lead SOIC DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. -7 - (MS-AA) www.irf.com
IR(S) & (PbF) LEADFREE PART MARKING INFORMATION Part number Date code IRxxxxxx YWW? IR logo Pin Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - digit SPN code) Assembly site code Per SCOP - ORDER INFORMATION Basic Part (Non-Lead Free) 8-Lead PDIP IR order IR 8-Lead SOIC IRS order IRS Leadfree Part 8-Lead PDIP R not available 8-Lead SOIC IRS order IRSPbF Thisproduct has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web Site http://www.irf.com Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: Kansas St., El Segundo, California 9 Tel: () -7 8// www.irf.com