1 Threshold Logic Computing: Memristive-CMOS Circuits for Fst Fourier Trnsform nd edic Multipliction Alex Pppchen Jmes, Dinesh S. Kumr, nd Arun Ajyn Abstrct Brin inspired circuits cn provide n lterntive solution to implement computing rchitectures tking dvntge of fult tolernce nd generlistion bility of logic gtes. In this brief, we dvnce over the memristive threshold circuit configurtion consisting of memristive verging circuit in combintion with opertionl mplifier nd/or CMOS inverters in ppliction to relizing complex computing circuits. The developed memristive threshold logic gtes re used for designing FFT nd multipliction circuits useful for modern microprocessors. Overll, the proposed threshold logic outperforms previous memristive-cmos logic cells on every spect, however, indicte lower chip re, lower THD, nd controllble lekge power, but higher power dissiption with respect to CMOS logic. Index Terms Threshold logic, memristors, digitl circuits, digitl integrted circuits, progrmmble circuits I. I T RO D U C T I O There hs been severl ttempts to functionlly nd electriclly mimic the neuron ctivity nd its networks [1]. However, mjor chllenge tht deters the progress in LSI implementtions of brin like logic gtes is the sclbility of the networks nd its prcticl limittions in solving lrge vrible boolen logic problems. The possibility to mimic the brin like circuits nd logic networks is topic of intense debte. One possibility is to pply the threshold logic gtes in designing conventionl computtionl blocks, while other option is to develop completely trinble rchitecture tht does not strictly bind itself to conventionl computing topologies. In this brief, we restrict the notion of the brin mimicking to develop generlised memristive threshold logic cell in ppliction to designing conventionl computing blocks. onetheless, this topic is one of the forefront chllenges in development of on-chip brin computing, nd would require us to investigte not just new circuit design logic, but lso new devices nd systems. Threshold logic is the primry logic of humn brin tht inspires from the neuronl firing nd trining mechnisms. The progress in threshold logic circuits [2] re often limited to implementtion of logic gtes with few number of input vribles, this leds to limited progress being mde in the development of prcticl computing circuit topologies. Memristor like switching devices [3] unlike mny other electronic devices hs n interesting ppel in on-chip brin computing, s it offers switching stte through its bi-level resistnce vlues. Further these resistors re mpped to the binry memory spce nd offer the dvntge of low on-chip re nd low lekge currents. We explore this spect of memristor, nd extend over our previous work [4] in designing FFT computing useful for signl processing pplictions, nd vedic dditions nd multiplictions for efficient ALU design. The resulting circuits cn be used in combintion with conventionl CMOS circuits to develop threshold logic processor designs. II. CO M P U T I G CI R C U I T S W I T H TH R E S H O L D LO G I C The memristive threshold logic (MTL) cell shown in Fig. 1 is the bsic cell which consists of two prts; memristor bsed input A.P. Jmes is fculty with Electricl nd Electronic Engineering deprtment, zrbyev University. D.S. Kumr nd A. Ajyn re member reserch stff with Enview R&D lbs. Contct Emil: pj@ieee.org Mnuscript received Oct. 7, 2013; revised Feb. 16, 2014; July 14, 2014; 12 Oct., 2014. Logic Fmily Fig. 1: Memristive threshold logic cell voltge verging circuit nd n output threshold circuit. In contrst to our previous work on resistive threshold logic [4], the proposed cell hs the input potentil divider circuit modified by removing the pull-down resistor to form n input voltge verging circuit nd the threshold circuit modified with the combined use of opertionl mplifier nd CMOS inverter. In prticulr, by removing the pulldown resistor from [4], n importnt improvement over lower power dissiption is chieved in cell s shown in the Tble I. In the presented work, the threshold unit consisting of combintion of n op-mp [5] nd CMOS inverter tht llows for fult tolernce in terms of logicl output signl stbility. The generliztion of the cell to work s different logic gtes is chieved with the bility of the cell to utilize wider rnge of threshold vlue. TABLE I: CO M PA R I G PR E I O U S CI R C U I T [4] W I T H P R E S E T PRO P O S E D CI R C U I T B Y IM P L E M E T I G A 2-I P U T OR LO G I C GAT E. RTL without op-mp [4] 8.30 MTL without op-mp 3.00 RTL with op-mp [4] 19.70 MTL with op-mp 16.61 Power dissiption (μw) For n input cell, the resistnce circuit prt consist of memristors hving equl memristnce vlues, M 1 = M 2 =...M = M. The output A = ( P voltge A for input voltges I cn be represented s I =1 I )/. Tble II shows truth tble for two input AD nd OR gtes. 1 nd 2 re the input voltge tht cn tke vlues of L (voltge low) or H (voltge high). For prcticl purposes, the boundry conditions re voided, nd in generl for ny inputs, if REF is in between (( 1) H + L )/ nd H we obtin AD logic nd if it is in between L nd ( L + ( 1) H )/ we obtin OR logic. The combined effect of REF t opertionl mplifier nd T H of the inverter provides stble threshold logic unit, where T H is the threshold voltge of the inverter. The opertionl mplifier ensures wider rnge of threshold vlue limiting the role of inverter s mens to ensure stble binry sttes. The impct of hving opertionl mplifier in the output of the cell is shown in Fig. 2, while Fig. 2b cptures the vritions of the output voltge for different vlues of REF. The dvntges of using opmp in order to fix the threshold of the circuit cn be clerly observed. from the Fig. 2. Only for the gtes tht hving inputs higher thn 2 input require the use n op-mp in the circuit. In ddition to this It hs been observed during simultion tht, without using n op-mp in the circuit nd +/-15% vribility in chnnel lengths does not hve ny effect on the output of AD logic, while minor vritions in OR logic. On the contrry, we observed no vrition in outputs even with +/-15% vribility in chnnel lengths when op-mps re incorported. The reson for this is becuse the mplifiction in the voltge rnge mde by the op-mp increses the voltge rnge to +/- 1. This offers broder selection rnge of CMOS inverters thresholds ensuring tht the threshold vlues lie inside this rnge even if the
2 Fig. 2: Reltion between output of the memristive divider nd output of the inverter of the proposed cell. shows the effect of op-mp on the output of the cell, nd shows the vrition in output of the cell for different vlues of REF. Fig. 5: Operting rnge of two input OR cell AD memristive threshold logic cell with REF = 0.5. AD OR Fig. 3: The grphs illustrte the effect of chnge in the technology length on the output of MTL logic fmily without op-mp. technology length re chnged. Additionlly chnge in the speed of the trnsistors will reflect in the dely introduced by inverter, i.e., slow-slow (0.89ns), fst-fst (0.23ns), slow-fst (0.50ns), fst-slow (0.52ns) tested with n input pulse with speed of 10ns. The dely is high for the slow-slow condition nd less in-cse of fst-fst. Fig. 3 shows the effect of chnge in technology length on the output of MTL logic gtes. While checking the effect of other process vritions, temperture nd chin of logic gtes, it is observed tht the power dissiption hs liner chnge in ccordnce with the temperture chnge nd hs no effect by the chin of logic gtes. In cse of dely, chnge in temperture doesn t hve ny significnt effect but the chin of logic gtes will increse the dely linerly with n increse of d 1 in ech level, where d 1 is the dely of single cell. For this study, inverter configurtion of the proposed cell is used nd chin of 6 inverters re checked in order to get the effect of chin of logic gtes. The results re shown in the Fig. 4. Throughout this pper, we use the non-idel resistive switching model of memristor reported in [4] for our study with n re of 10nm 10nm nd resistnces in the rnge of [10 6 Ω, 10 12 Ω], while CMOS circuits uses 0.25 μm (both in the MTL nd CMOS logics) Fig. 4: The grphs show the effects of chnges in temperture, nd dely introduced by chin of logic gtes on power dissiption nd dely. TSMC (Tiwn Semiconductor Mnufcturing Compny) technology to reflect the prcticl pplicbility in stndrd silicon technologies. The SPICE (Simultion Progrm with Integrted Circuit Emphsis) models tke into ccount the extrcted prsitics from CMOS lyout, so s to ensure the ccurcy for prcticl relistion. Memristor model hs non-idel behviour nd tke into ccount the boundry effects. In prctise, the memristor nd CMOS lyers cn be seprted into different lyers [6], [7]. Memristors cn be fbricted directly bove the CMOS circuits by mking them s prt of the interconnect. A 2D rry of vis provides electricl connectivity between the CMOS nd the memristor lyers. Since the vribility between the memristors re prcticlly limited nd there is lrge threshold rnge for REF for chieving desired logicl functionlity, the errors resulting from memristnce tolernce cn be ignored. TABLE II: TRU T H TA B L E F O R T H E ME M R I S T I E TH R E S H O L D LO G I C CE L L 1 2 A OR 1 AD 2 L L + L L 2 H H L L + H H 2 L H H H + L L 2 L H H H + H H 2 L 1 input OR threshold: L < REF < L ( 1)L +H 2 input AD threshold: ( 1) H + L < REF < H Fig. 5 shows the operting rnge for OR nd AD logic for two input cell where H = 1 nd L = 0. It is observed tht the gte provides robust functionl performnce even when there is n input signl vribility of 20%. Figure 6 shows the input nd output signl wveform of two input OR cell. Figure 6b shows the circuit digrms of OR, AD nd XOR functions implemented using the proposed OR logic cell, where the REF = L + δ with δ representing the incrementl threshold vlue required for the functionl implementtion of threshold logic cell. As the number of input increses the voltge rnge in which threshold cn be fixed will get nrrow. Hence for ech number of inputs the threshold vlue REF hve to be fixed seprtely. In order to void this problem REF vlue close to L nd H for OR nd AD configurtion should be selected. L + δ is voltge vlue tht is close to L nd less thn (( 1) L + H )/. This will give the freedom of using the cell without chnging REF for incresed number of inputs. Totl hrmonic distortion (THD) of the OR nd AD cells re clculted using test inputs whose signl frequency chnges from 20Hz to 20MHz. The comprison of the THD results with other logic fmilies is shown in Fig. 7. It is observed tht the memristive threshold logic hs better immunity to THDs when compred to other logic fmilies. This implies n improved ccurcy nd simplicity of circuit design for timing sensitive digitl circuit pplictions.
3 Fig. 6: Input nd output signl wveforms of the two input proposed cell with op-mp in OR logic Circuit digrms of the logic gtes using proposed cell - (i) OR gte (ii) AD gte (iii) XOR gte. Fig. 7: Totl hrmonic distortion oise spectrl density, of A - MTL AD, B - MTL OR, C - CMOS AD, D - CMOS OR, E - PSEUDO AD, F - PSEUDO OR, G - DYAMIC CMOS AD, nd H - DYAMIC CMOS OR Fig. 7b shows tht the noise spectrl density of the MTL logic is better thn the other two technologies. From THD nd noise comprison we cn conclude tht the proposed MTL logic fmily hs more immunity to noise nd hrmonic distortion. Tble III shows the exmple comprison of the memristive threshold logic for OR logic gte with CMOS logic fmily for re, power dissiption, energy nd lekge power. It cn be seen tht even for low number of inputs the re nd lekge power is lower thn CMOS, while the power dissiption nd energy is higher due to the use of CMOS nd opertionl mplifier circuits for threshold design. It my be noted RTL nd MTL enble the possibility of lrge number of inputs s demonstrted in [4] nd cn reduce the re requirements nd lekge power significntly for implementing digitl logic circuits. compre the technologies bsed on the lyout in quntified mnner. For exmple, the on-chip re for 2 input proposed OR cell in ElectricLSI resulted in n re of 95 μm 2 for MTL gte, while for CMOS gte this ws 125 μm 2, when using 0.25μm technology. Becuse the physicl design of the cells would require dditionl optimistion for the re, through out this pper, we use only spect rtios of the devices to mke the comprison between the circuits from different logic fmilies. Other memristive-cmos threshold logic gtes: There do not exist FFT or multiplier bsed circuit implementtions with memristive threshold logic circuits tht cn be firly compred with the exmple circuits reported in this pper. However, there do exists memristor- CMOS bsed threshold logic cells tht re close counterprts to the proposed cell, tht could be used to implement similr computing circuits. For exmple, RTLG [8] nd EEMTL [9] uses reconfigurble rchitectures tht cn be used to develop circuits for digitl logic problems by chnging the memristnce of the memristor, nd requires dditionl progrmming circuits leding to lrger re requirements nd higher power dissiption thn the proposed cell. RTLG uses two op-mps in single cell, one for progrmmble prt nd nother for thresholding prt. In ddition, the progrmming require pulse genertion units bsed on FPGA nd DSP processor, nd relted interfcing circuits. On the other hnd, for EEMTL, in-order to implement input cell requires memristors nd (2 +8) trnsistors, while in the proposed cell this is memristors nd 12 trnsistors (mximum). In the proposed cell, the number of trnsistors will not increse s per the number of inputs, nd is one of the dvntge over other threshold logic cells such s EEMTL. The comprison between proposed method, RTLG nd EEMTL bsed on the number of trnsistors required to implement different logic gtes is given in the Tble I. However, since these cell technologies re not mture yet for lrge scle implementtions, fir comprison for lrger circuits build with threshold logic is done only with estblished technologies such s CMOS. TABLE I: CO M PA R I S O O F TR A S I S TO R CO U T BE T W E E RTLG, EEMTL A D MTL LO G I C S Boolen Function RTLG,b EEMTL MTL OR / AD ( input) 24 2 +8 10 OR / AD ( input) 24 2 +8 12 For the firness in comprison op-mp used in ll logics hve sme number of trnsistors. b umber of trnsistors projected is for implementing bi-level hrd threshold function. This number cn significntly increse bsed on the complexity of the threshold function used. The use of the proposed memristive logic circuits in designing conventionl logic circuit is demonstrted using two exmples. The first exmple reports the design of FFT circuit using memristive TABLE III: CO M PA R I S O O F AR E A, POW E R DI S S I PAT I O, LE A K - threshold logic, while the second exmple reports the design of AG E POW E R A D E E R G Y O F T H E 2-I P U T CE L L W I T H OT H E R multiplier circuit. Both these circuit configurtions re useful in LO G I C FA M I L I E S I OR CO FI G U R AT I O. processors for computing purposes. Logic Fm- Are Power Lekge Energy Memristive Threshold FFT circuit: FFT/IFFT is widely used ily (μm 2 ) dissiption(w) Power (W) (J) in digitl signl processing for vrious filter implementtions. The j2πnk CMOS 9.4 28.6p 16.32p 28.6z bsic eqution of 4-point DFT is X (k) = P 3 x(n)e 4, k = i=0 MTL (with- 4.55 3.00μ 14.30p 0.30p 0, 1, 2, 3. Using this eqution, we cn represent the signl flow grph out op-mp) [10] of 4-point DFT s shown in Fig. 8. Implementtion of the FFT MTL (with 31.30 19.70μ 80.96p 1.09p op-mp) processor [11] cn be done s shown in Fig. 8b where ll the inputs to the circuit re 8 bits long. Hving closer look t the exponentil term j2πnk CMOS logics the vlues re obtined t mx speed of 1GHz. of 4-point DFT i.e. e 4 = ±1 or ±j, the multiplictions with The vlues for MTL with op-mp re obtined t mximum speed of 10MHz nd for MTL (without op-mp) & The re given in Tble III nd mentioned in other tbles re bsed on the device length nd width without considertion to wires nd interconnects. Since, the physcil lyout re cn vry significntly bsed on the optiml lyout configurtions, it will be difficult to ±1 nd ±j re trivil, nd no multipliers re needed to implement them. Ech FFT unit hve 4 inputs nd one corresponding FFT output. Inputs re given to the FFT units s shown in Fig. 8. The inputs which re to be subtrcted re complemented nd dded. From Fig. 8, it cn be seen tht the rel prt nd the imginry prt of the
4 TABLE : CO M PA R I S O O F AR E A, POW E R DI S S I PAT I O A D LE A K AG E POW E R O F T H E PRO P O S E D FFT CI R C U I T W I T H CMOS LO G I C Logic Fmily Are(μm 2 ) Power dissiption(w) Lekge Power(W) CMOS 75942.8 11.941n 6.218n MTL 42632.4 16.156m 13.46n Higher input gtes implemented using circuits with Op-mp (c) Fig. 8: Signl flow grph of 4-point DFT processor Block digrm of 4 point DFT processor (c) Block digrm of FFT units used in the DFT processor TABLE I: PE R F O R M A C E CO M PA R I S O O F 8-P O I T FFT IM P L E M E T E D U S I G MTL A D CMOS TE C H O L O G I E S Logic Fmily Are(mm 2 ) Power dissiption(w) CMOS 0.4155 0.356μ MTL 0.224 79.12m Higher input gtes implemented using circuits with Op-mp Fig. 9: 8 th bit of the 4 inputs to FFT unit nd shows the output sum, crry nd C out of the 8 th bit. first output in 4-point FFT requires only ddition opertion. Hence the inputs to the first 2 FFT units in Fig. 8b re not complimented. These FFT units re implemented using 3 Crry-Lookhed Adders (CLA) s shown in Fig. 8c. Other thn the first 2 FFT units, rest of the six FFT units hve 2 dditions nd 2 subtrctions. Inputs to be dded re given to the first CLA wheres the inputs tht re to be subtrcted re complimented nd then dded using the second CLA. In order to obtin the 2 s compliment, 1 is to be dded to the LSBs of inverted inputs. For this we utilize the C 0 pin of the crry look hed dders nd logic high is pplied to the C 0 pin of both the 8-bit CLA. This opertion equtes to dding one twice. ow, the outputs of these CLAs re dded using the third CLA whose output result in the required trnsform. The Crry- Lookhed dders re implemented using the proposed memristive threshold logic circuits. Signl wveform of the 8 th bit from the 4 inputs to the FFT circuit re shown in Fig. 9, while Fig. 9b shows the lest significnt bit of the resulting output signls. Tble shows the quntittive performnce comprison of the memristive logic nd CMOS logic FFT implementtions. It is observed tht the proposed logic shows reduced re requirement, however, hs higher power dissiption. The proposed logic hs zero lekge power in its memristor components nd the lekge power is entirely contributed by the op-mps. Clerly, the lekge power cn be reduced by the designing low power nd low lekge op-mp circuit. In-order to show the effect on the higher point FFTs, we hve implemented 8-point FFT using vedic multipliers nd CLAs with MTL nd did the performnce comprison with CMOS technology. The results re shown in the Tble I. From the tble it cn be seen tht the dvntge of the MTL is its lower on-chip re. The size of the circuit would sufficiently relte to the sclbility nd performnce issue of FFT circuit implementtion. Memristive Threshold edic Multiplier: edic multiplier is multiplier rchitecture tht uses vedic mthemtic [12] method for its multipliction lgorithm. Among the sixteen methods presented in the edic Mthemtics, due to the prllelism in the mode of opertion, we re using Urdhv Thirykbhym (verticl nd crosswise method) [13] method for our multiplier rchitecture. In this technique, ll the prtil products cn be found in prllel nd the entire multipliction cn be completed by using dditionl two or three levels of dders. Bsed on this lgorithm, the rchitecturl block digrm nd the working principle for 2bit multiplier is shown in Fig. 10. Figure 11 shows the equivlent circuit of 2 bit vedic multiplier lgorithm implemented using memristive threshold logic nd Fig. 11b shows the wveform of the corresponding circuit, where A 0 A 1 nd B 0 B 1 re the 2 bit inputs nd S 0 S 1 S 2 nd S 3 re the four bits of the result. In this lgorithm, the 2 bit multiplier is the bsic multiplier unit tht cn be used for mking the higher bit multipliers. In order to implement n bit memristive threshold vedic multiplier s shown in Fig. 10b, we need four /2 bit multipliers, two bit CLAs, one /2 bit CLA nd hlf dder, where must be in the power of 2. As shown in Fig. 10b, by using four 2 bit multipliers, we cn implement 4 bit multiplier. Similrly, by using four 4 bit multiplier, we cn implement 8 bit multiplier nd will continue the sme procedure for ny higher bits. Suppose, the tsk is to implement 8 bit multipliction then it would need four 4 bit multiplier, two 8 bit CLAs, one 4 bit CLA nd one hlf dder. First, the 8 bits of both multiplicnd nd multiplier is Fig. 10: Architecture block digrm for 2 bit vedic multiplier is shown in (i), while (ii) explins the working principle for ech stge of the rchitecture Block digrm for n bit multiplier
5 TABLE II: CO M PA R I S O O F O E R A L L AR E A, POW E R DI S S I PA - T I O A D LE A K AG E POW E R O F PRO P O S E D MU LT I P L I E R CI R C U I T W I T H CMOS LO G I C Multiplier Logic Fmily Are(μm 2 ) Power dissip- Lekge tion(w) Power(W) 2 bit multiplier CMOS 169.67 0.247n 0.115n MTL 50.05 1.09μ 0.173n b 8 bit multiplier CMOS 21093.54 26.97n 15.13n MTL 9628.55 3.01m 32.19n c 2 bit multipliers implemented without using op-mp, ll higher input gtes implemented with op-mp. b Memristor effectively hve no lekge power, the given vlue is tht contributed by the CMOS inverter c This vlue is entirely contributed from the threshold unit (op-mp nd CMOS inverter) Fig. 11: 2 bit memristive threshold vedic multiplier circuit input nd output wveform of the circuit, where A0 A1 nd B0 B1 re the 2 bit inputs nd S0 S1 S2 nd S3 re the four bits of the output divided into two 4 bit numbers. Let A nd B be two eight bit numbers, where we divide A s (A H, A L ) nd B s (B H, B L ). Similr to the steps tht we followed in implementing 2 bit multiplier s explined in Fig. 10, we multiply this four 4 bit numbers (A H, A L, B H nd B L ). The prtil products re A L x B L, A H x B L, A L xb H nd A H x B H. Since these re independent opertions they re processed in prllel. While doing the multipliction, ech of this 4 bit numbers (A H, A L, B H nd B L ) will gin divide into two 2 bit numbers, tht is A L s A LH nd A LL, nd proceed the 4 bit multipliction s explined in cse of 8 bit (A L x B L A LL x B LL, A LL x B LH, A LH x B LL, A LH x B LH ). The bsic multipliction unit is 2 bit multiplier s shown in Fig. 11. Tble II shows the comprison of 2 bit nd 8 bit vedic multiplier using memristive threshold logic nd CMOS logic for re, power dissiption nd lekge power. From the tble it is cler tht the proposed MTL rchitecture hs cler dvntge over the existing CMOS technology. As n initil step to chieve smll re on-chip brin computing, this reliztion is promising result for the future developments in the field of cognitive computing circuits. For the 2 bit multiplier, ll the cells re of two inputs nd we implement the circuit with cells without op-mp s shown in Fig. 10. The op-mp is not required in this cse s lrge vrition in threshold is not required to implement the threshold logic. For multiplier with higher number of bits, cells with op-mp re used to ensure tolernce to lrger rnge of threshold vlues. This will increse the power dissiption s indicted in Tble II. Like the FFT circuit, we expect to overcome this drwbck by designing low power op-mps in the circuit. III. CO C L U S I O In this brief, we reported n improved memristnce-cmos threshold logic cell hving lower power dissiption nd smller on-chip re footprint. In comprison with CMOS logic the proposed MTL cell implementtion hve lower re requirements nd higher power dissiption, nd in comprison with other memristive-cmos threshold logic gtes the proposed cell indicte lower re requirements nd lower power dissiption. Further, this brief, reports the successful ppliction of the MTL cells in the exmples of FFT nd vedic multipliction computing circuits. The MTL cell show robustness to process vribility in temperture, memristnces nd technology lengths indicting the fult tolernce bility of brin like logic circuits. The generlistion bility of the cell, i.e. single cell structure with multiple functionlity is gin chrcteristic of the proposed logic. The power dissiption nd lekge power of the proposed logic is contributed by the op-mp prt of the circuit, nd cn be improved in future by the developing low power high-speed op-mps. However, the design nd optimistion of the op-mp tht cn hndle wide rnge of threshold with high speed nd low power dissiption is left s n open problem for future work. RE F E R E C E S [1] S. H. Jo, T. Chng, I. Ebong, B. B. Bhdviy, P. Mzumder, nd W. Lu, noscle memristor device s synpse in neuromorphic systems, no Letters, no. 10, pp. 1297 1301, 2010. [2]. Beiu, J. Quintn, nd M. Avedillo, lsi implementtions of threshold logic- comprehensive survey, eurl etworks, IEEE Trnsctions on, vol. 14, no. 5, pp. 1217 1243, 2003. [3] R. Willims, How we found the missing memristor, Spectrum, IEEE, vol. 45, no. 12, pp. 28 35, 2008. [4] A. P. Jmes, L. R.. J. Frncis, nd D. S. Kumr, Resistive threshold logic, ery Lrge Scle Integrtion (LSI) Systems, IEEE Trnsctions on, vol. 22, no. 1, pp. 190 195, 2014. [5] P. E. Allen nd D. R. Holberg, CMOS Anlog Circuit Design. ew York:Oxford Univ. Press, 2011. [6] K. Eshrghin, K. R. Cho, S. K. Kvehei, O.nd Kng, D. Abbott, nd S. M. S. Kng, Memristor mos content ddressble memory (mcm): Hybrid rchitecture for future high performnce serch engines, ery Lrge Scle Integrtion (LSI) Systems, IEEE Trnsctions on, vol. 19, no. 8, pp. 1407 1417, 2011. [7] Q. Xi, W. Robinett, M. W. Cumbie,. Bnerjee, T. J. Crdinli, J. J. Yng, nd R. S. Willims, Memristor cmos hybrid integrted circuits for reconfigurble logic, no letters, vol. 9, no. 10, pp. 3640 3645, 2009. [8] T. Trn, A. Rothenbuhler, E. Brney Smith,. Sxen, nd K. Cmpbell, Reconfigurble threshold logic gtes using memristive devices, Journl of Low Power Electronics nd Applictions, vol. 3, no. 2, pp. 174 193, 2013. [9] J. Rjendrn, H. Mnem, R. Krri, nd G. S. Rose, An energy-efficient memristive threshold logic circuit, Computers, IEEE Trnsctions on, vol. 61, no. 4, pp. 474 487, 2012. [10] K. K. Prhi, LSI digitl signl processing systems: design nd implementtion. John Wiley & Sons, 2007. [11] W. Li nd L. Wnhmmr, Efficient rdix-4 nd rdix-8 butterfly elements, in Proc. of orchip Conf, 1999, pp. 262 267. [12] B. K. Tirthji, edic Mthemtics. Motill Bnrsidss, 1965. [13] R. Pushpngdn,. Sukumrn, R. Innocent, D. Ssikumr, nd. Sundr, High speed vedic multiplier for digitl signl processors, IETE Journl of Reserch, vol. 55, no. 6, pp. 282 286, 2009.