Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC
Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational Sequential Output = f(in) Output = f(in, Previous In) Digital IC
agenda Static CMOS design Ratioed logic design Pseudo NMOS Pass transistor design Dynamic logic Digital IC 3
agenda Static CMOS design Ratioed logic design Pseudo NMOS Pass transistor design Dynamic logic What is the difference between inverter and logic? Digital IC 4
Static CMOS logic CMOS static characteristic CMOS propagate delay Large fan-in technology Logic effort CMOS power analysis Digital IC 5
Static CMOS Circuit Gate output is connected to either V DD or V SS via a low-resistive path * Contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes * except during the switching transients Digital IC 6
Construction of PDN NMOS devices in series implement a NND function NMOS devices in parallel implement a NOR function + Digital IC
CMOS NND F 0 0 1 0 1 1 1 0 1 1 1 0 Digital IC
CMOS NOR + F 0 0 1 0 1 0 1 0 0 1 1 0 Digital IC
Complex CMOS Gate C D D C OUT =!(D + ( + C)) Digital IC
Standard Cell Layout Methodology Routing channel V DD signals GND What logic function is this? Digital IC
OI1 Logic Graph j C X C PUN X =!(C ( + )) X i V DD C i j C GND PDN Digital IC
Two Stick Layouts of!(c ( + )) C C V DD V DD X X GND GND uninterrupted diffusion strip Digital IC
Consistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph X C X i V DD j Digital IC GND Euler path: a path through all nodes in the graph such that each edge is visited once and only once C For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)
OI Logic Graph C X PUN D D C X =!((+) (C+D)) X V DD C D C D GND PDN Digital IC
OI Layout D C V DD X GND Some functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) Digital IC
VTC is Data-Dependent V GS = V V DS1 V GS1 = V M 3 M 4 D M S D M 1 F= Cint S 0 3 1 weaker PUN 0 1 0.5 /0.5 NMOS 0.5 /0.5 PMOS,: 0 -> 1 =1, :0 -> 1 =1, :0->1 The threshold voltage of M is higher than M 1 due to the body effect ( ) V Tn1 = V Tn0 V Tn = V Tn0 + ( ( F + V int ) - F ) since V S of M is not zero (when V = 0) due to the presence of Cint Digital IC
CMOS Properties Full rail-to-rail swing high noise margins not dependent upon device sizes ratioless lways a path to Vdd or Gnd low output impedance zero steady-state input current high input resistance No direct path steady state no static power Propagation delay function of load capacitance and resistance of transistors Digital IC 0
Static CMOS logic CMOS static characteristic CMOS propagate delay Large fan-in technology Logic effort CMOS power analysis Digital IC 1
Delay Definitions t pdr : t pdf : t pd : t r : t f : fall time Digital IC Slide
Delay Definitions t pdr : rising propagation delay From input to rising output crossing V DD / t pdf : falling propagation delay From input to falling output crossing V DD / t pd : average propagation delay(max-time) t pd = (t pdr + t pdf )/ t r : rise time From output crossing 0.1 V DD to 0.9 V DD t f : fall time From output crossing 0.9 V DD to 0.1 V DD Digital IC Slide 3
Delay Definitions t cdr : rising contamination delay Minimum time from input to rising output crossing V DD / t cdf : falling contamination delay Minimum time from input to falling output crossing V DD / t cd : average contamination delay(min-time) Minimum time from input crossing 50% to the output crossing 50% t pd = (t cdr + t cdf )/ Digital IC Slide 4
Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! ut simulations take time to write.0 1.5 1.0 (V) 0.5 V in t pd f = 66ps t pd V out r = 83ps 0.0 0.0 00p 400p 600p 800p 1n t(s) Digital IC Slide 5
Why we need estimation? We have timing analyzer at different levels The architectural/micro-architectual level Logic level Circuit level Layout level GIGO(Garbage In Garbage Out)! Simulation could only tell how fast, it could not tell how to modify the circuit Digital IC Slide 6
Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation ut easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches Digital IC Slide 7
Input Pattern Effects on Delay R p R n R n R p C L C int Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 R p / C L one input goes low delay is 0.69 R p C L High to low transition both inputs go high delay is 0.69 R n C L Digital IC 8
Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd i to source i nodes i R C R R C... R R... R C 1 1 1 1 R 1 R R 3 R N N N C 1 C C 3 C N Digital IC Slide 9
RC Delay Models Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance R, capacitance C Capacitance proportional to width Resistance inversely proportional to width g d k s g d R/k kc s kc kc g d k s g s kc R/k kc kc d Digital IC Slide 30
Switch Delay Model R p R p R p R eq R p R n C L R n C L R p C int R n NND C int INV R n R n C L NOR Digital IC 31
Example: 3-input NND Sketch a 3-input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) Digital IC Slide 3
Example: 3-input NND Sketch a 3-input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) Digital IC Slide 33
Example: 3-input NND Sketch a 3-input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) 3 3 3 Digital IC Slide 34
3-input NND Caps nnotate the 3-input NND gate with gate and diffusion capacitance. C C C C C C C C C 3C 3C 3C 3 3 3 3C 3C 3C 3C Digital IC Slide 35
3-input NND Caps nnotate the 3-input NND gate with gate and diffusion capacitance. 5C 5C 5C 3 3 3 9C 3C 3C Digital IC Slide 36
Example: -input NND Estimate worst-case rising and falling delay of - input NND driving h identical gates. x Y h copies Digital IC Slide 37
Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies Digital IC Slide 38
Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R Y (6+4h)C tpdr Digital IC Slide 39
Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R Y (6+4h)C t pdr ln (6 4h) RC Digital IC Slide 40
Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies Digital IC Slide 41
Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C tpdf Digital IC Slide 4
Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C t pdf R ln C ln (7 4h) RC [(6 R 4h) C ]( R ) Digital IC Slide 43
Delay Components Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance Digital IC Slide 44
Contamination Delay est-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously x 6C C Y 4hC R R Y (6+4h)C tcdr 3 h RC Digital IC Slide 45
Layout Comparison Which layout is better? V DD V DD Y Y GND GND Digital IC Slide 46
Diffusion Capacitance assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NND3 layout shares one diffusion contact Reduces output capacitance by C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion C C Isolated Contacted Diffusion 3 3 7C 3C 3C 3C 3C 3 3C Digital IC Slide 47
Transistor Sizing R p R p 4 R p R n C L 4 R p C int R n Cint 1 R n R n 1 C L Digital IC 48
Transistor Sizing a Complex CMOS Gate 4 3 C 8 8 6 6 D 4 6 OUT = D + ( + C) D 1 C Digital IC 49
Fan-In Considerations C D C D C 3 C C 1 C L Distributed RC model (Elmore delay) t phl = 0.69 R eqn (C 1 +C +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case Digital IC 50
t p (psec) t p (NND)as a function of fan-in 150 1000 quadratic 750 500 t phl t p 50 0 t pl 4 6 8 10 1 14 16 H linear fan-in Gates with a fan-in greater than 4 should be avoided Digital IC 51
t p (psec) t p as a function of fan-out t p NOR t p NND ll gates have the same drive current t p INV Slope is a function of driving strength 4 6 8 10 1 14 16 eff. fan-out Digital IC 5
t p as a function of fan-in and fan-out Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to C L t p = a 1 F I + a F I + a 3 F O Digital IC 53
Voltage [V] Delay Dependence on Input Patterns 3.5 1.5 1 0.5 共享电容放电 ==1 0 =1 0, =1 =1, =1 0 Input Data Pattern Delay (psec) ==0 1 69(max) =1, =0 1 6 = 0 1, =1 50 ==1 0 35(min) =1, =1 0 76 0-0.5 0 100 00 300 400 time [ps] 共享电容充电 = 1 0, =1 57 NMOS = 0.5 m/0.5 m PMOS = 0.75 m/0.5 m C L = 100 ff Digital IC 54
Static CMOS logic CMOS static characteristic CMOS propagate delay Large fan-in technology Logic effort CMOS power analysis Digital IC 55
How to choose design techniques for large fan-in Larger parasitic capacitor, larger load to the preceding gate Load is dominated by fan-out, the design technique makes sense Solution Progressive transistor sizing Transistor ordering lternative logic structures Isolating fan-in from fan-out using buffer insertion Digital IC 56
Transistor ordering critical path critical path In 3 1 In 1 In 1 0 1 M3 C L M3 In 1 M C charged M C In M1 charged 3 1 M1 C 1 C 1 charged 0 1 In 1 charged C L discharged discharged delay determined by time to discharge C L, C 1 and C delay determined by time to discharge C L Digital IC 57
Progressive sizing Distributed RC line M1 > M > M3 > > MN the closest to the output is the smallest Can reduce delay by more than 0%; decreasing gains as technology shrinks Digital IC 58
lternative logic structures F = CDEFGH Digital IC 59
Isolating fan-in from fan-out using buffer insertion Large fan-in Large fan-out isolating C L C L Digital IC 60