19-34; Rev ; 1/ 1-Bit Low-Power, -Wire, Serial General Description The is a single, 1-bit voltage-output, digital-toanalog converter () with an I C -compatible -wire interface that operates at clock rates up to 4kHz. The device operates from a single.7v to 5.5V supply and draws only 1µA at = 3.6V. A low-power powerdown mode decreases current consumption to less than 1µA. The features three software-selectable power-down output impedances: 1kΩ, 1kΩ, and high impedance. Other features include an internal precision Rail-to-Rail output buffer and a power-on reset circuit that powers up the in the 1kΩ power-down mode. The features a double-buffered I C-compatible serial interface that allows multiple devices to share a single bus. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The minimizes digital noise feedthrough by disconnecting the clock () signal from the rest of the device when an address mismatch is detected. The is specified over the extended temperature range of -4 C to +85 C and is available in a space-saving 6-pin SOT3 package. Refer to the MAX5811 for the 1-bit version. Applications Digital Gain and Offset Adjustments Programmable Voltage and Current Sources Programmable Attenuation VCO/Varactor Diode Control Low-Cost Instrumentation Battery-Operated Equipment Typical Operating Circuit Ultra-Low Supply Current 1µA at VDD = 3.6V 13µA at = 5.5V 3nA Low-Power Power-Down Mode Single.7V to 5.5V Supply Voltage Features Fast 4kHz I C-Compatible -Wire Serial Interface Schmitt-Trigger Inputs for Direct Interfacing to Optocouplers Rail-to-Rail Output Buffer Amplifier Three Software-Selectable Power-Down Output Impedances 1kΩ, 1kΩ, and High Impedance Read-Back Mode for Bus and Data Checking Power-On Reset to Zero Miniature 6-Pin SOT3 Package PART Ordering Information TEMP RANGE PIN- PACKAGE TOP MARK LEUT -4 C to +85 C 6 SOT3 AAYT MEUT -4 C to +85 C 6 SOT3 AAYV NEUT -4 C to +85 C 6 SOT3 AAYX PEUT -4 C to +85 C 6 SOT3 AAYZ Selector Guide appears at end of data sheet. Functional Diagram appears at end of data sheet. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. I C is a trademark of Philips Corporation. Pin Configuration µc TOP VIEW R P R P R S 1 6 R S GND 5 ADD R S 3 4 R S SOT3 Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-69-464, or visit Maxim s website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS,, to GND...-.3V to +6V, ADD to GND...-.3V to +.3V Maximum Current Into Any Pin...5mA Continuous Power Dissipation (T A = +7 C) 6-Pin SOT3 (derate 9.1mW above +7 C)...77mW ELECTRICAL CHARACTERISTICS Operating Temperature Range...-4 C to +85 C Maximum Junction Temperature...+15 C Storage Temperature Range...-65 C to +15 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ( = +.7V to +5.5V, GND =, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = +5V, T A = +5 C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (Note ) Resolution N 1 Bits Integral Nonlinearity INL (Note 3) ± ±16 LSB Differential Nonlinearity DNL Guaranteed monotonic (Note 3) ±1 LSB Zero-Code Error ZCE Code = hex, =.7V ±6 ±4 mv Zero-Code Error Tempco.3 ppm/ o C Gain Error GE Code = FFF hex -.8-3 %FS Gain-Error Tempco.6 ppm/ o C PUT Output Voltage Range No load (Note 4) V DC Output Impedance Code = 8 hex 1. Ω Short-Circuit Current Wake-Up Time Output Leakage Current DIGITAL INPUTS (, ) = 5V, V = full scale (short to GND) 4. = 3V, V = full scale (short to GND) 15.1 = 5V 8 = 3V 8 Power-down mode = high impedance, = 5.5V, V = or GND ma µs ±.1 ±1 µa Input High Voltage V IH.7 V Input Low Voltage V IL.3 V Input Hysteresis.5 V Input Leakage Current Digital inputs = or ±.1 ±1 µa Input Capacitance 6 pf DIGITAL PUT () Output Logic Low Voltage V OL I SINK = 3mA.4 V Three-State Leakage Current I L Digital inputs = or ±.1 ±1 µa Three-State Output Capacitance 6 pf DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR.5 V/µs Voltage-Output Settling Time To 1/LSB code 4 hex to C hex or C hex to 4 hex (Note 5) 4 1 µs
ELECTRICAL CHARACTERISTICS (continued) ( = +.7V to +5.5V, GND =, R L = 5kΩ, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = +5V, T A = +5 C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital Feedthrough Code = hex, digital inputs from to. nv-s Digital-to-Analog Glitch Impulse POWER SUPPLIES Major carry transition, code = 7FF hex to 8 hex and 8 hex to 7FF hex Note 1: All devices are 1% production tested at T A = +5 C and are guaranteed by design for T A = T MIN to T MAX. Note : Static specifications are tested with the output unloaded. Note 3: Linearity is guaranteed from codes 115 to 3981. Note 4: Offset and gain error limit the FSR. Note 5: Guaranteed by design. Not production tested. 1 nv-s Supply Voltage Range.7 5.5 V Supply Current with No Load All digital inputs at or = 3.6V 1 17 All digital inputs at or = 5.5V 13 19 Power-Down Supply Current All digital inputs at or = 5.5V.3 1 µa TIMING CHARACTERISTICS (Figure 1) Serial Clock Frequency f 4 khz Bus Free Time Between STOP and START Conditions t BUF 1.3 µs START Condition Hold Time t HD, STA.6 µs Pulse Width Low t LOW 1.3 µs Pulse Width High t HIGH.6 µs Repeated START Setup Time t SU, STA.6 µs Data Hold Time t HD, DAT.9 µs Data Setup Time t SU, DAT 1 ns and Receiving Rise Time and Receiving Fall Time t r (Note 5) 3 ns t f (Note 5) 3 ns Transmitting Fall Time t f (Note 5) +.1C b 5 ns STOP Condition Setup Time t SU-STO.6 µs Bus Capacitance C b (Note 5) 4 pf Maximum Duration of Suppressed Pulse Widths t SP 5 ns µa 3
( = +5V, R L = 5kΩ, T A = +5 C.) INTEGRAL NONLINEARITY (LSB) 4 3 1-1 - -3 INTEGRAL NONLINEARITY vs. INPUT CODE toc1 INTEGRAL NONLINEARITY (LSB) 5 4 3 1 INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE Typical Operating Characteristics toc INTEGRAL NONLINEARITY (LSB) 5 4 3 1 INTEGRAL NONLINEARITY vs. TEMPERATURE toc3-4 14 48 37 496 INPUT CODE.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) -4-15 1 35 6 85 TEMPERATURE ( C) DIFFERENTIAL NONLINEARITY (LSB) 1..75.5.5 -.5 -.5 -.75 DIFFERENTIAL NONLINEARITY vs. INPUT CODE toc4 DIFFERENTIAL NONLINEARITY (LSB) -.5 -.5 -.75 DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE toc5 DIFFERENTIAL NONLINEARITY (LSB) -.5 -.5 -.75 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE toc6-1. 14 48 37 496 INPUT CODE -1..7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) -1. -4-15 1 35 6 85 TEMPERATURE ( C) ZERO-CODE ERROR (mv) 1 8 6 4 ZERO-CODE ERROR vs. SUPPLY VOLTAGE.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) MAX851 toc7 ZERO-CODE ERROR (mv) 1 8 6 4 ZERO-CODE ERROR vs. TEMPERATURE -4-15 1 35 6 85 TEMPERATURE ( C) toc8 GAIN ERROR (%FSR) -. -1.6-1. -.8 -.4 GAIN ERROR vs. SUPPLY VOLTAGE.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) toc9 4
( = +5V, R L = 5kΩ, T A = +5 C.) GAIN ERROR (%FSR) SUPPLY CURRENT (µa) -. -1.6-1. -.8 -.4 1 1-4 8 6 4 GAIN ERROR vs. TEMPERATURE -15 1 35 6 85 TEMPERATURE ( C) SUPPLY CURRENT vs. INPUT CODE 819 1638 457 376 496 INPUT CODE toc1 toc13 PUT VOLTAGE (V) SUPPLY CURRENT (µa) Typical Operating Characteristics (continued) 6 5 4 3 1 1 95 9 85 PUT VOLTAGE vs. PUT SOURCE CURRENT (NOTE 6) CODE = FFF hex 4 6 8 1 PUT SOURCE CURRENT (ma) CODE = FFF hex SUPPLY CURRENT vs. TEMPERATURE 8-4 -15 1 35 6 85 TEMPERATURE ( C) toc11 toc14 PUT VOLTAGE (V) SUPPLY CURRENT (µa).5. 1.5 1..5 1 9 8 7 PUT VOLTAGE vs. PUT SINK CURRENT (NOTE 6) CODE = 4 hex 4 6 8 1 PUT SINK CURRENT (ma) SUPPLY CURRENT vs. SUPPLY VOLTAGE 6 CODE = FFF hex 5.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) toc1 toc15 POWER-DOWN SUPPLY CURRENT (na) 5 4 3 POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = -4 C T A = +5 C T A = +85 C 1 Z = HIGH IMPEDANCE.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) toc16 POWER-UP GLITCH 1µs/div toc17 5V 1mV/div EXITING SHUTDOWN µs/div C LOAD = pf CODE = 8 hex toc18 5mV/div Note 6: The ability to drive loads less than 5kΩ is not implied. 5
( = +5V, R L = 5kΩ, T A = +5 C.) MAJOR CARRY TRANSITION (POSITIVE) toc19 Typical Operating Characteristics (continued) MAJOR CARRY TRANSITION (NEGATIVE) toc SETTLING TIME (POSITIVE) toc1 5mV/div 5mV/div 5mV/div C LOAD = pf R L = 5kΩ µs/div CODE = 7FF hex TO 8 hex C LOAD = pf R L = 5kΩ µs/div CODE = 7FF hex TO 8 hex C LOAD = pf µs/div CODE = 4 hex to C hex SETTLING TIME (NEGATIVE) toc DIGITAL FEEDTHROUGH toc3 V/div 5mV/div mv/div C LOAD = pf µs/div CODE = C hex to 4 hex C LOAD = pf f = 1kHz 4µs/div CODE = hex 6
Pin Description PIN NAME FUNCTION 1 Power Supply and Reference Input GND Ground 3 Bidirectional Serial Data I/O 4 Serial Clock Line 5 ADD Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to. 6 Analog Output Detailed Description The is a 1-bit, voltage-output with an I C/SMBus-compatible -wire interface. The device consists of a serial interface, power-down circuitry, input and registers, a 1-bit resistor string, unitygain output buffer, and output resistor network. The serial interface decodes the address and control bits, routing the data to either the input or register. Data can be directly written to the register immediately updating the device output, or can be written to the input register without changing the output. Both registers retain data as long as the device is powered. Operation The uses a segmented resistor string architecture, which saves power in the overall system and guarantees output monotonicity. The s input coding is straight binary with the output voltage given by the following equation: V D V REF ( ) = N where N = 1(bits), and D = the decimal value of the input code ( to 495). Output Buffer The analog output is buffered by a precision unity-gain follower that slews.5v/µs. The buffer output Table 1. Power-Down Command Bits swings rail-to-rail and is capable of driving 5kΩ in parallel with pf. The output settles to ±.5LSB within 4µs. Power-On Reset The features an internal power-on-reset (POR) circuit that initializes the device upon power-up. The registers are set to zero-scale and the device is powered down with the output buffer disabled and the output pulled to GND through the 1kΩ termination resistor. Following power-up, a wake-up command must be initiated before conversions are performed. Power-Down Modes The has three software-controlled, lowpower, power-down modes. All three modes disable the output buffer and disconnect the resistor string from, reducing supply current draw to 3nA. In power-down mode, the device output is high impedance. In power-down mode 1, the device output is internally pulled to GND by a 1kΩ termination resistor. In power-down mode, the device output is internally pulled to GND by a 1kΩ termination resistor. Table 1 shows the power-down mode command words. Upon wake-up, the output is restored to its previous value. Data is retained in the input and registers during power-down mode. Digital Interface The features an I C/SMBus-compatible -wire interface consisting of a serial data line () POWER-DOWN COMMAND BITS PD1 PD MODE/FUNCTION Power-up device. output restored to previous value. 1 Power-down mode. Powers down device with output floating. 1 Power-down mode 1. Powers down device with output terminated with 1kΩ to GND. 1 1 Power-down mode. Powers down device with output terminated with 1kΩ to GND. 7
t LOW t SU, DAT t HIGH t HD, DAT t SU, STA t HD, STA tsp t SU, STO t BUF t HD, STA t R t F START CONDITION Figure 1. Two-Wire Serial lnterface Timing Diagram and a serial clock line (). The is SMBus compatible within the range of =.7V to 3.6V. and facilitate bidirectional communication between the and the master at rates up to 4kHz. Figure 1 shows the -wire interface timing diagram. The is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master, typically a microcontroller, initiates data transfer on the bus and generates to permit that transfer. A master device communicates to the by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (S r ) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. The and drivers are open-drain outputs, requiring a pullup resistor (5Ω or greater) to generate a logic high voltage (see the Typical Operating Circuit). Series resistors R S are optional. These series resistors protect the input stages of the from high-voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each clock cycle. The data on must remain stable during the high period of the clock pulse. Changes in while the is high are control signals (see the START and STOP Conditions section). and idle high when the I C bus is not busy. START and STOP Conditions When the serial interface is inactive, and idle high. A master device initiates communication by issuing a START condition. A START condition is a high-to- REPEATED START CONDITION STOP CONDITION S Sr P Figure. START/STOP Conditions STOP Figure 3. Early STOP condition START LEGAL STOP CONDITION START ILLEGAL STOP ILLEGAL EARLY STOP CONDITION START CONDITION 8
low transition on with high. A STOP condition is a low-to-high transition on while is high (Figure ). A START condition from the master signals the beginning of a transmission to the. The master terminates transmission by issuing a not acknowledge followed by a STOP condition (see the Acknowledge Bit section). The STOP condition frees the bus. If a repeated START condition (S r ) is generated instead of a STOP condition, the bus remains active. When a STOP condition or incorrect address is detected, the internally disconnects from the serial interface until the next START condition, minimizing digital noise and feedthrough. Early STOP Conditions The recognizes a STOP condition at any point during transmission except when a STOP condition occurs in the same high pulse as a START condition (Figure 3). This condition is not a legal I C format, at least one clock pulse must separate any START and STOP conditions. Repeated START Conditions A repeated start (S r ) condition might indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. Sr also can be used when the bus master is writing to several I C devices and does not want to relinquish control of the bus. The serial interface supports continuous write operations with or without an Sr condition separating them. Continuous read operations require Sr conditions because of the change in direction of data flow. Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving device. The generates an ACK when receiving an address or data by pulling low during the ninth clock period. When transmitting data, the waits for the receiving device to generate an ACK. Monitoring ACK allows detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address (Figure 4). When idle, the waits for a START condition followed by its slave address. The serial interface compares each address Table. IC Slave Addresses PART V ADD DEVICE ADDRESS (A 6...A ) L GND 1 L 1 1 M GND 1 1 M 1 11 N GND 11 1 N 11 11 P GND 11 1 P 11 11 S A6 A5 A4 A3 A A1 A R/W Figure 4. Slave Address Byte Definition C3 C C1 C D11 D1 D9 D8 Figure 5. Command Byte Definition value bit-by-bit, allowing the interface to power-down immediately when an incorrect address is detected. The LSB of the address word is the Read/Write (R/W) bit. R/W indicates whether the master is writing to or reading from the (R/W = selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the issues an ACK by pulling low for one clock cycle. The has eight factory/user-programmed addresses (Table ). Address bits A6 through A1 are preset; A is controlled by ADD. Connecting ADD to GND sets A =. Connecting ADD to VDD sets A = 1. This feature allows up to eight s to share a bus. Write Data Format In write mode (R/W = ), data that follows the address byte controls the (Figure 5). Bits C3 C configure the (Table 3). Bits D11 D are data. Input and registers update on the falling edge of during the acknowledge bit. Should the write cycle be prematurely aborted, data will not be updated and the write cycle must be repeated. Figure 6 shows two example write data sequences. 9
Table 3. Command Byte Definitions SERIAL INPUT C3 C C1 C D11/PD1* D1/PD* D9 D8 1 1 1 1 1 1 1 1 1 1 1 1 X X XX FUNCTION Load with a new data from the following data byte and update output simultaneously as soon as data is available from the serial bus. The and input registers are updated with the new data. Load input register with the data from the following data byte. output remains unchanged. Load input register with data from the following data byte. Update output to the previously stored data. Update output from input register. The device will ignore any new data. 1 X X X X XX Read data request. Data bits are ignored. The contents of the register are available on the bus. 1 X X XX Powers up device. 1 X X 1 XX 1 X X 1 XX Power-down mode. Powers down device with output floating. Power-down mode 1. Powers down device with output terminated with 1kΩ to GND. Power-down mode. Powers down device with output 1 X X 1 1 XX terminated with 1kΩ to GND. *When C3 = and C = 1, data bits D11 and D1 write to the power-down registers (PD1 and PD). X = Don t care. S LSB LSB A6 A5 A4 A3 A A1 A R/W ACK C3 C C1 C D11 D1 D9 D8 ACK LSB D7 D6 D5 D4 D3 D D1 D ACK P EXAMPLE WRITE SEQUENCE LSB LSB S A6 A5 A4 A3 A A1 A R/W ACK C3 C X X PD1 PD X X ACK P Figure 6. Example Write Command Sequences EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE 1
LSB LSB R/W S A6 A5 A4 A3 A A1 A ACK C3 C X X X X X X = Sr A6 A5 A4 A3 A A1 A BYTES GENERATED BY MASTER DEVICE LSB R/W = 1 ACK LSB X X PD1 PD D11 D1 D9 D8 ACK ACK BYTES GENERATED BY ACK GENERATED BY MASTER DEVICE LSB D7 D6 D5 D4 D3 D D1 D ACK P Figure 7. Example Read Word Data Sequence IN I C Compatibility The is compatible with existing I C systems. and are high-impedance inputs; has an open drain that pulls the data line low during the ninth clock pulse. The Typical Operating Circuit shows a typical I C application. The communication protocol supports standard I C 8-bit communications. The general call address is ignored. The address is compatible only with the 7-bit I C addressing protocol. Tenbit address formats are not supported. MAX63/ MAX65 GND Read Data Format In read mode (R/W = 1), the writes the contents of the register to the bus. The direction of data flow reverses after the address acknowledge by the. The device transmits the first byte of data, waits for the master to acknowledge, and then transmits the second byte. Figure 7 shows an exampleread data sequence. Figure 8. Powering the from An External Reference GND Digital Feedthrough Suppression When the detects an address mismatch, the serial interface disconnects the signal from the core circuitry. This minimizes digital feedthrough caused by the signal on a static output. The serial interface reconnects the signal when a valid START condition is detected. Applications Information Powering the Device From an External Reference The uses the VDD as the voltage reference. Any power-supply noise is directly coupled to the device output. The circuit in Figure 8 uses a precision voltage reference to power the, isolating the device from any power-supply noise. Powering the in such a manner greatly improves overall performance, especially in noisy systems. The MAX63 (3V, 75ppm/ C) or the MAX65 (5V, 75ppm/ C) precision voltage references are ideal choices because of the low power requirements of the. Digital Inputs and Interface Logic The -wire digital interface is I C and SMBuscompatible. The two digital inputs ( and ) load 11
INPUT REGISTER MUX AND REGISTER 1-BIT Functional Diagram RESISTOR NETWORK SERIAL INTERFACE POWER-DOWN CIRCUITRY ADD GND the digital input serially into the. Schmitt-trigger buffered inputs allow slow transition interfaces such as optocouplers to interface directly to the device. The digital inputs are compatible with CMOS logic levels. Power-Supply Bypassing and Ground Management Careful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the power supply ground is short and low impedance. Bypass with a.1µf capacitor to ground as close to the device as possible. TRANSISTOR COUNT: 717 PROCESS: BiCMOS Chip Information Selector Guide PART LEUT MEUT NEUT PEUT ADDRESS 1 X 1 1X 11 1X 11 1X 1
Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 1 San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 13 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.