ECE 3400 Project By: Josh Skow and Bryan Cheung
Design Approach Goal: Design a 3 stage amplifier to amplify an acoustic input signal from a piezoelectric microphone Amplifier should only amplify frequencies in the audible range (Desired passband range 20Hz-20kHz) while driving a low impedance load First stage: Common Emitter (BJT requirement) o Since BJT was required, we chose the common emitter configuration for its high voltage gain and its high input impedance Second stage: Common Source o In order to reach the target gain of 1000, we chose the common source configuration to further boost the voltage gain while providing high input impedance when loading the previous stage Third stage: Common Drain (high Rin, unity gain, high current gain) o To provide enough current to drive the 100-ohm output load, we chose the Common Drain follower configuration for its high current gain and high input impedance when loading the previous stage The design process was as follows: o Analyze bias-resistor networks for each transistor amplifier stage to generalize bias points o Choose a desired design parameter o Change bias points to obtain resistor values that will achieve the specified design parameter o Simulate each individual stage to verify bias point, midband gain and bandwidth, and clipping levels o Combine the stages with AC coupling capacitors to verify overall amplifier specifications
Transistor Configuration After choosing amplifier topologies, we handanalyzed the 4-resistor bias networks to find general equations for bias points of the transistors Then, we set up these equations in Mathcad documents. We used the transistor terminal voltages as our variable inputs, letting the software calculate the bias-resistor values appropriate for our desired bias point Using these equations, we were able to ensure that the transistors stayed biased in the appropriate modes while also meeting design criteria Each amplifier stage was designed independently; the effects of the preceding and following stages were modeled with a resistor representing the respective input and output impedances Figure 1. Mathcad bias point equations for the common emitter stage
Complete Amplifier Schematic Multisim was used to model and simulate the amplifier stages individually and then to model the entire circuit The schematic shows the chosen resistor and capacitor values that best satisfy the design requirements Large AC-coupling capacitors are used between stages to isolate the biasing of each stage and remove any DC offset in the output signal M1 Figure 2. Complete 3-stage amplifier design
Gain Since the first stage needed to have a high input impedance, we sacrificed gain in the first stage to improve input impedance and focused on having more gain in the second stage The gains achieved for each stage are as follows: o Stage 1: 15.52 V/V o Stage 2: 65.06 V/V o Stage 3: 0.935 V/V The total gain is 944.72 V/V, which is below the ideal gain of 1000 V/V. The total gain had to be sacrificed in order to provide a suitable output signal. A higher gain produced significant clipping and distortion which would result in an unusable output. The total gain when removing the one bypass capacitor is: 0.012 V/V Figure 3. Gain of each individual stage and total gain. Common Emitter gain is stage 1 in red, Common Source gain is stage 2 in blue, Common Drain gain is stage 3 in purple, and the total system gain is green
Input and Load Impedance We achieved a large input impedance by choosing two large base biasing resistors, as well as choosing a moderately sized source resistor that is multiplied by the forward-beta as seen through the base The load impedance was achieved by simply putting a bypass capacitor in front of the 100 ohm load impedance, and putting this 100 ohm load in parallel with a biasing resistor at the output of the common drain Figure 4. Formula for calculating the input impedance. Input impedance of the system was 1.1MΩ, achieving the given design parameter Figure 5. First-stage (Common-emitter) input impedance
Bandwidth The desired bandwidth of 20 to 20kHz was achieved by incorporating a passive bandpass filter, isolated by the third amplifier stage We designed a passive low-pass filter (fc=20khz) by connecting a shunt capacitor before the third amplifier stage. The capacitance was chosen to be C=82.3pF by calculating the time constant using the impedance the capacitor sees looking into the third stage. We designed a passive high-pass filter (fc=20hz) by adding a capacitor in series with the 100-ohm load. The capacitance was chosen to be C=79.6uF by calculating the time constant using the impedance of the load The achieved cutoff frequencies were: o Lower cutoff: 19.55 Hz o Upper cutoff:20.87 khz o Bandwidth: 20.85 khz Figure 6. 3-stage amplifier frequency response. Cursors indicate the -3dB frequencies of 19.55Hz and 20.87kHz
Input & Output Voltage Range The design parameter for input voltage range is a 5 mv peak-topeak signal into the amplifier without any clipping or distortion at the output The output voltage range would ideally be from 2.5 to -2.5 V We were unable to fully reach these values, partially due to too small of voltage gain In order to obtain a larger input and output voltage range, we chose bias points of the transistors that allowed for a wider range of voltages to allow the transistors to stay in either forward active or saturation mode and operate correctly Figure 7. The input voltage of the amplifier begins clipping at approximately 6.4 mv peak to peak, and the clipping output is shown above Figure 8. The output voltage range of the amplifier goes from 2.012 V to -2.36 V
Rise and Fall Time The rise and fall time of the amplifier should be designed to be as small as possible We measured the rise and fall time of our amplifier by applying a step input with a rise/fall time of 0 sec and measured the time it took the output signal to reach 90% amplitude from 10% amplitude The measured rise time of our amplifier was 9.3uSec and the fall time was 11.6uSec. Figure 9. Measured rise time (left) and fall time (right) of 3-stage amplifier
Distortion The total distortion of the amplifier should be designed to be as low as possible We measured the distortion of our amplifier by applying 2.5 mvpk, 300 Hz input signal to the amplifier and running a Fourier Analysis on the output at a fundamental frequency of 300 Hz The Total Harmonic Distortion of our amplifier was measured to be 6.92%, the majority of which comes from the second harmonic As the gain of the amplifier increases, the output voltages nearly reach the clipping levels, so slight distortion of the output is unavoidable at higher voltage levels Figure 10. Fourier analysis of 3-stage amplifier
PSRR + Power Consumption The power consumption of the circuit is measured by taking the voltage of the two power supplies, Vdd and Vss, and multiplying by the sum of the current through each biasing branch Our power consumption is.791 W total, less than the 1 W design parameter PSRR is measured by shorting the input voltage source and measuring the output voltage while varying the power supply voltages slightly Our PSRR+ is : 0.481 Our PSRR- is: 0.519 Figure 11. The simulation formula to determine the power consumption. Figure 12. The PSRR calculations in MathCAD. The power supplies were offset by.2 V and the output voltage offset was simulated finding the DC operating point at the node before the load decoupling capacitor.